JP3249270B2 - Pulse sampling circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex communication line system for exchanging information by connecting a plurality of devices ( hereinafter referred to as nodes ) separated from each other, for example, a door lock control system and a light control system in a vehicle. The present invention relates to a pulse sampling circuit of a multiplex communication bus in each node connected to a line, which is used for a network such as a navigation system and a centralized management system of a vending machine.

[0002]

2. Description of the Related Art FIG. 2 is a schematic block diagram of a conventional multiplex communication line system. As a bit format of transmission data used for multiplex communication, there are an NRZ system without modulation and a PWM system with pulse width modulation. Here, the PWM method will be described as an example.

This multiplex communication line system has a differential bus structure in which a network is constituted by two wires (twisted pair lines), and a BUS (-) line 1 and a B
US (+) line 2 is provided. The BUS (-) line 1 is connected to the power supply potential VDD via the pull-up resistor 3 and the BUS (+)
The lines 2 are respectively connected to a ground potential GND via a pull-down resistor 4. BUS (-) line 1 and BUS
A plurality of devices (nodes) 10-1, 10-2,... , 10-n are connected to the dual wire of the (+) line 2 by wired and logic. Each node 10-1 to 10-
n is a receiving circuit 11 for taking in data on the BUS (-) line 1 and BUS (+) line 2, a PWM pulse demodulation circuit 12 for sampling a PWM pulse and outputting various decode signals according to the pulse width. , The central processing unit (Central Proces
sing Unit (hereinafter referred to as CPU) 13 and CPU 13
Is provided with a PWM modulation circuit 14 for pulse-width-modulating the processing result and outputting the result, and is configured to be able to transmit and receive data.

The receiving circuit 11 has a BUS (-) line 1 and a B
Receives digital data on US (+) line 2 and performs PWM
This circuit is provided to the pulse demodulation circuit 12, and the output terminal is P
It is connected to the WM pulse demodulation circuit 12. The PWM pulse demodulation circuit 12 is a circuit that captures a PWM pulse on the multiplex communication line and outputs a decode signal according to the width of the PWM pulse, and an output terminal is connected to the CPU 13. The CPU 13 controls the PWM pulse demodulation circuit 12
The output terminal is connected to the PWM modulation circuit 14.
The PWM modulation circuit 14 includes transistors 15-1 to 15-15
-N, a transmission data generating circuit (not shown) for generating transmission data for driving each of 16-1 to 16-n, an encoder circuit, and the like. -1 to 15
−n, 16-1 to 16-n. Each of the transistors 15-1 to 15-n and 16-1 to 1
6-n are transistors which are driven by the output control signals of the respective PWM modulation circuits 14 and output digital data to the BUS (-) line 1 and the BUS (+) line 2, and one of the transistors 15-1 to 15-1 The 15-n collector is connected to the BUS (-) line 1 and the emitter is connected to GND. The other transistors 16-1 to 16-n
The emitter is VDD and the collector is the BUS (+) line 2
, Respectively.

FIG. 3 shows a PWM pulse demodulation circuit 1 shown in FIG.
2 is a schematic configuration diagram of FIG. This PWM pulse demodulation circuit 1
2 has a PWM pulse detection circuit 20 for detecting a change from a bus idle state (passive state) to an active state (dominant state) on the multiplex communication line. The PWM pulse detection circuit 20 includes a delay flip-flop (hereinafter, referred to as D-FF) 21 and a two-input AN.
A D gate 22 is provided. PWM pulse detection circuit 20
Is the reset input terminal R of the ring counter 31.
It is connected to the. Ring counter 31 operates by the clock signal CLK, and a circuit for generating a sample clock signal in synchronization with the edge detection result of the PWM pulse detection circuit 20. The output of the ring counter 31 is P
Clock input terminals CK of the WM pulse demodulation sequencer 32
Connected as a sample clock signal on. PWM
Pulse demodulating sequencer 32 is to sample the PWM pulse IN with sample clock signal generated by the ring counter 31 for each predetermined small time unit, a circuit for outputting a decoded signal DS according to a combination of the results of the sample is there. Generally, the timing signal of the ring counter 31 is set near the center of a certain small time unit.

Next, the operation will be described. During normal operation, all the circuits in each of the nodes 10-1 to 10-n are in the operating state, and the BUS (-) line 1 and the BUS (-)
(+) The state of the line 2 is constantly monitored. For example, when transmitting data from the node 10-1 to the node 10-2, the transistors 15-1, 16 in the node 10-1
The address of the destination, the message data, and the like are output to the BUS (-) line 1 and the BUS (+) line 2 by -1. Then, in the node 10-2, the receiving circuit 11
Receiving the data on (-) line 1 and BUS (+) line 2,
The received signal is provided to the PWM pulse demodulation circuit 12. P
The WM pulse demodulating circuit 12 decodes the output of the receiving circuit 11 and inputs the decoded signal to the CPU 13. The CPU 13 determines whether the data from the node 10-1 is addressed to itself or not. If the data is addressed to itself, the CPU 13 continuously receives the message data.
Input to the M modulation circuit 14. The PWM modulation circuit 14 performs pulse width modulation on the response signal, and outputs
16-2 returns it to the node 10-1. here,
The bit information of the PWM bit is taken into the demodulation circuit ( this
This is referred to as sampling).

FIG . 9 shows one example of the general asynchronous communication.
Time chart indicating the sample clock signal for byte communication
It is. In general, in serial communication, to the asynchronous communication, communicating together baud rate communication nodes. Determining a start signal as a trigger a rise or fall of the data, to determine a <br/> sampling period tR sample point tc and the clock signal SCLK of one data bit when received in Figure 9, the serial data DA
TA is sampled by a predetermined number of data bits.

[0008] de Tasanpuru point is, data D
Sampling is performed at the position of the center of the data bit, avoiding a position near the ATA change point. For example, in the case where data bit switching occurs at a cycle 16 times the original cycle, after the time 8 times the original cycle elapses after the data bit switching occurs, that is, when the data is at the center position, the data DATA is switched. Is sampled, and then 1
Data DATA sequentially at 6 times interval (constant cycle)
Will be sampled. Synchronized in the manner of this, it captures the data DATA. The sampling period tR is configured by a ring counter or the like, and has a circuit configuration for obtaining sample points at a constant period.
Center punching of bits (data capture at the center position) is realized.

[0009]

However, the above structure
MaturesystemThen, if waveform dullness of transmission data is large,
That data cannot be sampled normallyTaskThere
Was.FIG. 8 shows a multiplex communication bus line circuit and signal waveforms.
FIG.For example,As shown in FIG.Multiple mail
Bus-eye in a no-signal state on a serial transmission path, etc.
Dollar status is resistancerIs pulled down and signal transmission starts
In the case of, drive with a driving element such as a transistor to go to “H”.
Start up and communicate. DriveAfter finishing the movement,,
Down resistancerTo return to "L" bus idle state
Is repeated to transmit a PWM bit or the like. Where multiplex
Communication busBSNode connected toA, B, ...increased
As transmission lines become longer, parasitic capacitance increases.,Ruda
Resistancer, The time to return to “L” becomes longer. Paraphrase
If the waveform changes to “H” driven by the transistor,
ChiResistor that rises quickly but is a passive elementrBus-like
The waveform that returns the state to "L" is delayed by parasitic capacitance.
Of FIG. As shown in FIG.

[0010]SoTherefore, the data bit
When center sampling is performed,Running out of "L"
To sample the bus level in a transient state
There was a problem.As a measure against thisOf FIG. I will show you
The sample point is located at the center position of the data bit.
From the data bit toward the last edge of the data bit.
It is possible to sample with a pull point. I
ScarecrowIn this case, the next bit
There is a disadvantage that the time margin t2 until
Hinders transmission control for sending bits
Problems arise. The present inventionSaidConventional technology had
As an assignment,When the capacitance value of the bus line increases, the transmission signal
Communication becomes impossible and communication cannot be performed normally.Point
And resolved pulseProviding sampling circuits.
is there.

[0011]

To solve the previous SL problems SUMMARY OF THE INVENTION The first aspect of the present invention, the pulse <br/> sampling circuit in a multiplex communication bus system coupled by wired AND logic Wherein the first sample point of the passive signal at the transition from the dominant signal output state indicating the active state of the signal logic to the passive signal output state is located on the trailing edge side of 1/2 of the transmission bit unit time, and Of the passive signal at the location where the passive signal at the predetermined location is continuously sampled.
Are arranged on the leading edge side in the transmission bit unit time from the first sample point.

A second invention relates to a pulse sampling circuit.
Here, the first, second and third timings are set according to the input signal.
Ring counter that outputs the sampling signal, pulse and sample
Clock signal and the sample clock signal.
Sampling of the pulse according to the
Output a predictive decoded signal according to the sample result.
The first, second and third ties.
Inputting the prediction signal and the predicted decoding signal,
When the first timing signal is input, the third timer
The second timing later than the timing of the timing signal
Output the sampling signal as the sample clock signal,
If the predictive decode signal is input, the second time
The third timing earlier than the timing signal
Select for outputting a signal as the sample clock signal
And is constituted by

[0013]

According to the first aspect of the present invention, since it is configured to pulse San <br/> pulling circuit as described above, the reception of the passive state of the stage of transition from dominant state of the bus on the data to the passive state, the transmission Sampling can be performed in the latter half of the bit unit, and stable sampling can be performed even if the waveform becomes dull.Also, for transmission control, for a predetermined portion in a communication frame that needs to be sampled earlier, For example, since there is no waveform dulling at a point where the passive state is continuously sampled, transmission control is easily and efficiently realized by sampling at a position before the sample point.

According to the second aspect, the ring counter
A first timing signal, a second timing signal,
A third timer earlier in timing than the second timing signal
When the imaging signal is output, these signals are
Given to. In the pulse demodulation circuit, the sample clock
Pulse sampling according to the signal and predictive decoding
And outputs it to the selector. In the selector,
When the timing signal 1 is input, the second timing
Pulse as a sample clock signal
When given to the demodulation circuit and the predicted decoded signal is input
Uses the third timing signal as a sample clock signal.
And outputs it to the pulse demodulation circuit. This allows
The demodulation circuit inputs the signal according to the sample clock signal.
Sampled pulse and output sample result
I do.

[0015]

FIG. 1 is a schematic block diagram of a PWM pulse sampling circuit showing an embodiment of the present invention. This PWM pulse sampling circuit detects a change of the PWM pulse IN from passive to dominant, and detects the PWM pulse IN.
An edge detection circuit 40 that outputs the output signal S42 is provided. The edge detection circuit 40 includes a D-FF 41 and a two-input A
An ND gate 42 is provided. The output side of the edge detection circuit 40 is connected to a reset input terminal RA of a ring counter 50 which is a timing signal generating means. The ring counter 50 detects the detection signal S42 of the edge detection circuit 40.
In synchronization with the reference clock signal C of the clock input terminal CK.
LK , the first, second, and third timing signals S50
c, a circuit for outputting S50b and S50a . This PWM pulse sampling circuit is a pulse demodulation circuit.
A certain PWM pulse demodulation sequencer 60 is provided. P
WM pulse demodulation sequencer 60 takes the PWM pulse IN, and the sample at the sample clock signal S71, a circuit for outputting a decode signal DS1 and the prediction decode signal DS2 in accordance with the combination of the sample results.

On the other hand, the output terminal Q of the ring counter 50
3 and Q5 are connected to input terminals I1 and I2 of the selector 71, respectively. The selector 71 is a circuit that selects one of the input terminals I1 and I2 according to the input signal of the select input terminal S and outputs the sample clock signal S71. The output terminal O of the selector 71 is connected to the clock input terminal CK of the PWM pulse demodulation sequencer 60. Prediction Deco <br/> over de output terminal PQ5~PQ7 PWM pulse demodulation sequencer 60, three-input OR gate 72
Through a reset set flip-flop (hereinafter, referred to as
RS-FF) 73 is connected to the set input terminal S. The output terminal Q6 of the ring counter 50 is connected to the reset input terminal R of the RS-FF 73.

[0017] R S-FF 73 is a circuit logic switches the output signal S73 by the input signal to the set input terminal S and the reset input terminal R. Output terminal Q of RS-FF73
Is connected to the select input terminal S of the selector 71,
If the S-FF 73 is set, the ring counter 5
The timing signal S50a output terminal Q3 of 0 to the clock input terminal CK of the PWM pulse demodulation sequencer 60, P
It is input as the sample clock signal S71 of the WM pulse IN . If the RS-FF 73 is reset,
Timing signal S at output terminal Q5 of ring counter 50
50b is input to the clock input terminal CK of the PWM pulse demodulation sequencer 60, and the sample clock signal of the PWM pulse IN
This is input as the number S71 .

[0018] Figure 4, one ring counter 50 in FIG. 1
It is a schematic block diagram showing an example . This ring counter 50
Means that the output signal of the first stage D-FF 51 is
2-58 are cascaded to sequentially input to, and is connected to the output signal of the D-FF 58 of the final stage is inputted to the input side of the first stage D-FF 51. Reset input terminal R
A is a set input terminal S of D-FF 51 and D-FF 5
Commonly connected to 2 to 58 reset input terminals R.
The clock input terminal CK of the ring counter 50 is DF
Commonly connected to clock input terminals CK of F51 to F58.

[0019] FIG. 5 is a configuration diagram schematically illustrating an example of a PWM pulse demodulation sequencer 60 in Fig. This PWM
The pulse demodulation sequencer 60 includes a state control circuit 6
1 , status latch circuit 62 , decode output circuit 63,
It has a measurement decoding output circuit 64 . State control circuit 61 includes a Control input terminal q1~q11 and PWM pulse input terminal PWM, PWM pulses IN
, And changes the state of the output signals D1 to D11 according to the output signal of the state latch circuit 62. State latch circuit 62 includes a D-FF62-1~62-11, the reset input terminal R of the D-FF 62- 1~ 62- 11 are commonly connected to the reset input terminal R of the sequencer 60. D -FF 62- 1~ 62- 11 of the clock input terminal CK, the sequencer 60 clock input terminal
Commonly connected to CK . 11 of the state latch circuit 62
Pieces of output terminal Q, controls <br/> roll input terminal q1~q11 state control circuit 61, an input terminal q1~q11 decoding output circuit 63, and the prediction decoded output circuit 64
Are connected to the input terminals q1 to q11.

The state latch circuit 62 is sampled at a sample clock signal S71 inputs the output signal D1~D11 state control circuit 61, an input terminal q1~q11 state control circuit 61 and the sample result, the decoded output a circuit for input to the input terminal q1~q11 circuit 6 3及 beauty prediction decoded output circuit 64. Also, de co <br/> over de output circuit 63 and the prediction decoding output circuit 64 is a circuit for outputting respective decoding to decode signals DS1 and prediction decoding signal DS2 output signal of the state latch circuit 62.

FIG. 6 is a flowchart for explaining the operation of the PWM pulse demodulation sequencer 60 of FIG.
FIG. 7 is a time chart for explaining the operation of the PWM pulse sampling circuit in FIG. 1, in which time is plotted on the horizontal axis and voltage is plotted on the vertical axis. 6 and 7
The operation of the PWM pulse sampling circuit of FIG. 1 will be described with reference to FIG. PWM pulse IN is detected by the edge detection circuit 4
When it is entered into 0, D-FF 41 and the AND gate 42
When the PWM pulse IN rises, that is, when the pulse changes from passive to dominant, the ring counter 50
The PWM pulse detection signal S42 is applied to the reset input terminal RA of
Is input, and the ring counter 50 is reset. This operation is performed every time the rising edge of the PWM pulse IN is detected, thereby synchronizing with the PWM pulse IN.

[0022] In step 71 of FIG. 6, PWM pulses IN, if RS-FF 73 is reset, the scan <br/> step 72, is sampled by the timing <br/> signal S50b of the ring counter 50. Then, step 7
In 3, when the sample result of the PWM pulse IN is dominant level (hereinafter, referred to as "H"), step 74
, The output terminal Q of the D- FF 62-1 (that is, q
1) becomes "H", and the input terminal q1 of the state control circuit 61 also becomes "H". In addition, in step 73,
When the sampling result of the PWM pulse IN is a passive level (hereinafter, referred to as “L”), the process returns to the reset state of step 71.

In step 75 of FIG. 6, the PWM pulse IN is output from the timing signal S50 of the ring counter 50.
sampled by b. Next, in step 76, when the sample result of the PWM pulse IN is "H", the in scan <br/> step 77, D- FF62-1,62-2 output terminal Q (i.e., q1, q2) Become "H", and the input terminals q1 and q2 of the state control circuit 61 also become "H". In addition, in step 76, P
When the sampling result of the WM pulse IN is "L", in step 78 , the output terminals Q (i.e., q7 to q11 ) of the D- FFs 62-7 to 62-11 are each set to the "H" state. Hereinafter, sampling of the PWM pulse IN is performed in a fixed time unit in a similar manner, and the PWM pulse demodulation is performed.
The decode signal DS1 is output from the sequencer 60 . Here, the timing signal S50b of the ring counter 50
Since the sample point of (that is, the sample clock signal S71) is set on the trailing edge side of the transmission bit unit time of the PWM pulse IN, the processing timing of the decode signal DS1 is delayed.

Next, for example, when the sampling result of the PWM pulse IN is "L", "L" and "L" twice,
Predicted decoded signal DS of WM pulse demodulation sequencer 60
2 is output, the RS-FF 73 is set, and the selector 7
1, the sample clock signal S of the PWM pulse IN
71 is a timing signal S50b of the ring counter 50.
To the timing signal S50a. Here, the timing signal S50a of the ring counter 50, Timing
To be outputted earlier than the ring signal S50b, the sample points of the PWM pulses IN received by the faster, and also earlier timing decode signal DS1 is Ru is output. When the output of the decode signal DS1 is completed, the timing signal S50c of the ring counter 50, RS
The FF 73 is reset, and the selector 71 sets the timing signal S50b of the ring counter 50 to the PWM pulse I
As the sample clock signal S71 of N, is input to the clock input terminal CK of the PWM pulse demodulation sequencer 60.

As described above, the timing of processing the decode signal DS1 must be delayed.
, For example, during data reception after the start of message reception, the sampling point of the PWM pulse IN is made to approach the falling of the PWM pulse IN. In addition, while receiving the PWM pulse IN, the timing of processing the decode signal DS1 must be earlier, for example,
Message reception before the start, or during the like before the start of the response to receiving the message, the sample points of the PWM pulse IN, by changing the position in time for the timing of processing of the decode signals DS1, PWM pulses IN
Can be decoded normally even if the dulling of the image occurs to some extent. Here, PWM pulse IN is a timing of processing of the decode signal DS1 must be fast, for example, message reception start command, or the response request command or the like for receiving messages, that there is no pulse width (e.g., "L" is Is used in general)
It is not affected by the dullness of the PWM pulse IN.

As described above, this embodiment has the following advantages. In this embodiment, the sample points of the PWM pulses IN received so as to vary in accordance with the timing for processing the decode signal DS1. Therefore, even when blunting the PWM pulse IN, makes it possible to decode a properly placing the sample points behind the half of the transmission bit unit time, allowable capacity such as associated with the signal transmission line or the like Value can be improved. Therefore,
The wiring length of the multiplex communication line can be increased, the connection range of the multiplex communication line can be widened, and control over a wide range can be performed.
In addition, the number of nodes to be connected can be increased, and various kinds of control can be performed. Although this embodiment can be used for various purposes, if it is applied to a vehicle navigation system, an audio system, a security monitoring system network, a vending machine centralized management system, etc., which are rapidly spreading in recent years, It is very effective.

The present invention is not limited to the above embodiment,
Various modifications are possible. As the modified example, For example <br/>, it is as follows. (A) The edge detection circuit 40 in FIG. 1 may have another configuration as long as it detects a pulse edge. (B) ring counter 5 0 a timing signal generating means, if a circuit for generating a plurality of timing signals having mutually time difference based on the reset signal and the clock signal, or in other configurations. (C) The selector 71 may be composed of another gate circuit or the like. (D) The RS-FF 73 may be replaced with another flip-flop such as a JK flip-flop. Method of predicting the timing of processing (e) decode signal DS1 may be in other ways. For example, PWM pulse <br/> scan IN sample results of "L", "L", "L", ··
- a prediction when the "L" was followed by more than three times decode signal D
S2 may be set to be output. (F) The present invention is not limited to multiplex communication.

[0028]

As described [Effect Invention above in detail, according to the first and second aspects of the present invention, the sample points of pulses received. Thus is changed according to the timing of processing of the decoding result, the pulse Can be normally decoded even if the dulling occurs, and the allowable value of the capacitance and the like attached to the signal line and the like can be improved. Therefore, for example, since the wiring length of the multiplex communication line can be increased , the connection range of the multiplex communication is widened, and control over a wide range is possible. In addition, the number of nodes can be increased, and various types of control can be performed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a PWM pulse sampling circuit showing an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional multiplex communication line system.

FIG. 3 is a schematic configuration diagram of a PWM pulse demodulation circuit in FIG. 2;

FIG. 4 is a configuration diagram of a ring counter in FIG. 1;

5 is a configuration diagram of a PWM pulse demodulation sequencer in Fig.

FIG. 6 is a flowchart for explaining the operation of FIG. 5;

FIG. 7 is a time chart for explaining the operation of FIG. 1;

8 is a view to view a multiplex communication bus line circuit and a signal waveform.

FIG. 9 shows a sample clock in a general start-stop synchronization signal.
It is a time chart of a signal .

[Explanation of symbols]

40 edge detection circuit 50 ring counter 60 PWM pulse demodulation sequencer 71 selector 73 RS-FF

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-216778 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 25/08 H04L 25/49

Claims (2)

(57) [Claims] In a multiplex communication bus system coupled by wired and logic, transmitting a first sample point of a passive signal at a transition from a dominant signal output state to a passive signal output state indicating an active signal logic. The second sample point of the passive signal at a location where the passive signal is continuously sampled at a predetermined location in the communication frame is located on the trailing edge side of a half of the bit unit time, and is transmitted from the first sample point in transmission bit units. Pal characterized by being arranged at the leading edge of time
It is sampled circuit. 2. The method according to claim 1, further comprising the steps of:
A ring counter for outputting a timing signal, and a pulse and a sample clock signal,
The pulse is sampled according to the clock signal and the pulse is sampled.
Output the sample result,
A pulse demodulation circuit for outputting the first, second and third timing signals and the prediction data.
Code signal, and the first timing signal is input.
The third timing signal timing
The second timing signal that is later than
Output as a lock signal, and the predictive decode signal is input
The timing is higher than the second timing signal.
The third timing signal, which has the fastest
And a selector that outputs a
Loose sampling circuit.