JP5617795B2 - Communication system and master node and slave node used in the communication system - Google Patents

Description

  The present invention operates in synchronization with the master node by receiving a master node that outputs a synchronization signal including a clock component (hereinafter referred to as a “clock pulse”) to the bus communication path and the clock pulse via the bus communication path. And a slave node.

2. Description of the Related Art Conventionally, communication systems that use bus communication paths such as CAN and LIN are known as communication systems mounted on vehicles.
In order to perform efficient communication in this type of communication system, it is necessary to synchronize the operations of transceivers provided in each communication device (hereinafter referred to as “node”) for transmitting and receiving signals via a bus communication path. desirable.

  As one of methods for realizing such synchronization, a method in which any one node (master node) transmits a clock pulse to a bus communication path is known. At this time, the other node (slave node) extracts the clock component from the clock pulse on the bus communication path and processes (divides, etc.) the free-running clock generated by the own transceiver, thereby extracting the extracted clock. A bus clock synchronized with the component is generated, and the transceiver is operated according to the bus clock.

  In such a communication system, each node has a wake-up mode that is an operation mode that can execute all functions assigned in advance, and a sleep that is an operation mode in which some functions are stopped to reduce power consumption. Some work with modes. When each node is in the sleep mode, for example, when a wake-up factor such as a predetermined switch being pressed occurs, the mode shifts to the wake-up mode based on a signal on the bus communication path.

  Thus, when shifting to the wake-up mode based on the signal on the bus communication path, erroneous wake-up that causes wake-up due to noise superimposed on the bus communication path becomes a problem.

  As a technique for solving such a problem, a technique has been proposed in which sampling of a signal corresponding to a wake-up instruction is performed a plurality of times (see, for example, Patent Document 1). That is, if wakeup is performed only with an instantaneous signal level, noise superimposition cannot be recognized, so that the continuation of the signal level is determined. That is, if the signal level based on the time-series sampling result is on the wake-up side, it is recognized as a wake-up signal.

JP 2007-22355 A

  However, in the invention described in Patent Document 1, it is not possible to determine when the signal on the bus communication path is fixed to the wake-up side (for example, low level) due to a short circuit or the like. Therefore, the problem of false wakeup still remains.

  The present invention has been made to solve the above-described problem, and its purpose is to wake up in a communication system that performs communication based on clock pulses transmitted from a master node, regardless of the influence of noise or the like. It is to appropriately switch the operation mode to the mode.

The communication system of the present invention made to achieve the above-mentioned object receives a master node that outputs a clock pulse including a clock component to a bus communication path, and receives the clock pulse from the master node via the bus communication path. Thus, a slave node that operates in synchronization with the master node is provided.

  At this time, each node is configured to operate in a wake-up mode that is an operation mode capable of executing a pre-assigned function and a sleep mode that is an operation mode in which some functions are stopped.

  Here, in particular, in the master node, the factor presence / absence determining means determines the presence / absence of a wakeup factor that causes the transition to the wakeup mode. When the factor presence / absence determining means determines that there is a wake-up factor, the master control means starts outputting clock pulses to the bus communication path.

  On the other hand, in the slave node, the clock pulse output determination means determines whether or not the clock pulse from the master node is output to the bus communication path. When the clock pulse output determining means determines that the clock pulse is being output, the slave control means switches the operation mode to the wake-up mode and performs communication processing.

  Conventionally, since continuation of the signal level on the wakeup side is determined, it is impossible to determine the case where the signal on the bus communication path is fixed on the wakeup side. On the other hand, in the present invention, the slave node is woken up by a clock pulse from the master node. In this case, it is possible to appropriately switch the operation mode to the wake-up mode regardless of noise or the like because the clock pulse that periodically falls or rises is determined instead of the continuation of the signal level.

  By the way, it is conceivable that the master node determines a wake-up request generated in its own node. However, the wake-up request may be generated at another node (slave node).

Therefore, slave nodes, when the wakeup factor occurs in the own node, has a wake-up signal transmission means for transmitting a wake-up signal, causes presence determination means, the wake-up signal at the wake-up signal transmission unit When transmitted, it may be determined that there is a wake-up factor. In this case, the master node starts outputting the clock pulse due to the wake-up signal from the slave node, and thereby the other slave node is activated. Even in this case, the operation mode can be appropriately switched to the wake-up mode regardless of the influence of noise or the like.

In the case of determining the output of the clock pulses from the master node, the clock pulse output determining means, based on the sampling information in the large count clock frequency to the clock pulse, the high and low levels in the period count value It is conceivable to determine that a clock pulse is being output when the ratio of is within a predetermined range. In this way, for example, instantaneous rise and fall of an edge due to noise or the like is not determined as a clock pulse, and it is possible to appropriately determine whether or not a clock pulse is being output.

Further, the clock pulse output determining unit, an edge detecting circuit for detecting an edge of a clock pulse, a clock detection signal which inverts depending on whether the clock pulse based on the output from the edge detection circuit is outputted Output And an edge interval determination circuit. Even in this case, for example, it is not determined that the edge rises or falls due to noise or the like as the clock pulse, and it is possible to appropriately determine whether or not the clock pulse is output. In this case, since the configuration is based on hardware, it is possible to instantaneously perform from the determination of the clock pulse to the switching of the operation mode.

  By the way, the time required for wake-up may differ between the slave nodes, and in this case, there is a possibility of so-called reception leakage, in which data transmitted by the slave node that has been woken up first is not received by another slave node.

Accordingly, after switching the operation mode to the U E cum-up mode, further configured to start receiving and first communication processing predetermined information from the master node is preferred. Here, the predetermined information may be a header including an identifier (ID) for regular communication. In this case, if predetermined information is transmitted from the master node in consideration of the time difference required for wakeup between the slave nodes, reception omission at the slave node can be prevented.

Up to this point, the switching of the operation mode to the wake-up mode has been described. A configuration for switching the operation mode to the sleep mode will be described next.
That is, switches the operation mode to the sleep mode the master control means stops the output of the clock pulse, the slave control means, when the clock pulses in the clock pulse output determining means is determined not to be output, the sleep mode Switch the operation mode to. As described above, when the transition to the sleep mode is made by the interruption of the clock pulse from the master node, the transition to the sleep mode can be realized relatively easily.

At this time, the master control unit may after transmitting the sleep signal, after waiting for the predetermined time, when to stop the output of the clock pulse. At this time, when receiving the sleep signal, the slave control means executes a pre-sleep saving process prior to switching the operation mode to the sleep mode within a predetermined time. In this way, for example, a parameter saving process can be performed, and the operation of the slave node at the next wakeup can be stabilized.

On the other hand, when the operation mode is switched to the sleep mode, a wakeup factor may occur in the slave node. Therefore, the master control unit receives a pulse from the slave node as defined in until a predetermined time elapses, transmits the predetermined information to continue the output of the clock pulse, the slave control means, after receiving the sleep signal When a wake-up factor occurs in the own node, a predetermined pulse is output, and when predetermined information is received from the master node, communication processing is started and data indicating sleep inhibition is output. In this way, communication can be quickly restored without sleeping even after receiving a sleep signal.

  Although the above has been described as the invention of the communication system, it can also be realized as the invention of the master node used in the communication system and the invention of the slave node used in the communication system.

It is a block diagram which shows schematic structure of a communication system. (A) is explanatory drawing which shows the structure of the transmission-line code | cord | chord used on a bus channel, (b) is explanatory drawing which shows the structure of the flame | frame transmitted / received via a bus channel, (c) is UART. It is explanatory drawing which shows the structure of the block data which transmits / receives. It is a block diagram which shows the structure of a master node and a slave node. It is explanatory drawing which shows the various signals which a timing generation part produces | generates. It is a flowchart which shows a master wake-up process. It is a flowchart which shows the first half part of a slave wakeup process. It is a flowchart which shows the second half part of a slave wakeup process. It is explanatory drawing which shows the specific example of wakeup. It is explanatory drawing which shows the specific example of wakeup. It is explanatory drawing which shows the specific example of wakeup. It is a flowchart which shows a master sleep process. It is a flowchart which shows a slave sleep process. It is explanatory drawing which shows the specific example of a sleep. It is explanatory drawing which shows the specific example of a sleep. It is a block diagram which shows the structure of a clock detection circuit. (A) is a circuit diagram which shows the structure of an edge detection circuit, (b) is a timing chart which shows the signal of each part of an edge detection circuit. It is a circuit diagram which shows the structure of an edge space | interval determination circuit. It is a timing chart which shows the signal of each part of an edge space | interval determination circuit.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a communication system 1 mounted on a vehicle. Here, nodes 3 as communication devices are connected to each other via a bus communication path 5. The node 3 is an electronic control device (body system ECU) that realizes a body system application or related equipment (switches, sensors, etc.) that is provided to detect the state of the vehicle or control the state of the vehicle. is there.

  As shown in FIG. 1, among the nodes 3 constituting the communication system 1, the body system ECU includes a body wiper ECU, a seat ECU, a slide door ECU, a mirror ECU, a back door ECU, a light ECU, a tilt tele (electric steering) Position adjusting device (ECU) and the like, while related devices include a light SW, a wiper SW, a light sensor, a rain sensor and the like.

  The bus communication path 5 is configured such that when a high level signal and a low level signal are simultaneously output from different nodes 3, the signal level on the bus communication path 5 becomes a low level. To achieve bus arbitration.

Here, FIG. 2A is an explanatory diagram showing transmission path codes used in the bus communication path 5.
As shown in FIG. 2A, in the bus communication path 5, a PWM code in which the signal level changes from a low level to a high level in the middle of a bit is used as a transmission path code, and a dominant (corresponding to 0 in this embodiment) is used. ) And recessive (corresponding to 1 in the present embodiment) are expressed by two types of duty ratios.

  Specifically, the dominant is set so that the ratio of the low level is longer than the recessive (in this embodiment, the dominant is a 2/3 period of 1 bit and the recessive is a 1/3 period of 1 bit) When a dominant and recessive collide with each other on the bus communication path 5, the dominant wins arbitration.

  In the communication system 1, a so-called CSMA / CA access control method is used in which the node 3 that has lost the arbitration immediately stops transmission, and only the node 3 that has won the arbitration continues transmission.

FIG. 2B is an explanatory diagram showing a configuration of a frame used for communication between the nodes 3.
As shown in FIG. 2B, the frame includes a header for designating data permitted to be transmitted and a variable length response for transmitting the data designated by the header.

  Among these, the header is made up of an identifier (ID) of data that is permitted to be transmitted, and is set so that the smaller the ID value, the longer the bus arbitration is won. On the other hand, in addition to the data, the response includes at least a size information indicating the size of the data (response) and a CRC code for checking whether there is an error.

  Here, returning to the description of FIG. 1, each node 3 is a wake-up mode that is an operation mode capable of executing all the functions assigned in advance, and an operation mode in which some functions are stopped in order to reduce power consumption. Operates in sleep mode.

  One of the nodes 3 (here, the body wiper ECU) is a master node (hereinafter simply referred to as “master”) 3a, and the other node is a slave node (hereinafter simply referred to as “slave”) 3b. At this time, when the master 3a transmits the header, data to be permitted to be transmitted (and thus the slave 3b serving as the data transmission source) is sequentially specified, and the slave 3b serving as the data transmission source specified by the header responds ( Data) and event communication in which the slave 3b autonomously controls communication regardless of an instruction from the master 3a.

Hereinafter, the configurations of the master 3a and the slave 3b will be described with reference to FIG.
The master 3 a is supplied from the signal processing unit 10 that executes various processes assigned to the node 3 based on information obtained by communication with the other nodes 3 via the bus communication path 5, and the signal processing unit 10. The NRZ code transmission data TXD is encoded into PWM code transmission data TX and output to the bus communication path 5. The PWM code reception data RX received from the bus communication path 5 is decoded into the NRZ code reception data RXD. And a transceiver 20 that supplies the signal processing unit 10.

  The signal processing unit 10 is configured around a known microcomputer including a CPU, ROM, RAM, IO port, and the like, and further, a UART (universal asynchronous transmission / reception circuit: Universal Asynchronous) that realizes asynchronous communication. Receiver Transmitter) 11, an oscillation circuit for generating an operation clock for operating the signal processing unit 10 and an internal clock CK that is set to the same speed (20 Kbps in this embodiment) as the communication speed of the UART 11 and is supplied to the transceiver 20 12 is provided.

  However, the oscillation circuit 12 is configured using a crystal oscillator, and a highly accurate circuit that oscillates at a stable frequency is used. The signal processing unit 10 is configured to supply the transceiver 20 with a mode signal MD representing the operation mode of the own node.

  Here, FIG. 2C is an explanatory diagram showing a configuration of data TXD and RXD transmitted and received by the UART 11. As shown in the figure, the UART 11 has a 1-bit length start bit (low level) indicating the start of data, a stop bit (high level) indicating the end of data, and 8 bits sandwiched between the start bit and stop bit. A total of 10-bit block data composed of bit data is transmitted and received as a unit. However, the 8-bit data as the main part is set so that the LSB (least significant bit) is the head and the MSB (most significant bit) is the end.

  The header constituting the above-mentioned frame (see FIG. 2B) is composed of a single block data, and 7 bits are used as an ID among 8 bits data excluding the start bit and stop bit. One bit is used as a parity bit. The response is composed of one or a plurality of block data, and size information is set in the first block.

  Returning to FIG. 3, the transceiver 20 includes a simple oscillation circuit such as a ring oscillator configured by connecting a plurality of inverters in a ring shape, and divides the count clock CCK generated by the oscillation circuit. Accordingly, the timing generation unit 21 that generates various timing signals synchronized with the internal clock CK supplied from the signal processing unit 10, and the encoding and reception of the transmission data TXD according to the timing signal generated by the timing generation unit 21 An encoding / decoding unit 22 that decodes the data RX, a transmission buffer 23 that outputs the transmission data TX encoded by the encoding / decoding unit 22 to the bus communication path 5, and data on the bus communication path 5 In accordance with the reception buffer 24 that captures and the mode signal MD supplied from the signal processing unit 10, the timing generation unit 21 and And a mode management unit 25 for controlling the operation of the No. decoding unit 22.

  The transmission buffer 23 is configured using, for example, a known open collector circuit so that bus arbitration on the bus communication path 5 described above is possible. The reception buffer 24 is configured by a known comparator that outputs a high level if the signal level of the bus communication path 5 is greater than a preset threshold value, and outputs a low level if the signal level is less than the threshold value.

  When the mode signal MD indicates the wake-up mode (“1” in the present embodiment), the mode management unit 25 operates the timing generation unit 21 and the encoding / decoding unit 22 effectively, When the signal MD indicates the sleep mode (“0” in the present embodiment), the timing generator 21 is controlled so that the generation of the timing signal is stopped.

  Here, FIG. 4 is an explanatory diagram showing various timing signals generated by the timing generator 21. Note that the count clock CCK is set to have a sufficiently high frequency (several tens to several hundred times) with respect to the internal clock CK.

  The timing generation unit 21 includes a counter that counts the interval of the falling edges of the internal clock CK, that is, the length of one cycle, using the counting clock CCK, and the cycle count value Ci (i = 1, 2, ..)), And a frequency dividing circuit for generating various timing signals synchronized with the internal clock CK by dividing the count clock CCK.

Specifically, the following clock is generated as the timing signal.
As shown in FIG. 4, the timing generator 21 has a period corresponding to the period count value Ci, and the interval from the falling edge to the rising edge is set to a length corresponding to ½ of the period count value Ci. The bus clock BCK having a duty of 50% and a cycle corresponding to the cycle count value Ci, and the timing of the falling edge of the bus clock BCK and 1/4, 2/4, 3 of the cycle count value from the edge The sampling clock SCK whose rising edge (sampling edge) is the timing when the period corresponding to / 4 has elapsed, and the timing when the period corresponding to 1/3 of the cycle count value has elapsed from the falling edge of the bus clock BCK The edge of recessive generation clock RCK and bus clock BCK Generating a clock DCK for dominant generation timing has elapsed by a time period corresponding to 2/3 of the period count value from the gully edge becomes a rising edge.

  The timing generation unit 21 generates a timing signal by operating the oscillation circuit in accordance with an instruction from the mode management unit 25 when the operation mode is the wake-up mode, that is, when the mode signal MD is “1”. . In this case, a clock pulse serving as a synchronization signal is output to the bus communication path 5. On the other hand, when the operation mode is the sleep mode, that is, when the mode signal MD is “0”, generation of the timing signal is stopped by stopping the oscillation circuit. In this case, the output of the clock pulse is stopped and the bus communication path 5 is fixed at the high level.

Returning to FIG. 3, the configuration of the slave 3b will be described.
Similarly to the master 3a, the slave 3b has a signal processing unit 30 that executes various processes assigned to the own node 3 based on information obtained by communication with other nodes 3 via the bus communication path 5, and the like. Transmission data TX obtained by encoding transmission data TXD supplied from the signal processing unit 30 with a PWM code is output to the bus communication path 5 and received data (reception data) RX on the bus communication path 5 is received and decoded. And a transceiver 40 for supplying the RXD to the signal processing unit 30.

The signal processing unit 30 is configured in the same manner as the signal processing unit 10 except that the function of supplying the internal clock CK to the transceiver 40 is omitted.
However, the signal processing unit 30 of the slave 3b is not necessarily configured by a microcomputer, and may be configured by a sequencer having at least a function corresponding to the UART 11 and an oscillation circuit that generates an operation clock for operating the sequencer. Good.

  Similar to the transceiver 20, the transceiver 40 includes a timing generation unit 41, an encoding / decoding unit 42, a transmission buffer 23, a reception buffer 24, and a mode management unit 25, and the timing generation unit 41 and the encoding / decoding unit 42. A part of the configuration differs from the timing generation unit 21 and the encoding / decoding unit 22.

  Specifically, when the timing generation unit 41 generates various timing signals, the signal to be synchronized is not the internal clock CK but the reception data RX acquired from the bus communication path 5 via the reception buffer 24. Is different.

  In the present embodiment, when the slave 3b detects a clock pulse output from the master 3a to the bus communication path 5 while in the sleep mode, the slave 3b shifts to the wake-up mode. The clock pulse is detected by sampling the reception data RX received from the bus communication path 5 at the timing of the count clock CCK, and the high level in the cycle count value Ci (i = 1, 2,...) This is performed depending on whether the low level ratio is within a predetermined range. For example, as shown in FIG. 4, it is determined whether or not the ratio between the count value of the period A at the low level and the count value of the period B at the high level is within a predetermined range.

Note that the timing generation unit 41 may omit the generation of the recessive generation clock RCK, which is one of the timing signals.
The encoding / decoding unit 42 is configured in the same manner as the encoding / decoding unit 22 except that the operation of the internal circuit is partially different.

  As described above, when the operation mode is the wake-up mode, that is, when the mode signal MD is “1”, the transceiver 40 of the slave 3b becomes a bit boundary of the reception data RX of the PWM code fetched from the bus communication path 5. A falling edge is extracted as a clock component, a bus clock BCK synchronized with the clock component is generated, transmission data TXD is encoded and reception data RX is decoded according to the bus clock BCK, and the bus communication path 5 is used. Realize communication.

  Next, a master wake-up process executed by the signal processing unit 10 of the master 3a will be described. FIG. 5 is a flowchart showing the master wake-up process. This process is executed when the master 3a is in the sleep mode.

  In first S100, it is determined whether or not there is a wake-up factor. The wake-up factor is generated by a request from a host application based on, for example, pressing a power switch or the like. At this time, the wake-up factor may be detected by another node when detected by the own node. When detected by the other node 3b, a wake-up signal is received via the bus communication path 5. If it is determined that there is a wake-up factor (S100: YES), the process proceeds to S110. On the other hand, when it is determined that there is no wake-up factor (S100: NO), the determination process of S100 is repeated.

  In S110, it is determined whether or not the wake-up factor has occurred in the own node. Here, when it is determined that the wake-up factor has occurred in the own node (S110: YES), the wake-up factor flag is set in S120, and then the process proceeds to S130. On the other hand, if it is determined that the cause is not a wakeup factor generated in the own node (S110: NO), that is, if a wakeup signal is received from another node, the process proceeds to S130 without executing the process of S120. .

  In S130, the mode signal MD is set to “1” and a clock pulse is output. In this process, the timing generation unit 21 generates a timing signal and outputs a clock pulse to the bus communication path 5. At this time, if the wake-up factor flag is set, that is, if it is a wake-up factor generated in the own node, a timing pulse is output immediately after activation. On the other hand, if the wake-up factor flag is not set, that is, if it is a wake-up factor that has occurred in another node, a predetermined time shorter than that after the activation, assuming that the slave 3b is activated within the predetermined time T2. A timing pulse is output within T3 (<T2).

  In subsequent S140, it is determined whether or not a predetermined time T1 has elapsed. This process is based on the assumption that the slave 3b is activated within the predetermined time T2, and determines the elapse of the predetermined time T1 (> T2) longer than that. If it is determined that the predetermined time T1 has elapsed (S140: YES), transmission of an arbitrary ID is started in S150, and then the master wake-up process is terminated. On the other hand, while the predetermined time T1 has not elapsed (S140: NO), the determination process of S140 is repeated.

Note that the wake-up factor flag is cleared when data transmission after activation is completed. The same applies to the following.
Next, the slave wake-up process executed by the signal processing unit 30 of the slave 3b will be described. 6 and 7 are flowcharts showing the slave wake-up process. This process is executed when the slave 3b is in the sleep mode.

  In the first S200, it is determined whether there is a wake-up factor. As described above, the wake-up factor may be detected by the own node or may be detected by another node. When detected by another node (slave 3b), a wake-up signal is received via the bus communication path 5. If it is determined that there is a wake-up factor (S200: YES), the process proceeds to S210. On the other hand, when it is determined that there is no wake-up factor (S200: NO), the determination process of S200 is repeated.

  In S210, it is determined whether or not the wake-up factor has occurred in the own node. Here, when it is determined that the wake-up factor has occurred in the own node (S210: YES), the wake-up factor flag is set in S220, and then the process proceeds to S230. On the other hand, when it is determined that it is not a wake-up factor generated in the own node (S210: NO), that is, when a wake-up signal is received from another node, the process of S220 is not executed and the process proceeds to S230. .

  In S230, it is determined whether or not the wake-up factor flag is set. If it is determined that the flag is set (S230: YES), the process proceeds to S240. On the other hand, when it is determined that the flag is not set (S230: NO), the processing of S240 and S250 is not executed, and the process proceeds to S260.

  In S240, it is determined whether there is a dominant pulse. If it is determined that there is no dominant pulse (S240: NO), a wakeup signal is transmitted in S250, and then the process proceeds to S260. The wake-up signal is a one-block command that can be transmitted / received by the UART 11. On the other hand, when it is determined that there is a dominant pulse (S240: YES), the process proceeds to S260 without executing the process of S250.

  As a result of the processing of S230 to S250, the wakeup factor flag is set (S230: YES), and if there is no other node 3 that is transmitting data (S240: NO), a wakeup signal is transmitted. (S250).

  When the determination is negative in S230, the process proceeds to S260, or the process proceeds from S250 to determine whether there is a clock pulse. In this process, it is determined whether or not a clock pulse from the master 3 a is output on the bus communication path 5. As described above, in this embodiment, this clock pulse is detected by sampling the reception data RX received from the bus communication path 5 at the timing of the count clock CCK, and the cycle count value Ci (i = 1, 2,... The ratio between the high level and the low level in () is within a predetermined range. If it is determined that there is a clock pulse (S260: YES), the mode signal MD is set to “1” in S270, and then the process proceeds to S300 in FIG. On the other hand, when it is determined that there is no clock pulse (S260: NO), the process proceeds to S280.

  In S280, it is determined whether or not a predetermined time T4 has elapsed since the first reception of the wakeup signal. If it is determined that the predetermined time T4 has elapsed (S280: YES), the mode signal MD is set to “0” in S290, and then the slave wake-up process is terminated. In this case, a physical bus error is detected in which the clock pulse from the master 3a is not detected, and the sleep mode is continued. On the other hand, as long as the predetermined time T4 has not elapsed (S280: NO), the processing from S230 is repeated. In this embodiment, the wake-up signal is repeatedly transmitted until the predetermined time T4 has elapsed (S280: NO, S250). For example, the wake-up signal is a predetermined number of times (for example, twice) after a predetermined time. An up signal may be transmitted.

  In S300 in FIG. 7 that moves from S270, it is determined whether or not an arbitrary ID has been received. As described above, when the predetermined time T1 has elapsed after activation (S140: YES in FIG. 5), the master 3a starts transmitting an arbitrary ID (S150). If it is determined that an arbitrary ID has been received (S300: YES), the processes of S310 and S320 are not executed, and the slave wake-up process is terminated. At this time, the slave 3b operates in the wake-up mode. That is, data transmission / reception is possible only after receiving an arbitrary ID. On the other hand, when it is determined that the arbitrary ID has not been received (S300: NO), the process proceeds to S310.

  In S310, it is determined whether or not a predetermined time has elapsed. If it is determined that the predetermined time has elapsed (S310: YES), the mode signal MD is set to “0”, and then the slave wake-up process is terminated. At this time, the slave 3b enters the sleep mode. On the other hand, while the predetermined time has not elapsed (S310: NO), the processing from S300 is repeated.

  The master wakeup process and the slave wakeup process have been described above. Further, in order to facilitate understanding of these processes, a specific description will be added based on FIGS. In order to distinguish the slave 3b, symbols A to C in the figure are used and are appropriately described as A slave 3b, B slave 3b, and C slave 3b.

  In FIG. 8, since the wake-up factor is generated in the master 3a (S100: YES, S110: YES in FIG. 5), the wake-up factor flag is set (S120). At this time, a clock pulse is output immediately after startup (S130). On the other hand, the slaves 3b of A to C detect the clock pulse from the master 3a (S260: YES in FIG. 6), start within the predetermined time T2 from the start of the master 3a, and set the mode signal MD to “1”. (S270) Waiting for reception of an arbitrary ID (S300, S310 in FIG. 7).

  When the predetermined time T1 elapses (S140: YES in FIG. 5), the master 3a starts transmitting an arbitrary ID (S150). On the other hand, when the slave 3b of A to C receives the arbitrary ID transmitted by the master 3a (S300 in FIG. 7: YES), the slave wake-up process is terminated and regular communication or event communication is performed.

  In FIG. 9, since a wake-up factor is generated in the A slave 3b (S200: YES, S210: YES in FIG. 6), a wake-up factor flag is set in the A slave 3b (S220). . Therefore, the A slave 3b transmits a wakeup signal (S250).

  When the master 3a receives the wake-up signal from the A slave 3b (S100 in FIG. 5: YES), it is assumed that the slaves A to C start within a predetermined time T2 from the reception of the wake-up signal. A clock pulse is output within a predetermined time T3 (<T2) (S130).

  As a result, as in FIG. 8, the slave 3b of A to C detects the clock pulse from the master 3a (S260 in FIG. 6: YES), and receives the arbitrary ID transmitted by the master 3a (in FIG. 7). S300: YES), the slave wake-up process is terminated, and regular communication or event communication is performed.

  Furthermore, in FIG. 10, the wake-up factor is generated in the A slave 3b as in FIG. 9 (S200: YES, S210: YES in FIG. 6), so the wake-up factor flag is set in the A slave 3b. It is set (S220). Therefore, the A slave 3b transmits a wakeup signal (S250).

  However, here, the master 3a does not output a clock pulse, and no response is obtained. Therefore, the A slave 3b repeats the transmission of the wakeup signal (S250) until the predetermined time T4 has not elapsed (S280: NO).

  The slaves 3b of A to C set the mode signal MD to “0” (S290) when the elapse of the predetermined time T4 is determined without detecting the clock pulse (S260: NO) (S290: YES), and continue the sleep mode. To do.

  Next, a master sleep process executed by the signal processing unit 10 of the master 3a will be described. FIG. 11 is a flowchart showing the master sleep process. This process is executed when the master 3a is in the wake-up mode.

  In the first S400, it is determined whether or not there is a sleep prohibition factor. When there is a sleep prohibition factor, data indicating sleep prohibition is transmitted from the slave 3b. If it is determined that there is no sleep prohibition factor (S400: YES), the process proceeds to S410. On the other hand, when it is determined that there is a sleep prohibition factor (S400: NO), the determination process of S400 is repeated.

In S410, the transmission of the arbitrary ID is stopped. This process stops the above-described regular communication.
In subsequent S420, a sleep signal is transmitted. This signal is a one-block command that can be transmitted and received by the UART 11.

  In the next S430, a timer is set. In subsequent S440, it is determined whether or not a predetermined time T5 has elapsed. If it is determined that the predetermined time T5 has elapsed (S440: YES), the mode signal MD is set to “0” in S450 to stop the output of the clock pulse, and then the master sleep process is terminated. That is, here, the output of the clock pulse is stopped after waiting for a predetermined time T5. This is to cause the slave 3b to execute a save process prior to sleep. On the other hand, when it is determined that the predetermined time T5 has not elapsed (S440: NO), the process proceeds to S460.

  In S460, it is determined whether there is a dominant pulse. If it is determined that there is a dominant pulse (S460: YES), transmission of an arbitrary ID is started in S470, and then the master sleep process is terminated. In this case, the wake-up mode is continued. On the other hand, when it is determined that there is no dominant pulse (S460: NO), the processing from S440 is repeated.

  Next, a slave sleep process executed by the signal processing unit 30 of the slave 3b will be described. FIG. 12 is a flowchart showing slave sleep processing. This process is repeatedly executed when the slave 3b is in the wake-up mode.

  In first S500, it is determined whether or not a sleep signal is received. This process corresponds to S420 in FIG. If it is determined that a sleep signal has been received (S500: YES), a timer is set in S510, and the process proceeds to S520. On the other hand, when it is determined that the sleep signal has not been received (S500: NO), the slave sleep process is terminated without executing the subsequent processes.

  In S520, it is determined whether there is a wake-up factor. If it is determined that there is a wake-up factor (S520: YES), a dominant pulse is output in S530, and then the process proceeds to S560. On the other hand, if it is determined that there is no wake-up factor (S520: NO), the pre-sleep saving process is performed in S540, and the process proceeds to S550.

  In S550, it is determined whether or not a predetermined time T6 has elapsed. If it is determined that the predetermined time T6 has elapsed (S550: YES), the process proceeds to S560. On the other hand, as long as the predetermined time T6 has not elapsed (S550: NO), the process proceeds to S580.

  In S560, which shifts from S530 or shifts to affirmative determination in S550, it is determined whether or not the clock pulse is stopped. This process corresponds to S450 in FIG. If it is determined that the clock pulse is stopped (S560: YES), the mode signal MD is set to “0” in S570, and then the slave sleep process is terminated. At this time, the slave 3b shifts to the sleep mode. On the other hand, if it is determined that the clock pulse is not stopped (S560: NO), the process proceeds to S580.

  In S580 to which the process proceeds when a negative determination is made in S550 or S560, it is determined whether or not an arbitrary ID has been received. This process corresponds to S470 in FIG. If it is determined that an arbitrary ID has been received (S580: YES), the slave sleep process is terminated. At this time, the slave 3b continues the wakeup mode. On the other hand, when it is determined that the arbitrary ID has not been received (S580: NO), the processing from S550 is repeated.

  The master sleep process and the slave sleep process have been described above. In order to facilitate understanding of these processes, a description will be given here with specific examples based on FIGS. 13 and 14.

  In FIG. 13, the master 3a is performing regular communication, and if data indicating that sleep is prohibited is not transmitted from the slaves 3b of A to C (S400: YES), transmission of an arbitrary ID is stopped (S410), A sleep signal is output (S420). Thereafter, when the predetermined time T5 elapses without outputting the dominant pulse (S460: NO, S440: YES), the output of the clock pulse is stopped (S450). Thereby, the master 3a shifts to the sleep mode.

  As described above, the reason why the master 3a waits for the elapse of the predetermined time T5 is to cause the slaves 3b of A to C to execute the pre-sleep saving process. That is, when the slaves 3b of A to C receive the sleep signal (S500 in FIG. 12: YES), if there is no wake-up factor (S520: NO), the slave 3b executes the pre-sleep saving process (S540). Then, after the predetermined time T6 has elapsed (S550: YES), if the clock pulse is stopped (S560: YES), the mode signal MD is set to “0” (S570), and the mode is shifted to the sleep mode.

  In FIG. 14, a wake-up factor has occurred in the B slave 3b that has not responded to the regular communication of the master 3a. Therefore, after receiving the sleep signal from the master 3a (S500: YES in FIG. 12), the B slave 3b determines that there is a wake-up factor (S520: YES), and outputs a dominant pulse (S530).

  At this time, the master 3a determines that there is a dominant pulse before the predetermined time T5 has elapsed (S440: NO in FIG. 11) (S460: YES), and starts transmitting an arbitrary ID (S470).

  Thereby, the B slave 3b notifies the prohibition of sleep by, for example, event communication (see FIG. 14). Also, the slaves 3b of A and C also receive the sleep signal (S500: YES in FIG. 12), and the clock pulse from the master 3a is not stopped when the predetermined time T6 has passed (S550: YES). (S560: NO), an arbitrary ID is received (S580: YES), and the wake-up mode is continued.

  As described above in detail, in the present embodiment, when the master 3a determines whether or not there is a wake-up factor (S100 in FIG. 5) and determines that there is a wake-up factor (S100: YES), the mode signal MD is changed to “ 1 "and a clock pulse is output to the bus communication path 5 (S130). On the other hand, the slave 3b determines whether or not the clock pulse from the master 3a is output to the bus communication path 5 (S260 in FIG. 6), and determines that the clock pulse is output (S260: YES). ), The mode signal MD is set to “1” (S270), and the operation mode is shifted to the wake-up mode.

  As described above, in the present embodiment, the slave 3b is woken up by the clock pulse from the master 3a. In this case, since the presence or absence of a clock pulse that periodically falls or rises is determined, it is possible to appropriately switch the operation mode to the wake-up mode regardless of the influence of noise or the like.

  In this embodiment, when a wake-up factor occurs in the slave 3b (S200 in FIG. 6), if it occurs in the own node (S210: YES), a wake-up factor flag is set (S220), A wake-up signal is transmitted (S250). Even when this wake-up signal is received, the master 3a determines that there is a wake-up factor (S100: YES in FIG. 5), and outputs a clock pulse with the mode signal MD set to “1” (S130). Thereby, the slave 3b determines the output of the clock pulse (S260) and shifts the operation mode to the wake-up mode. Therefore, also in this case, it is possible to appropriately switch the operation mode to the wake-up mode regardless of the influence of noise or the like.

  Furthermore, in the present embodiment, the reception data RX received from the bus communication path 5 is sampled at the timing of the count clock CCK, and the high level and low level in the cycle count value Ci (i = 1, 2,...) Are sampled. The clock pulse is detected depending on whether the ratio is within a predetermined range. As a result, for example, an instantaneous rise or fall of an edge due to noise or the like is not determined as a clock pulse, and it is possible to appropriately determine whether or not a clock pulse is being output.

  Further, in the present embodiment, the master 3a waits for a predetermined time T1 longer than the master 3a to start within a predetermined time T2 after the start (S140 in FIG. 5: S140 in FIG. 5). YES), transmission of an arbitrary ID is started (S150). On the other hand, the slave 3b sets the mode signal MD to “1” and switches to the wakeup mode (S270 in FIG. 6), and then completes the wakeup process only after receiving an arbitrary ID from the master 3a. (S300 in FIG. 7: YES), communication processing is started. As a result, it is possible to prevent reception leakage occurring in the slave 3b due to the time difference required for wakeup between the slaves 3b.

  Furthermore, in this embodiment, when there is no sleep prohibition factor (S400: YES in FIG. 11), the master 3a transmits a sleep signal (S420), sets the mode signal MD to “0”, and outputs a clock pulse. Is stopped (S450). On the other hand, after receiving the sleep signal (S500: YES in FIG. 12), the slave 3b determines that the output of the clock pulse is stopped (S560: YES), sets the mode signal MD to “0” ( S570) Transition to the sleep mode. Thereby, the transition to the sleep mode can be realized relatively easily.

  At this time, after transmitting the sleep signal (S420 in FIG. 11), the master 3a waits for the elapse of the predetermined time T5 (S440: YES), and stops outputting the clock pulse (S450). On the other hand, the slave 3b executes the pre-sleep saving process using the predetermined time T5 (S540 in FIG. 12). Thereby, the slave 3b can perform, for example, a parameter saving process, and can stabilize the operation of the slave 3b at the next wake-up.

  The communication system 1 in the present embodiment constitutes the “communication system” in the claims, the master 3a constitutes the “master node”, the slave 3b constitutes the “slave node”, and the bus communication path 5 Configure the “bus communication path”.

  Further, the signal processing unit 10 of the master 3a constitutes “factor presence / absence judging means”, the signal processing unit 10 and the mode management unit 25 of the transceiver 20 constitute “master control means”, and the signal processing unit 30 of the slave 3b “Clock pulse output determination unit” and “wake-up signal transmission unit” are configured, and the signal processing unit 30 and the mode management unit 25 of the transceiver 40 configure “slave control unit”.

  Furthermore, the processing of S100 in FIG. 5 corresponds to the processing as the function of the “factor presence / absence judging means”, the processing of S130 in FIG. 5 and the processing of S420, S440, S450 in FIG. 6, and the process of S260 in FIG. 6 and the process of S560 in FIG. 12 correspond to the process as the function of “clock pulse output determining means”, and the processes of S200 to S250 in FIG. The processing corresponds to processing as a function of “wake-up signal transmission means”, and processing at S270 in FIG. 6, S300 in FIG. 7, and processing at S540 and S570 in FIG. 12 is processing as a function of “slave control means”. It corresponds to.

[Second Embodiment]
In the above embodiment, the detection of the clock pulse from the master 3a by the slave 3b samples the reception data RX received from the bus communication path 5 at the timing of the count clock CCK, and the cycle count value Ci (i = 1, 2). ,...) Depending on whether the ratio between the high level and the low level is within a predetermined range. For example, as shown in FIG. 4, it is determined whether or not the ratio between the count value of the period A at the low level and the count value of the period B at the high level is within a predetermined range.

  On the other hand, the present embodiment is different from the above-described embodiment in that the slave 3b includes a clock detection circuit 43 as indicated by a broken line in FIG. Therefore, here, the configuration of the clock detection circuit 43 will be described.

  The clock detection circuit 43 receives the reception data RX from the reception buffer 24 and outputs a clock detection signal CS to the mode management unit 25. The clock detection circuit 43 includes a falling edge detection circuit 44 and an edge interval determination circuit 45 as shown in FIG. Here, the falling edge detection circuit 44 outputs the edge detection signal ED, and the edge interval determination circuit 45 outputs the clock detection signal CS based on the edge detection signal ED.

  The edge detection circuit 44 will be described. FIG. 16A is a circuit diagram showing the configuration of the edge detection circuit 44, and FIG. 16B is a timing chart showing signals at various parts of the edge detection circuit 44. FIG.

  As shown in FIG. 16A, the edge detection circuit 44 includes an inversion circuit (NOT gate) 51 that inverts the signal level of the reception data RX, and outputs of the reception data RX and the NOT gate 51, that is, the reception data RX. An inverted signal is input, and a negative OR circuit (NOR gate) 52 whose output is at a high level when both are at a low level is output, and the output of the NOR gate 52 is output as an edge detection signal ED.

  As shown in FIG. 16 (b), the edge detection circuit 44 configured in this way has the NOT gate 51 as the edge detection signal ED at every falling edge timing at which the received data RX changes from recessive to dominant. A pulse signal having a width corresponding to the delay time is output.

  Next, the edge interval determination circuit 45 will be described. FIG. 17 is a circuit diagram showing a configuration of the edge interval determination circuit 45, and FIG. 18 is a timing chart showing signals of respective parts of the edge interval determination circuit 45.

As shown in FIG. 17, the edge interval determination circuit 45 includes a switch 61, a capacitor 62, a constant current source 63, a determination circuit 70, and a latch circuit 80.
One end of the capacitor 62 is grounded, and the switch 61 connects the non-grounded end of the capacitor 62 to either the constant current source 63 or the ground (GND). Specifically, the switch 61 connects the non-grounded end of the capacitor 62 to the constant current source 63 while the edge detection signal ED is at a low level. On the other hand, the non-grounded end of the capacitor 62 is connected to GND while the edge detection signal ED is at a high level. A voltage at the non-grounded end of the capacitor 62 (hereinafter referred to as “charging voltage”) Vc is input to the determination circuit 70.

  The determination circuit 70 includes three resistors connected in series to divide the power supply voltage VCC to generate threshold voltages Vt1 and Vt2, a threshold voltage Vt1 at the inverting input terminal, and a voltage at the non-inverting input terminal. The comparator 72 to which the charging voltage Vc is applied, the comparator 73 to which the charging voltage Vc is applied to the inverting input terminal and the threshold voltage Vt2 to the non-inverting input terminal, and the outputs JH and JL of both the comparators 72 and 73 are input. Are both AND circuits 74 that output a determination signal DJ that becomes high level.

  The latch circuit 80 is connected to the input terminal so that the determination signal DJ is applied, the edge detection signal ED is applied to the clock terminal CK, and the output JH of the comparator 72 is applied to the reset terminal CLR. Consists of.

  In the edge interval determination circuit 45 configured as described above, when the edge detection signal ED becomes high level, the switch 61 connects the non-grounded end of the capacitor 62 to GND. Thereby, as shown in FIG. 18, the capacitor 62 is discharged, and the charging voltage Vc drops. On the other hand, when the edge detection signal ED becomes low level, the switch 61 connects the non-grounded end of the capacitor 62 to VCC. As a result, as shown in FIG. 18, the capacitor 62 is charged and the charging voltage VC increases.

  At this time, as shown in FIG. 18, the output JH of the comparator 72 is at a high level in a section where the charging voltage Vc is equal to or lower than the threshold voltage Vt1. Further, in a section where the charging voltage Vc is equal to or higher than the threshold voltage Vt2, the output JL of the comparator 73 is at a high level. The logical product of these outputs JH and JL becomes the judgment signal DJ of the logical product circuit 74. The latch circuit 80 latches the determination signal DJ at the timing of the etch detection signal ED. As a result, the clock detection signal CS from the latch circuit 80 is as shown in FIG. 18 and becomes high level only when a clock pulse is output on the bus communication path 5.

If the clock detection circuit 43 configured in this way is used, the processing of S260 and S270 in FIG. 6 and the processing of S560 and S570 in FIG. 11 can be realized by hardware.
As described above in detail, the present embodiment can provide the same effects as those of the above embodiment. Further, according to the clock detection circuit 43 of the present embodiment, the clock detection signal CS is at a high level only when the clock pulse from the master 3a is output on the bus communication path 5, so that an instantaneous edge due to noise or the like is generated. Therefore, it is possible to appropriately determine whether or not a clock pulse is output. In this case, since the configuration is based on hardware, it is possible to instantaneously perform from the determination of the clock pulse to the switching of the operation mode.

  In the present embodiment, in particular, the clock detection circuit 43 of the slave 3b constitutes “clock pulse output determination means” in the claims, and more specifically, the falling edge detection circuit 45 corresponds to the “edge detection circuit”. The edge interval determination circuit 45 corresponds to an “edge interval determination circuit”.

  As mentioned above, this invention is not limited to embodiment mentioned above at all, In the range which does not deviate from the summary, it can implement with a various form.

  1: communication system, 3: node, 3a: master node, 3b: slave node, 5: bus communication path, 10, 30: signal processing unit, 11: UART (general purpose asynchronous transmission / reception circuit), 12: oscillation circuit, 20, 40: transceiver, 21, 41: timing generation unit, 22, 42: encoding / decoding unit, 23: transmission buffer, 24: reception buffer, 25: mode management unit, 43: clock detection circuit, 44: falling edge detection Circuit: 45: edge interval determination circuit, 51: NOT gate, 52: NOR gate, 61: switch, 62: capacitor, 70: determination circuit, 71: voltage dividing circuit, 72, 73: comparator, 74: AND gate, 80 : Latch circuit

Claims (9)

A master node that outputs a clock pulse including a clock component to a bus communication path, and a slave node that operates in synchronization with the master node by receiving the clock pulse from the master node via the bus communication path. Prepared,
Each of the nodes is a communication system configured to operate in a wake-up mode that is an operation mode capable of executing a pre-assigned function and a sleep mode that is an operation mode in which some functions are stopped,
Wherein each node is,
Factor presence / absence determining means for determining presence / absence of a wakeup factor that causes the transition to the wakeup mode;
A signal transmitting means that is determined by the factor presence / absence determining means to have a wake-up factor,
The master node is
Means for receiving a signal determined to have the wake-up factor;
Means for outputting the clock pulse including the clock component for synchronizing the slave node to the master node as a signal determined to have the wake-up factor;
Master control means for starting output of the clock pulse to the bus communication path when it is determined by the factor presence / absence determination means that the wake-up factor is present;
The slave node is
Clock pulse output determination means for determining whether or not the clock pulse from the master node is output to the bus communication path;
A wakeup signal transmitting means for transmitting a wakeup signal as a signal determined to have the wakeup factor when the wakeup factor is generated in the own node;
Wake-up signal detecting means for detecting the wake-up signal;
When the clock pulse output determining means determines that the clock pulse is output, and when the wakeup signal detecting means detects the wakeup signal, the operation mode is switched to the wakeup mode. Slave control means for performing communication processing,
The communication system characterized by having . The communication system according to claim 1 ,
The clock pulse output determining means is configured to output the clock pulse when a ratio between a high level and a low level in a cycle count value is within a predetermined range based on sampling information with a counting clock having a frequency higher than the clock pulse. A communication system, characterized in that it is determined that it is output. The communication system according to claim 1 ,
The clock pulse output determination means outputs an edge detection circuit that detects an edge of the clock pulse, and a clock detection signal that is inverted depending on whether the clock pulse is output based on an output from the edge detection circuit The communication system is characterized by comprising an edge interval determination circuit that performs the above-described operation. In the communication system according to any one of claims 1 to 3 ,
The slave control means starts communication processing only after receiving predetermined information from the master node after switching the operation mode to the wake-up mode. In the communication system according to any one of claims 1 to 4 ,
The master control means stops the output of the clock pulse and switches the operation mode to the sleep mode,
The slave control unit switches the operation mode to the sleep mode when the clock pulse output determination unit determines that the clock pulse is not output. The communication system according to claim 5 , wherein
The master control means waits for the elapse of a predetermined time after transmitting the sleep signal, and stops outputting the clock pulse,
When the slave control unit receives the sleep signal, the slave control unit executes a pre-sleep saving process prior to switching the operation mode to the sleep mode within the predetermined time. It said master control means in a communication system according to claim 5 or 6, when receiving the provision of a pulse from the slave node until the predetermined time has elapsed, transmits a predetermined information to continue the output of the clock pulse ,
After receiving the sleep signal, the slave control means outputs the specified pulse when the wake-up factor is generated in its own node, and when receiving predetermined information from the master node, starts the communication process and sleeps. A communication system characterized by outputting data indicating prohibition. Master node for use in a communication system according to any one of claims 1-7. Slave node for use in a communication system according to any one of claims 1-7.

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