JP5113229B2 - Communication system, transceiver, node - Google Patents

Description

    The present invention relates to a communication network configured by nodes having a sleep / wake-up function, and more particularly to a technique for individually starting a sleeping node.

  Conventionally, CAN (Controller Area Network) has been standardized as an in-vehicle LAN protocol for realizing communication between a plurality of nodes mounted on a vehicle (ISO 11898-1).

  In CAN, dominant and recessive are defined as signal levels on a communication path, and when any one node outputs a dominant signal, the signal level on the communication path is set to be dominant. .

  In addition, in order to enable clock error correction from a signal received via a communication path, it is also defined that a stuff bit having an inverted signal level is inserted when the same signal level continues for 5 bits.

  Furthermore, in CAN, a physical layer having a sleep / wake-up function is also defined (ISO11898-5). Specifically, a node in the sleep mode, which is an operation mode for stopping the communication function for power saving, wakes up when detecting a dominant on the communication path, and is a normal mode in which the communication function can be used. It is specified to transition to.

  By the way, in such a communication system having a wake-up / sleep function, when there is a node in a sleep mode (hereinafter referred to as a dormant node), the normal operation mode is a normal operation mode while the dormant node is kept in a sleep state. There has been a problem that it is not possible to communicate with only nodes in the mode (hereinafter referred to as startup nodes) or to selectively wake up only necessary nodes.

That is, performing communication means that a dominant appears on the communication path, and therefore, if the activation nodes communicate with each other, all the dormant nodes are activated.
In contrast, if the transceiver of the dormant node monitors the bus and the transceiver detects that the bus is not idle, the protocol controller that analyzes the received frame is activated in a limited manner (power supply is resumed), and the protocol is A technique is described in which the controller starts (wakes up) the entire ECU when the protocol controller determines that the received frame is a frame for wakeup of the own node (see, for example, Patent Document 1). .

JP 2005-529393 A

  By the way, in the protocol controller, since each bit constituting the frame must be individually identified, it is usually necessary for the operation to be supplied with a clock from a highly accurate clock source. That is, in order to start the protocol controller, a high-accuracy clock source must be started at the same time.

  In a situation where the start node and the dormant node coexist, if the communication between the start nodes (that is, the non-idle state of the bus) continues, during that time, the dormant node has a protocol controller and a high-accuracy clock source. There has been a problem that power that cannot be ignored continues to be consumed despite being a dormant node (not functioning as an ECU).

  In order to solve the above problems, the present invention provides a communication system capable of individually waking up a node in the sleep mode, and starting up the own node without increasing the power consumption of the node in the sleep mode. It is intended to make it possible to identify a frame for use.

  In the communication system of the present invention made to achieve the above object, an NRZ (Non Return to Zero) code is used for communication between nodes connected to a communication path. Note that the signal level of the communication channel is inferior in the communication channel over a period corresponding to the allowable number of consecutive bits that is the maximum number of consecutive bits of the same signal level permitted by the generation rule of the frame transmitted to the communication channel. A state in which the signal level continues to be recessive is defined as a standby state.

  When the node changes to a dominant signal level in the communication channel after the communication channel is in a standby state, the node recognizes this as the head of the frame and stops communication via the communication channel. When in the sleep mode, which is an operation mode for reducing power consumption, when a predetermined activation frame is sent to the communication path, the mode is changed to the normal mode, which is an operation mode capable of performing communication via the communication path. It is configured.

  In the communication system of the present invention, a frame used for communication is a start pattern area which is an area for setting a bit pattern for indicating that the frame is a start frame, and a start target. And a designated pattern area which is an area for setting a bit pattern for designating a node, and a point in the frame where the bit pattern satisfies a preset boundary condition as a boundary point is set as an activation pattern area. A unique bit pattern is set in which the length from the beginning of the frame to the boundary point is a preset activation length.

  Then, when the operation mode is the sleep mode, the node measures the length from the head of the frame sent to the communication path to the boundary point, the measurement result is equal to or greater than the activation length, and the specified pattern of the frame is measured. When the bit pattern detected in the area matches the assigned pattern assigned in advance for designating the own node, the normal mode is entered.

  According to the communication system of the present invention configured as described above, whether or not the frame on the communication path has a unique pattern (here, a pattern in which the length from the head of the frame to the boundary point is unique) is determined. By determining, it is identified whether or not it is a start frame without interpreting (decoding) individual bits constituting the frame.

  Therefore, according to the communication system of the present invention, it is not necessary to operate a protocol controller or a high-accuracy clock source when determining whether or not a node in the sleep mode has received a startup frame. The power consumption of a certain node can be greatly reduced.

  Also, instead of unconditionally starting all the nodes that have received the start frame, only the node specified by the bit pattern detected in the specified pattern area is started. As a result, power consumption of the entire communication system can be reduced.

  By the way, the start pattern area of the start frame has a place where the dominant is continuous for 2 bits or more, and the bits before the place are all recessive except for the place specified to be dominant by the frame generation rule. When the pattern is set, the node may be configured to detect a boundary point using a boundary condition that the dominant is continuous for 2 bits or more.

  That is, such a boundary condition can be used when the region length from the beginning of the frame to the boundary point changes depending on the bit pattern set in the region. As a factor that changes the boundary length depending on the set bit pattern, insertion of stuff bits can be considered.

  In addition, as one of the rules for generating a frame, when the same signal level is continuously defined by a predetermined bit, a stuff bit in which the signal level is inverted is inserted, and a recessive pattern is included in the activation pattern area of the activation frame. If an edge that changes from dominant to dominant is set as the target edge and a bit pattern is set such that the number of target edges is minimum (K, where K is an integer of 2 or more), the node is Kth from the head of the frame. The boundary point may be detected using the detection of the target edge as a boundary condition.

  By the way, in the communication system of the present invention, it is desirable that the designated pattern area is encoded for each unit block composed of a plurality of bits. In this case, since it is sufficient to perform processing in units of blocks, if a plurality of bits are M bits, even if decoding is performed using a clock, if the accuracy is 1 / M of the clock required for a normal protocol controller. Processing is possible.

  In this case, for example, the unit block may be composed of 3 bits or more, and 1-bit information may be represented by two types of code patterns having different duty ratios. Specifically, “001”, “011” when the unit block is 3 bits, “0001”, “1110”, etc. when the unit block is 4 bits can be considered.

  In the communication system of the present invention, when CAN (Controller Area Network) is used as the communication protocol in the communication path, the area before the DLC of the data frame in CAN is used as the start pattern area and the data field is used as the designated pattern area. That's fine.

  Next, the transceiver of the present invention described in claim 6 is connected to a communication path that performs communication using an NRZ code (Non Return to Zero), and stops communication through the communication path to suppress power consumption. A node configured to transition to a normal mode, which is an operation mode capable of executing communication via a communication path, when a predetermined activation frame is sent to the communication path in the sleep mode, which is an operation mode for Is used for transmitting and receiving signals via the communication path.

  In the transceiver of the present invention, the start timing detection means exceeds a period corresponding to the allowable number of consecutive bits that is the maximum number of consecutive bits of the same signal level permitted by the generation rule of the frame transmitted to the communication path. The state where the signal level of the communication path continues in a recessive state where the signal level is inferior in the communication path is set as a standby state, and after the communication path enters the standby state, the dominant signal level in the communication path is changed to the dominant signal level. The changed timing is detected as the start timing. In addition, when the start timing is detected by the start timing detection unit when the operation mode is the sleep mode, the end timing detection unit detects a point where the bit pattern of the frame satisfies a preset boundary condition as the end timing.

  Further, whether or not the period length from the start timing detected by the start timing detection means to the end timing detected by the end timing detection means is equal to or longer than a preset activation length. When the period length determining means determines that the period length is equal to or greater than the activation length, the code pattern determining means is preset with the code pattern indicated in the preset designated pattern area of the frame. The assigned pattern is compared, and if the two match, a wakeup signal indicating that the activation frame has been received is output.

The transceiver of the present invention configured as described above can be suitably used when configuring a node in the communication system of the present invention described above.
By the way, the end timing detection means may be configured to use, for example, that a dominant is continuous for 2 bits or more in a frame as a boundary condition.

In this case, the end timing detection means can be configured as follows.
That is, the first charging circuit resets the charging voltage of the first capacitive element to the initial voltage when the signal level of the communication path is recessive, and the first capacitive circuit when the signal level of the communication path is dominant. The device is charged with a constant charging current.

  The end timing detection means includes an end determination threshold set to a magnitude corresponding to the charging voltage of the first capacitive element when charging by the first charging circuit has continued for a period corresponding to 2 bits, Comparing with the charging voltage of the first capacitive element, the end timing is detected by detecting the region where the dominant continues for 2 bits or more. Specifically, the timing at which the charging voltage of the first capacitive element increases beyond the termination determination threshold is detected as the termination timing.

  The end timing detection means configured in this way can detect the end timing without decoding each bit constituting the frame (and without using a high-accuracy clock necessary for the decoding operation). It can be realized by an analog circuit.

  Further, the end timing detection means is configured to use, for example, an edge that changes from recessive to dominant as a target edge, and that a value obtained by counting the target edge in a frame reaches a preset number of boundaries as a boundary condition. May be.

  In this case, the end timing detection means can be constituted by, for example, a counter that operates based on the target edge. That is, the end timing can be detected by an analog circuit without decoding each bit constituting the frame (and without using a high-accuracy clock necessary for the decoding operation).

Further, the period length determination means can be configured as follows, for example.
That is, the second charging circuit resets the charging voltage of the second capacitive element to the initial voltage when the communication path is in the standby state, and keeps the second capacitive element constant when the communication path is in the non-standby state. The battery is charged with a charging current of a magnitude of.

  Then, the period length determination means includes a period determination threshold value set to a magnitude corresponding to the charging voltage of the second capacitive element when charging by the second charging circuit has continued for the activation length or longer, and the second capacitive By comparing with the charging voltage of the element, it is determined whether or not the elapsed period from the start timing is equal to or longer than the activation length.

  The end timing detection means configured as described above determines the period length (bit length) from the start timing to the end timing without counting the individual bits constituting the frame (and thus, the high timing synchronized with each bit). It can be realized by an analog circuit (without using an accurate clock).

By the way, the start timing detection means can be configured as follows, for example.
That is, the third charging circuit resets the charging voltage of the first capacitive element to the initial voltage when the signal level of the communication path is dominant, and the first capacitive circuit when the signal level of the communication path is recessive. The device is charged with a constant charging current.

  Then, the start timing detection means has a standby determination threshold value set to a magnitude corresponding to the charging voltage of the third capacitive element when charging by the third charging circuit has continued for a period corresponding to the allowable number of consecutive bits. Is compared with the charging voltage of the third capacitive element to determine whether or not it is in a standby state. Specifically, when the charging voltage of the third capacitive element is larger than the standby determination threshold, it is determined that the device is in the standby state.

  In the start timing detecting means configured in this way, it is determined whether or not it is in a standby state without counting individual bits constituting the frame (and using a high-accuracy clock synchronized with each bit). Without) an analog circuit.

  In addition, the code pattern to be determined by the code pattern determination means of the transceiver of the present invention is separated by the edge of interest with either the edge changing from recessive to dominant or the edge changing from dominant to recessive as the edge of attention. The code pattern determination means can be configured as follows, for example, when it is composed of two types of patterns having different duty ratios.

  That is, the fourth charging circuit alternately switches the positive charge current having a constant magnitude or the negative charge current having a constant magnitude every time the signal level of the communication path changes to change the fourth capacity. The fourth capacitive element is charged / discharged by supplying to the capacitive element, and the charging voltage of the fourth capacitive element is reset to the initial voltage every time an edge of interest is detected.

  The code pattern determination means determines whether or not the charging voltage of the fourth capacitive element before the fourth charging circuit is reset is greater than a preset threshold every time an edge of interest is detected. It is determined whether the code pattern corresponds to 0 or 1.

That is, when the positive charge current and the negative charge current are the same, the period ends if the duty ratio of the code pattern in the period (unit block) divided by the edge of interest is 50%. Since the charging voltage of the fourth capacitive element at the time coincides with the initial voltage, if the duty ratio is set to a value other than 50%, the code pattern determining means determines either 0 or 1; The duty signal can be decoded.

In the transceiver of the present invention, the decoding means may be configured as follows.
That is, the clock generation circuit generates a clock synchronized with the received frame based on the signal on the communication path, and the decoder circuit decodes the code pattern using the clock generated by the clock generation circuit.

  In other words, since the code pattern is composed of a plurality of bits, the decoder circuit can be operated with a clock with a lower accuracy than the clock for operating a normal protocol controller. Can be used.

  Next, a node according to the present invention described in claim 14 includes the transceiver according to any one of claims 6 to 13. The communication control means transmits and receives signals via the transceiver, and the operation mode transition means transitions the operation mode to the sleep mode when a preset sleep condition is satisfied when the operation mode is the normal mode. When the wakeup signal is output from the transceiver when the operation mode is the sleep mode, the operation mode is returned to the normal mode.

  The node of the present invention configured as described above can be suitably used when configuring the above-described communication system.

1 is a block diagram showing a configuration of a communication system to which the present invention is applied. Explanatory drawing which shows the structure of the data frame in a communication system. The block diagram containing the partial circuit diagram which shows schematic structure of a transceiver. The circuit diagram which shows the structure of a standby state detection circuit, and the timing diagram which shows the operation | movement. The circuit diagram which shows the structure of a starting pattern determination circuit. The timing diagram which shows operation | movement of the starting pattern determination circuit at the time of starting frame reception. The timing diagram which shows operation | movement of the starting pattern determination circuit at the time of non-starting frame reception. The circuit diagram which shows the structure of a designated pattern determination circuit. The timing diagram which shows operation | movement of an edge detection circuit and a duty ratio decoder. The timing diagram which shows operation | movement of the designated pattern determination circuit when it corresponds with an allocation pattern. The timing diagram which shows operation | movement of the designation | designated pattern determination circuit when it is inconsistent with an allocation pattern. The circuit diagram which shows the other structural example of a starting pattern determination circuit. The timing diagram which shows operation | movement of the starting pattern determination circuit at the time of starting frame reception. The timing diagram which shows operation | movement of the starting pattern determination circuit at the time of non-starting frame reception. The block diagram which shows the other structural example of a designated pattern determination circuit.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
<Overall configuration>
FIG. 1 is a block diagram illustrating a configuration of an in-vehicle communication system 1 in which a CAN (Controller Area Network) is used as a communication protocol.

  As shown in FIG. 1, the communication system 1 connects a plurality of electronic control units 10a, 10b, 10c,... Mounted on a vehicle so that they can communicate with each other via a common communication path LN. Each of these electronic control units 10a, 10b, 10c,... Functions as a node. In the following, the electronic control unit is referred to as an ECU, and the ECUs 10a, 10b, 10c, 10d,.

  Among these, the communication path LN is composed of a pair of buses CANH and CANL, and both ends thereof are terminated by termination resistors (not shown). In the communication path LN, a dominant (for example, 0) that is a dominant signal level in the communication path LN or a recessive (for example, 1) that is an inferior signal level in the communication path LN is expressed by the potential difference between the two buses CANH and CANL. The NRZ code is transmitted by the differential signal.

  Specifically, as the ECUs 10a, 10b, 10c, 10d, etc., the engine ECU that controls the engine, the brake ECU that controls the brake control, the steering ECU that controls the steering control, the suspension ECU that controls the suspension control, and the light on / off Various electronic control devices, such as ECU to control, can be mentioned. In FIG. 1, only four ECUs 10 are illustrated, but it goes without saying that the number of ECUs 10 constituting the communication system 1 is not limited to this.

  Further, one of the ECUs 10 (in this case, the ECU 10b) is configured such that an external event serving as a trigger for starting up the entire communication system 1 is input from an in-vehicle device not shown.

  The external event may be generated, for example, when a door of the vehicle is opened or closed, or may be generated when a switch provided for starting up the communication system 1 is operated.

  Furthermore, the ECU 10 is configured to transition between a normal mode that is a normal operation mode when controlling the controlled object and a sleep mode that is an operation mode for stopping communication and suppressing power consumption.

<Frame format>
Here, FIG. 2 is an explanatory diagram showing a configuration of a data frame used for data transmission / reception in the communication system 1.

  As shown in FIG. 2, the data frame is composed of a 1-bit start-of-frame (SOF), an 11-bit identifier (ID) and an 1-bit RTR bit, an arbitration field, 1-bit IDE bit, From a control field consisting of reserved bits (rO) and a 4-bit data length code (DLC), a data field consisting of 0 to 64 bits (ie 0 to 8 bytes) of data, a 15-bit CRC sequence and a 1-bit CRC delimiter CRC field, ACK field consisting of 1-bit ACK slot and ACK delimiter, and 7-bit end-of-frame (EOF).

  In the standard format data frame, as shown by the bold lines in the figure, the SOF, RTR bit, IDE bit, and r0 are always dominant, and the CRC delimiter, ACK delimiter, and EOF are always recessive. That is, there is always a region (RTR, IDE, r0) that is dominant for 3 bits in a data frame. Hereinafter, the area (SOF, ID, RTR, IDE, r0) on the head side from the DLC is also referred to as an activation pattern area, and the data field is also referred to as a designated pattern area.

  When a frame is transmitted, it is defined that transmission is started from the bit next to an intermission (not shown) composed of a recessive 3-bit inserted after the EOF of the preceding frame. . In the frame, when the same signal level continues for N (N = 5 in this case) bits, it is defined that a stuff bit having an inverted signal level is inserted.

<Startup frame>
Further, in the communication system 1, a data frame whose ID is set to 0x7FF is used as an activation frame used when the ECU 10 whose operation mode is the sleep mode is activated (waked up). That is, this ID is prohibited from being used for communication between the ECUs 10 whose operation mode is the normal mode.

  If a part (SOF, ID) of the activation pattern area of the activation frame is represented by a bit pattern, <0> 11111 (0) 11111 (0) 1 is obtained. However, <0> represents SOF and (0) represents a stuff bit. In this way, when ID = 0x7FF, the bit length to a location that satisfies this boundary condition (also referred to as a boundary point) is defined as a boundary condition that a region in which a dominant is continuous for 2 bits or more appears first in a frame. This is the only unique bit pattern that is the longest (14 bits). Specifically, since a dominant of 2 bits continuous appears at RTR and IDE first, the area length of SOF and ID before that is 14 bits including stuff bits.

  In addition, a designation pattern for individually designating the ECU 10 to be activated is set in the designation pattern area (data field) of the activation frame. This designated pattern represents a 1-bit value using a predetermined code pattern for each unit block, with 4 bits as a unit block.

  The code pattern is set so that an edge that changes from recessive to dominant (hereinafter referred to as “target edge”) is always detected at the boundary of the unit block. Specifically, the code pattern represents data “0”. It is assumed that “0111” is used as “0001” and “0001” is used as a code pattern representing data “1”. That is, one bit is set by two types of code patterns having different duty ratios. Hereinafter, data obtained by decoding the code pattern in the designated pattern area is also referred to as a designated code.

  Furthermore, since the end of the last unit block is a boundary with the CRC sequence, and the edge of interest is not always detected, the last unit block has a code pattern corresponding to the above-described data “0” and “1”. Instead, the end pattern “0010” or “0100” is set. That is, the end pattern may be set so that a total of two noticed edges can be reliably detected at locations other than the boundary on the head side and the boundary on the tail side of the unit block.

  Note that the data length code (DLC) of the start frame is always recessive at the end of the DLC area, and always changes from recessive to dominant at the boundary between the control field and the data field (that is, the beginning of the first unit block). Is set to an odd number or 8 bytes with the end of the DLC area being recessive.

  That is, the code length (number of unit blocks) of the specified code is p (bytes) × 8 (bit number of 1 byte) / 4 (bit number of unit block) −1 (end pattern), where p is the data length. Therefore, specifically, it is selected from 1 (when p = 1), 5 (when p = 3), 9 (when p = 5), 13 (when p = 7), and the like. .

<ECU>
Returning to FIG. 1, the ECU 10 is connected to a communication path LN and a microcomputer (hereinafter referred to as “microcomputer”) 11 that executes a control process for controlling each part of the vehicle and a process for communicating with other ECUs. In addition, the data (transmission frame) TxD given from the microcomputer 11 is output to the communication path LN, and the transceiver 12 that receives the data (reception frame) RxD on the communication path LN and inputs the data to the microcomputer 11; 12 is provided with a power supply circuit 13 for supplying power. Further, the microcomputer 11 supplies a standby signal STB for switching the operation of the transceiver 12 to the transceiver 12, and the transceiver 12 provides the microcomputer 11 with a wakeup signal WU or WA indicating that the activation frame has been received via the communication path LN. It is configured to supply.

  Of the two wake-up signals WU and WA, the wake-up signal WA is required to be activated whenever a frame is sent to the communication path LN (for example, an ECU having a function of monitoring an in-vehicle LAN, In the following, it is also referred to as an indiscriminate wakeup signal. The wake-up signal WU is used by the ECU 10 that only needs to wake up when it receives a start frame in which a designated pattern for designating its own ECU is set. Hereinafter, it is also referred to as an individual wake-up signal.

  The configuration of the ECU 10 shown in FIG. 1 is common to any ECU 10, and each ECU 10 has a configuration for realizing functions individually assigned to each ECU 10, in addition to the above configuration. .

<Microcomputer>
In addition to the well-known configuration of a microcomputer comprising a CPU, ROM, RAM, IO port, etc., the microcomputer 11 transmits and receives frames according to the CAN protocol, arbitration control for determining which frames are preferentially processed, and communication errors. A CAN controller 14 that executes processing and the like is provided.

  In addition, the microcomputer 11 includes a clock circuit (not shown) that generates an operation clock for operating the CPU and the CAN controller 14, and the operation of the clock circuit ( As a result, the operation of the CPU itself can be stopped. The operation mode when the clock circuit is operating is the normal mode, and the operation mode when the clock circuit is not operating is the sleep mode.

  Further, the microcomputer 11 sets the standby signal STB to inactive if the operation mode is the normal mode, and sets the standby signal STB to active if the operation mode is the sleep mode.

  The microcomputer 11 executes various controls assigned to it when the operation mode is the normal mode, and executes a sleep process when a predetermined sleep condition is satisfied during the execution.

  In this sleep process, the standby signal STB is switched to active to stop the communication function of the transceiver 12, operate the start frame monitoring function of the transceiver 12, cut off the power supply to the clock circuit, and By stopping itself, the operation mode is changed to the sleep mode.

  Further, the microcomputer 11 is configured such that the clock circuit is activated when the wakeup signal WU (or WA) from the transceiver 12 becomes active (high level in the present embodiment) in the sleep mode. When the clock circuit is activated, the CPU starts its operation and executes a wake-up process.

  In this wake-up process, the standby signal STB is switched to inactive to stop the activation frame monitoring function of the transceiver 12 and operate the communication function of the transceiver 12. Thereby, the operation mode of ECU10 changes to normal mode.

  In addition, the ECU 10 having a function of waking up another ECU transmits an activation frame in which a designated pattern of the ECU to be activated is set when a predetermined activation condition is satisfied when the operation mode is the normal mode. Then, the ECU to be activated is activated (waked up). When the ECU 10b whose operation mode is the sleep mode receives an external event (one of the activation conditions), the microcomputer 11 has the clock circuit in the same manner as when the wakeup signal WU (or WA) is activated. After activation and execution of the above wake-up process, an activation frame is transmitted.

<Transceiver>
FIG. 3 is a block diagram including a partial circuit diagram showing a schematic configuration of the transceiver.
As shown in FIG. 3, the transceiver 12 includes a bus driving transistor TR1 that conducts / cuts off a path that connects one bus CANH that configures the communication path LN and the power supply VCC, and the other bus that configures the communication path LN. A bus driving transistor TR2 for conducting / cutting off a path connecting CANL and ground GND, and a driver 15 for simultaneously turning on / off the transistors TR1 and TR2 according to the signal level of transmission data TxD input from the CAN controller. I have. Note that diodes D1 and D2 for protecting the transistors TR1 and TR2 are connected to the connection ends of the transistors TR1 and TR2 with the buses CANH and CANL, respectively.

  The transceiver 12 compares the signal levels of the buses CANH and CANL (that is, the signal level of the differential signal), and outputs a comparison result as received data RxD supplied to the CAN controller 14. And a receiver 16 including a second comparator CP2 that compares the signal levels of the buses CANH and CANL and outputs the comparison result as a reception signal Rsl. By the way, these comparators (CP1, CP2) compare whether the signal level difference (potential difference) between CANH and CANL is equal to or greater than the value defined in the specification (0.5 V in this embodiment). Output.

  Furthermore, the transceiver 12 detects the activation frame based on the reception signal Rsl from the second comparator CP2, and outputs the wakeup signals WU and WA to the microcomputer 11 according to the activation frame detection unit 17 and the standby signal STB from the microcomputer 11. And a wake-up control unit 18 that controls operations of these units by permitting or prohibiting power supply to the driver 15, the receiver 16, and the activation frame detection unit 17.

  Note that the signal lines of the transmission data TxD and the standby signal STB are pulled up to the power supply voltage VCC via the resistors R1 and R2, respectively. That is, when the ECU 10 enters the sleep mode and the operation of the microcomputer 11 stops, the transmission data TxD input to the transceiver 12 is set to “1” and the standby signal STB is fixed to the active level.

  Further, the buses CANH and CANL are set in a recessive state in which no signal level difference is generated by a known termination resistor (not shown) when the transistors TR1 and TR2 are off.

  The driver 15 turns off the transistors TR1 and TR2 when the transmission data TxD is “1”, and turns on the transistors TR1 and TR2 when the transmission data TxD is “0”. That is, the signal level of the differential signal on the communication path LN is set to 0 V (recessive) when the transmission data TxD is “1”, and to 2 V (dominant) when the transmission data TxD is “0”. .

  The first comparator CP1 and the second comparator CP2 constituting the receiver 16 are configured such that either one operates according to an instruction from the wakeup control unit 18. In addition, the first comparator CP1 is configured using an element having a high operating speed (relatively large power consumption) so that the signal waveform of the differential signal can be accurately reproduced, while the second comparator CP2 is configured to consume power. It is configured using elements with low power.

  When the standby signal STB is in an inactive level (the operation mode is the normal mode), the wakeup control unit 18 permits power supply to the first comparator CP1 of the driver 15 and the receiver 16 via the communication path LN. The communication function for communicating with the other ECU 10 is operated, and the activation frame monitoring function for detecting the activation frame is stopped by prohibiting the power supply to the second comparator CP2 and the activation frame detection unit 17 of the receiver 16.

  On the other hand, when the standby signal STB is at the active level (the operation mode is the sleep mode), the wake-up control unit 18 conversely inhibits the power supply to the first comparator CP1 of the driver 15 and the receiver 16, thereby enabling the communication function. And the power supply to the second comparator CP2 and the start frame detector 17 of the receiver 16 is permitted to operate the start frame monitoring function.

<Startup frame detection unit>
As shown in FIG. 3B, the activation frame detection unit 17 generates a standby state detection signal DTw that becomes high level when the communication path LN is in the standby state based on the reception signal Rsl from the second comparator CP2. When the standby state detection circuit 21 to be generated and the standby state detection signal DTw change from the high level to the low level, that is, the pattern set in the startup pattern area of the frame sent to the communication path LN sets the startup ID. The activation pattern determination circuit 22 that generates the indiscriminate wakeup signal WA whose signal level becomes the active level when the signal is expressed, and set in the designated pattern area of the frame when the indiscriminate wakeup signal WA becomes active If the designated pattern represents the assignment code assigned to the ECU, the signal level is the active level. And a specified pattern decision circuit 23 for generating an individual wake-up signal WU to be Le.

Hereinafter, the circuit configuration and operation of each unit constituting the activation frame detection unit 17 will be described in detail.
<Standby detection circuit>
4A is a circuit diagram showing a detailed configuration of the standby state detection circuit 21, and FIG. 4B is a timing diagram showing the operation of each part of the standby state detection circuit 21.

  As shown in FIG. 4A, the standby state detection circuit 21 has a capacitor 31 that is grounded at one end and is capable of charging and discharging charges, and a non-grounded end of the capacitor 31 according to the signal level of the reception signal Rsl. A switch 33 connected to one of the constant current sources 32, a voltage dividing circuit 34 including a pair of resistors for dividing the power supply voltage VCC and generating a reference voltage (standby determination threshold value) Vref1, and a reference voltage Vref1 at an inverting input terminal. The comparator 35 is applied with a voltage Vc1 applied to the non-inverting terminal of the capacitor 31 (hereinafter referred to as “charging voltage”) at the non-inverting input terminal, and the output of the comparator 35 is output as the standby state detection signal DTw. It is configured.

The switch 33 is set to be connected to the ground side when the received signal Rsl is dominant, and to the constant current source 32 side when it is recessive.
The magnitude of the current supplied from the constant current source 32, the capacity of the capacitor 31, and the magnitude of the reference voltage Vref1 are such that the period during which the capacitor 31 is continuously charged corresponds to 5 bits of the transmission code on the communication path LN. In the following length, the charging voltage Vc1 does not reach the reference voltage Vref1, and the charging voltage Vc1 is set so that the charging voltage Vc1 exceeds the reference voltage Vref1 when the length exceeds a period corresponding to 6 bits. ing.

  In the standby state detection circuit 21 configured as described above, as shown in FIG. 4B, the charging voltage Vc1 is reset to 0V which is the initial voltage when the reception signal Rsl is dominant, and the reception signal Rsl is recessive. It increases at a constant rate for a while.

  When the recessive continuous number is less than 6 bits and the charging voltage Vc1 is equal to or lower than the reference voltage Vref1, the standby state detection signal DTw becomes an inactive level indicating that the standby state is not set. On the other hand, when the recessive continuous number becomes 6 bits or more and the charging voltage Vc1 exceeds the reference voltage Vref1, the standby state detection signal DTw indicates that the standby state detection signal DTw is in a standby state until the reception signal Rsl changes to a dominant state thereafter. It becomes the active level shown.

  Note that the 6 bits, which are the criteria for determining whether or not to be in the standby state, are based on a stuff bit insertion rule (inserting a stuff bit having an inverted signal level when the same signal level continues for 5 bits), which is one of the frame generation rules. Based on 5 bits, which is the maximum continuous number (allowable continuous bit number) of the same signal level allowed in the frame, a value larger than this is set.

<Startup pattern determination circuit>
FIG. 5 is a circuit diagram showing a detailed configuration of the activation pattern determination circuit 22. 6 and 7 are timing charts showing the operation of each part of the activation pattern determination circuit 22. The numbers in parentheses shown in the figure indicate how many bits are from the beginning of the frame.

  As shown in FIG. 5, the activation pattern determination circuit 22 is provided in the supply path of the reception signal Rsl and receives the timing of the falling edge of the standby state detection signal DTw (hereinafter referred to as “start timing”), that is, the reception of the frame. Becomes the ON state (the state where the reception signal Rsl is supplied to the output side) at the timing of starting the signal, and the OFF state (the ground potential is applied to the output side) at the timing of the rising edge of the end signal DTe (hereinafter referred to as “end timing”). When a region in which the dominant continues for a period corresponding to 2 bits of the transmission code on the communication path LN is detected from the switch 24 that is in a state of being supplied) and the received signal Rsl supplied via the switch 24, the active level ( End timing detection circuit 50 that generates an end signal DTe that becomes a high level), and elapses from the start timing A period length determination circuit that generates an indiscriminate wakeup signal WA that remains active (high level) until the end timing when a period corresponding to a preset activation length elapses before reaching the end timing. 40.

<End timing detection circuit>
The end timing detection circuit 50 is configured to charge / discharge electric charge and has one end grounded, and according to the signal level of the reception signal Rsl, the non-ground end of the capacitor 51 is set to either the ground level or the constant current source 52. A switch 53 connected to the power supply voltage, a voltage dividing circuit 54 for generating a reference voltage (end determination threshold value) Vref3 consisting of a pair of resistors that divide the power supply voltage VCC, and a reference voltage Vref3 is applied to the inverting input terminal. And a comparator 55 to which a voltage Vc3 (hereinafter referred to as “charging voltage”) Vc3 of the capacitor 51 is applied. The output of the comparator 55 is output as an end signal DTe.

The switch 53 is set to be connected to the ground side when the received signal Rsl is recessive and to the constant current source 52 side when the received signal Rsl is dominant.
The magnitude of the current supplied from the constant current source 52, the capacity of the capacitor 51, and the magnitude of the reference voltage Vref3 are such that the period during which the capacitor 51 is continuously charged is equal to or shorter than the period corresponding to one bit of the transmission code. Then, when the charging voltage Vc3 does not reach the reference voltage Vref3 and exceeds the reference voltage Vref3 (in this embodiment, the length corresponding to almost 2 bits), the charging voltage Vc3 exceeds the reference voltage Vref3. It is set to be a large size.

<Period length determination circuit>
The period length determination circuit 40 is configured to charge / discharge electric charge and has one end grounded, and according to the standby state detection signal DTw and the end signal DTe, the non-ground end of the capacitor 41 is connected to the ground level or constant current source 42. A switch 43 connected to any one of the above, a voltage dividing circuit 44 comprising a pair of resistors for dividing the power supply voltage VCC and generating a reference voltage (period determination threshold value) Vref2, and a reference voltage Vref2 applied to the inverting input terminal. The comparator 45 has a non-grounded terminal voltage (hereinafter referred to as “charging voltage”) Vc2 applied to the inverting input terminal, and is configured to output the output of the comparator 45 as an indiscriminate wakeup signal WA. Yes.

  The switch 43 is set to switch to the constant current source 42 side at the falling edge timing of the standby state detection signal DTw, that is, the start timing, and to switch to the ground side at the timing of the rising edge of the end signal DTe, that is, the end timing. Has been.

  The magnitude of the current supplied from the constant current source 42, the capacity of the capacitor 41, and the magnitude of the reference voltage Vref2 are such that the period during which the capacitor 41 is continuously charged is equal to or shorter than the period corresponding to 15 bits of the transmission code. In this case, the charging voltage Vc2 does not reach the reference voltage Vref2, and if the charging voltage Vc2 exceeds the reference voltage Vref2 (i.e., the length corresponding to the 16th bit), the charging voltage Vc2 exceeds the reference voltage Vref2. Is set to

  That is, the length of the period corresponding to the reference voltage Vref2 is the start length, and specifically, a location slightly exceeding the boundary between the 15th and 16th bits of the frame (at least the center of the bit) It is set so as to correspond to the length of the area up to the head).

<Operation of startup pattern determination circuit>
In the startup pattern determination circuit 22 configured in this way, as shown in FIGS. 6 and 7, the end timing detection circuit 50 and the period length determination circuit 40 are at the falling edge of the standby state detection signal DTw, that is, at the start timing. Start operation.

  When the activation ID (= 0x7FF) is set in the activation pattern area of the frame transmitted to the communication path LN, as shown in FIG. 6, during the period of SOF and ID in the activation pattern area, Since the dominant does not continue for two bits, in the end timing detection circuit 50, the charging voltage Vc3 does not exceed the reference voltage Vref3. Since the periods of RTR, IDE, and r0 following ID are defined to be dominant, the charging voltage Vc3 is near the boundary between IDE (the 16th bit from the top) and r0 (the 17th bit from the top). The reference voltage Vref3 is exceeded and the end signal DTe becomes an active level. Then, the state of the switch 24 is switched, and further, the state of the switch 53 is switched, so that the charging voltage Vc3 is reset to 0V which is the initial voltage, so that the end signal DTe returns to the inactive level.

  At this time, in the period length determination circuit 40, the charging voltage Vc2 continues to increase at a constant rate from the start timing, and the period from the start timing slightly exceeds the period corresponding to the boundary between the 15th and 16th bits. At this time, the charging voltage Vc2 exceeds the reference voltage Vref2. As a result, the indiscriminate wakeup signal WA becomes active level, and then the state of the switch 43 is switched at the end timing when the end signal DTe becomes active level, whereby the charging voltage Vc2 is reset to 0V which is the initial voltage. Therefore, the indiscriminate wakeup signal WA returns to the inactive level.

  On the other hand, when an ID other than the activation ID is set in the activation pattern area of the frame transmitted to the communication path LN, when two stuff bits are inserted other than the activation ID, ID = 0x7FE is set. In other cases, the stuff bit inserted during the ID period is 1 or less.

In the latter case, the maximum period of SOF and ID is 13 bits, and FIG. 7 shows an example of ID = 0x7FD.
In this case, since the dominant does not continue for 2 bits during the SOF and ID periods in the startup pattern area, the end timing detection circuit 50 uses IDE (15th bit from the head) and r0 (16th bit from the head). ) Near the boundary (but around the 15th bit), the charging voltage Vc3 exceeds the reference voltage Vref3, and the end signal DTe becomes the active level.

  That is, since the period from the start timing to the end timing is shorter than the activation length (length corresponding to the 16th bit), the charging voltage Vc2 of the period length determination circuit 40 reaches the reference voltage Vref3 at the end timing. Without being reset to 0V, which is the initial voltage, and the indiscriminate wakeup signal WA is maintained at the inactive level without changing to the active level.

  In the former case (ID = 7EF), the period of SOF and ID is 14 bits, but since the last bit of ID is dominant, the end timing detection circuit 50 uses RTR (15th bit from the head) and IDE ( In the vicinity of the boundary with the 16th bit from the head), the charging voltage Vc3 increases beyond the reference voltage Vref3, and the end signal DTe becomes an active level. As a result, the operation of the period length determination circuit 40 is the same as in the latter case described above.

  In addition, when the number of inserted stuff bits is 0, or when there are locations where the dominant is continuous for 2 bits or more in the activation pattern area, the period from the start timing to the end timing is naturally the activation length (the 16th bit). Therefore, the indiscriminate wakeup signal WA does not change to the active level.

<Designated pattern determination circuit>
FIG. 8 is a circuit diagram showing a detailed configuration of the designated pattern determination circuit 23. 9 and 10 are timing charts showing the operation of each part of the designated pattern determination circuit 23. FIG.

  As shown in FIG. 8, the designated pattern determination circuit 23 is provided in the supply path of the reception signal Rsl, and the edge timing at which the indiscriminate wakeup signal WA changes from the inactive level (low level) to the active level (high level). The switch 61 is turned on at an edge timing when an enable signal EN described later changes from an active level (low level) to an inactive level (high level), and a reception signal Rsl supplied via the switch 61. The edge detection circuit 62 that generates the edge detection signal ED representing the timing of the target edge (the edge that changes from recessive to dominant) and the reception signal Rsl supplied via the switch 61 are decoded by decoding as a duty signal. A duty ratio decoder 63 for generating data Ddc; Based on the edge detection signal ED and the decoded data Ddc, a data comparison circuit 64 is provided that generates an individual wakeup signal WU that becomes an active level when the decoded data Ddc matches the activation code assigned to the ECU. .

Hereinafter, the circuit configuration and operation of each part constituting the designated pattern determination circuit 23 will be described in detail.
<Edge detection circuit>
The edge detection circuit 62 receives an inversion circuit (NOT gate) 75 that inverts the signal level of the reception signal Rsl, and outputs of the reception signal Rsl and the NOT gate 75, that is, an inversion signal of the reception signal Rsl. At this time, it is composed of a negative OR circuit (NOR gate) 76 whose output becomes high level, and the output of the NOR gate 76 is outputted as the edge detection signal ED.

  As shown in FIG. 9A, the edge detection circuit 62 configured in this way has a width corresponding to the delay time of the NOT gate 75 at each edge timing of the received signal Rsl as the edge detection signal ED. Outputs a pulse signal.

<Duty ratio decoder>
Returning to FIG. 8, in the duty ratio decoder 63, a capacitor 71a capable of charging and discharging charges is connected between the inverting input terminal and the output terminal, and a reference voltage (sign determination threshold) Vref4 is applied to the non-inverting input terminal. When the edge detection signal ED is at a high level, the well-known integration circuit 71 composed of an operational amplifier connected to the inverting input terminal so that the reception signal Rsl is applied via a resistor is short-circuited when the edge detection signal ED is at a high level. The switch 72 is composed of a comparator 73 in which the output Vy of the integrating circuit 71 is applied to the inverting input terminal and the reference voltage Vref4 is applied to the non-inverting input terminal, and a D-type flip-flop. And a latch circuit 74 that latches at the timing of ED, and is configured to output the output of the latch circuit 74 as decoded data Ddc.

  The reference voltage Vref4 is set so that the high level (recessive) of the received signal Rsl is VH and the low level (dominant) is VL, and the intermediate value between them, that is, Vref4 = (VH + VL) / 2.

  In the duty ratio decoder 63 configured in this way, as shown in FIG. 9B, every time a noticed edge is detected, the charging voltage of the capacitor 71a which is the output of the integrating circuit 71 (on the output terminal side of the operational amplifier). The voltage Vy is initialized to the reference voltage Vref4. While the reception signal Rsl is at a low level, the charging voltage Vy increases at a constant rate (that is, charged with a positive charging current), and when the reception signal Rsl changes to a high level, the charging voltage Vy increases. Decrease at the same constant rate (that is, charged with a negative charging current).

  That is, if the signal level of the received signal Rsl is longer than the low level period during the continuous attention edge, the charging voltage Vy becomes lower than the reference voltage Vref4 at the end of the period. On the contrary, if the low level period is longer than the high level period, the charging voltage Vy becomes larger than the reference voltage Vref4 at the end of the period. In other words, the interval between successive edges of interest is regarded as one duty code, and the duty code is decoded into binary digital data depending on whether the duty ratio of the duty code is 50% or more.

  In the designated pattern area (that is, the data field) of the start frame, since the edge of interest is set to be detected for every 4-bit unit block, the bit pattern in the designated pattern area is the duty ratio decoder 63. Thus, each unit block is decoded.

<Data comparison circuit>
Returning to FIG. 8, the data comparison circuit 64 includes a decode data holding circuit 81 including a multi-stage shift register that receives the decode data Ddc and operates using the edge detection signal ED as a shift clock, a plurality of switches, and the like. The allocation pattern setting circuit 83 in which the signal level corresponding to the allocation pattern allocated to the allocation pattern is set, and the decode data held in the decode data holding circuit 81 and the setting contents of the allocation pattern setting circuit 83 match each other. And a comparator 82 for generating comparison data Dcp.

  In addition, the data comparison circuit 64 receives the permission signal EN and the comparison data Dcp representing the timing at which the comparison data Dcp indicating the desired comparison result is output from the comparator 82 based on the edge detection signal ED and the standby state detection signal DTw. The timing generation circuit 84 generates a latch clock LCK representing the latch timing, and a D-type flip-flop circuit. An enable signal EN is applied to the reset terminal, and the comparison data Dcp from the comparator 82 is used as the timing of the latch clock LCK. And a latch circuit 85 that latches the signal, and the signal latched by the latch circuit 85 is output as an individual wakeup signal WU.

  The enable signal EN changes to an active level (low level) that permits the operation of the latch circuit 85 at a timing between the last unit block and the end pattern, and the standby state detection signal DTw changes from the inactive level to the active level. It is generated so as to change to an inactive level (high level) that inhibits the operation of the latch circuit 85 at the changing timing. Further, the latch clock LCK changes from the low level to the high level from the time when the enable signal EN becomes the low level to the timing of the target edge of the end pattern, and the standby state detection signal DTw changes from the inactive level to the active level. It is generated so as to return to the low level at the changing timing.

  The timing generation circuit 84 is configured to calculate the number of edges of interest that are generated after the reception signal Rsl is supplied via the switch 61, that is, after the indiscriminate wakeup signal WA changes to the active level (high level). In consideration, the counter, the shift register, the latch circuit, the delay circuit, and the like can be easily created by appropriately combining them. Therefore, detailed description thereof is omitted here.

  In the data comparison circuit 64 configured as described above, the decoded data Ddc, which is the decoding result of the duty ratio decoder 63, is sequentially held in the decode data holding circuit 81, and the held contents and assignment pattern setting are set by the comparator 82. It is compared whether the setting contents of the circuit 83 match.

  As shown in FIG. 10, all of the decoded data Ddc is decoded data from the timing of the target edge between the last unit block and the end pattern until the timing of the next target edge, as shown in FIG. Comparison data Dcp held in the holding circuit 81 and indicating an effective comparison result with the assigned pattern is obtained. The comparison data Dcp is latched in the latch circuit 85 by the latch clock LCK that rises at the timing when this effective comparison result is obtained.

  FIG. 10 shows a case where the designation code obtained by decoding the designation pattern set in the designation pattern area matches the assigned pattern, and the comparison data Dcp matches at the timing when the latch clock LCK rises. Since the signal level is expressed (high level), the individual wakeup signal WU, which is the output of the latch circuit 85, changes to the active level at this timing. Thereafter, the individual wakeup signal WU returns to the inactive level at the timing when the standby state detection signal DTw changes to the active level.

  FIG. 11 shows a case where the designated code does not match the assigned pattern. Since the comparison data Dcp is at a signal level (low level) indicating a mismatch at the timing when the latch clock LCK rises, the individual codes are individually displayed. The wake-up signal WU is held at an inactive level.

<Effect>
As described above, in the communication system 1, the ECU 10 in the sleep mode monitors the communication path LN, and the area length from the beginning of the frame (start timing) to the location where the dominant is 2 bits continuous (end timing) is the activation length. Decoded data that recognizes a larger frame as a startup frame (changes the indiscriminate wakeup signal WA to an active level) and decodes the specified pattern set in the specified pattern area of the startup frame as a duty signal When the designation code represented by Ddc matches the assigned pattern previously assigned to the own ECU 10, the normal mode is entered (the individual wakeup signal WU is changed to the active level).

  Therefore, according to the communication system 1, it is not necessary to operate the CAN controller 14 or the clock circuit in order to determine whether or not the activation frame has been received, so that the power consumption of the ECU 10 in the sleep mode is greatly reduced. be able to.

  Further, according to the communication system 1, not all nodes that have received the activation frame are activated unconditionally, but only the node specified in the activation frame is activated, so that a node that does not need to be activated is activated wastefully. In other words, the power consumption of the entire communication system 1 can be reduced.

<Correspondence with Invention>
In the present embodiment, the standby state detection circuit 21 corresponds to start timing detection means, the end timing detection circuit 50 corresponds to end timing detection means, the period length determination circuit 40 corresponds to period length determination means, and the designated pattern determination circuit 23 corresponds to code pattern determination means. To do.

  The capacitor 51 in the end timing detection circuit 50 is the first capacitive element, the constant current source 52 and the switch 53 are the first charging circuit, and the capacitor 41 in the period length determination circuit 40 is the second capacitive element, the constant current. The source 42 and the switch 43 are the second charging circuit, the capacitor 31 in the standby state detection circuit 21 is the third capacitive element, the constant current source 32 and the switch 33 are the third charging circuit, and the capacitor 71a in the duty ratio decoder 63 is The fourth capacitive element and the integration circuit 71 correspond to a fourth charging circuit.

  Furthermore, the configuration for the CAN controller 14 to start and stop the communication control means, the wake-up process executed by the microcomputer 11, the sleep process, and the clock circuit that is a part of the microcomputer 11 corresponds to the operation mode transition means.

[Second Embodiment]
Next, a second embodiment will be described.
In the second embodiment, the ID used for activation and a part of the configuration of the activation pattern determination circuit 22a are only different from those in the first embodiment. Therefore, the differences will be mainly described below. .

<Startup frame>
In the present embodiment, a data frame whose ID is set to 0x078 is used as the activation frame. That is, this ID is prohibited from being used for communication between the ECUs 10 whose operation mode is the normal mode.

  When the activation pattern area of the activation frame is represented by a bit pattern, [0] [0000 (1) 1111 (0) 00] [0 (1) 00] is obtained. However, the first bracket represents the SOF, the second bracket represents ID, the third bracket represents RTR, IDE, r0, and (0) and (1) represent stuff bits.

  This ID (= 0x078) has an edge that changes from recessive to dominant as an attention edge, and the bit length from the beginning (start timing) of the frame to the third attention edge (end timing) is the longest (16 bits). The only unique bit pattern. From another viewpoint, it is the only unique bit pattern in which the number of target edges detected in the activation pattern area is the minimum number of boundaries K (K = 3).

<Startup pattern determination circuit>
FIG. 12 is a circuit diagram showing the configuration of the activation pattern determination circuit 22a, and FIGS. 13 and 14 are timing diagrams showing the operation of each part of the activation pattern determination circuit 22a. The numbers in parentheses shown in the figure indicate how many bits are from the beginning of the frame.

  As shown in FIG. 12, the activation pattern determination circuit 22a includes a switch 24, an end timing detection circuit 50a, and a period length determination circuit 40, just like the activation pattern determination circuit 22 in the first embodiment, and only the end timing detection circuit 50a. The configuration is different from that of the first embodiment.

  However, in the period length determination circuit 40, the magnitude of the current supplied by the constant current source 42, the capacity of the capacitor 41, and the magnitude of the reference voltage Vref2 are set so that the period during which the capacitor 41 is continuously charged is 15 bits of the transmission code. When the length is equal to or shorter than the corresponding period, the charging voltage Vc2 does not reach the reference voltage Vref2, and if the length exceeds that (that is, the length applied to the 16th bit), the charging voltage Vc2 becomes the reference voltage. The voltage is set so as to exceed the voltage Vref2.

<End timing detection circuit>
The end timing detection circuit 50a receives a low-pass filter 56 provided for removing distortion of the reception signal Rsl supplied via the switch 24 and a reception signal Rsl supplied via the low-pass filter 56 as an input clock. Assuming that the synchronous counter 57 that counts the number of edges of interest in the received signal Rsl and the first digit Q0 and the second digit Q1 of the output of the counter 57 are input and both are at the high level, that is, the count value Is provided with an AND circuit (AND gate) 58 for generating an end signal DTe that becomes a high level (active level) when K reaches the boundary number K (= 3). The counter 57 is connected so that the count value is cleared when the end signal DTe is at the active level.

<Operation of startup pattern determination circuit>
In the startup pattern determination circuit 22a configured in this way, as shown in FIGS. 13 and 14, the end timing detection circuit 50 and the period length determination circuit 40 are at the falling edge of the standby state detection signal DTw, that is, at the start timing. Start operation.

  When the activation ID (= 0x078) is set in the activation pattern area of the frame sent to the communication path LN, the first edge of interest is generated at the start timing as shown in FIG. The third target edge occurs at the boundary between the 10th bit and the 11th bit from the head, and the third target edge is the 16th bit (stuff bit inserted after RTR) and the 17th bit (IDE) from the top. Occurs at the boundary. That is, the end signal DTe changes to the active level at the boundary between the 16th and 17th bits from the beginning, and this timing is the end timing.

  Since the charging voltage Vc2 of the period length determination circuit 40 exceeds the reference voltage Vref2 near the boundary between the 15th and 16th bits (however, the first half of the 16th bit), the indiscriminate wakeup signal is given before the end timing. WA becomes an active level. In addition, since the state of the switch 43 is switched at the subsequent end timing, the charging voltage Vc2 is reset to 0V, which is the initial voltage, so the indiscriminate wakeup signal WA returns to the inactive level.

  On the other hand, when an ID other than the activation ID is set in the activation pattern area of the frame transmitted to the communication path LN, the third edge of interest is the 16th and 17th bits from the head as shown in FIG. It always occurs at a timing earlier than the boundary. However, the figure shows a case where ID = 0x551.

  That is, since the end signal DTe becomes the active level at a timing earlier than the timing when the charging voltage Vc2 exceeds the reference voltage Vref2, the indiscriminate wakeup signal WA does not change to the active level. Inactive level is maintained.

<Effect>
As described above, in the present embodiment, the ID set in the activation pattern area and the method for detecting the ID are different, and the other operations are the same as those in the first embodiment. The same effect as in the case of can be obtained.

Note that the end timing detection circuit 50a in the present embodiment corresponds to the end timing detection means described in claim 9.
[Other Embodiments]
As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, it is possible to implement in various aspects.

  For example, in the above embodiment, the receiver 16 is configured with two comparators CP1 and CP2, and the comparator to be used is switched depending on the operation mode. However, the receiver is configured with one comparator CP1 and the output of the comparator CP1. May be switched to the microcomputer 11 as the reception data RxD or to the activation frame detection unit 17 as the reception signal Rsl depending on the operation mode.

  In the designated pattern determination circuit 23 of the above embodiment, the duty ratio decoder 63 regards the bit pattern for each unit block set in the designated pattern area as a duty signal, and the length of the period of two signal levels in the unit block. , The start frame is recognized (for example, the indiscriminate wakeup signal WA becomes active) as in the designated pattern determination circuit 23a shown in FIG. ), The PLL circuit 91 for reproducing the clock signal from the received signal Rsl may be operated, and the decoder 92 may be configured to decode the bit pattern of the data field according to the clock generated by the PLL circuit 91. In this case, the data comparison circuit 93 may generate the enable signal EN and the latch clock LCK based on the clock generated by the PLL circuit 91 instead of the edge detection signal ED. In this case, the bit pattern set in the designated pattern area of the start frame is set for each unit block composed of a plurality of bits, and can be decoded with a clock having a lower accuracy than the clock used by the CAN controller 14. Any pattern is possible. Here, the PLL circuit 91 corresponds to the clock generation circuit in the present invention (claim 13), and the decoder 92 corresponds to the decoder circuit.

  In the above-described embodiment, it is determined that the dominant state is in the standby state when the dominant continues for 6 bits or more. However, the present invention is not limited to this. As long as it is N + 1 bits or more and 11 bits or less. Note that 11 bits is the total number of bits of ACK delimiter (1 bit), EOF (7 bits), and intermission (3 bits) inserted between frames.

DESCRIPTION OF SYMBOLS 1 ... Communication system 10 (10a-10d) ... Electronic control unit 11 ... Microcomputer 12 ... Transceiver 13 ... Power supply circuit 14 ... CAN controller 15 ... Driver 16 ... Receiver 17 ... Startup frame detection part 18 ... Wake-up control part 21 ... Standby State detection circuit 22, 22a ... Startup pattern determination circuit 23, 23a ... Designated pattern determination circuit 24, 61, 72 ... Switch 31, 41, 51, 71a ... Capacitor 32, 42, 52 ... Constant current source 33, 43, 53 ... Switch 34, 44, 54 ... Voltage divider circuit 35, 45, 55, 73 ... Comparator 40 ... Period length determination circuit 50, 50a ... End timing detection circuit 56 ... Low pass filter 57 ... Counter 62 ... Edge detection circuit,
63: Duty ratio decoder 64, 93 ... Data comparison circuit 71 ... Integration circuit 74, 85 ... Latch circuit 75 ... NOT gate 76 ... NOR gate 81 ... Decoded data holding circuit 82 ... Comparator 83 ... Allocation pattern setting circuit 84 ... Timing generation Circuit 91 ... PLL circuit 92 ... Decoder 93 ... Data comparison circuit

Claims (14)

An NRZ (Non Return to Zero) code is used for communication between nodes connected to the communication path, and the node has the maximum number of consecutive bits of the same signal level permitted by a generation rule of a frame sent to the communication path. The state in which the signal level of the communication path continues in a recessive state, which is an inferior signal level in the communication path, exceeds the period corresponding to the allowable continuous bit number, and the communication path is in the standby state. Then, when it changes to a dominant signal level in the communication path, this is recognized as the head of the frame, and the operation mode for suppressing power consumption by stopping communication via the communication path. In a certain sleep mode, when a predetermined activation frame is sent to the communication path, a normal mode that is an operation mode capable of executing communication via the communication path A a communications system configured to transition,
The start frame is for setting a start pattern area which is an area for setting a bit pattern for indicating that the frame is a start frame and a bit pattern for specifying a node to be started. And a specified pattern area that is an area of the frame, and a point in the frame where the bit pattern satisfies a preset boundary condition as a boundary point, the start pattern area includes the start point of the frame to the boundary point. A unique bit pattern whose length is the preset activation length is set,
The node measures the length from the head of the frame sent to the communication path to the boundary point when the operation mode is the sleep mode, and the measurement result is equal to or greater than the activation length, and A communication system, wherein a transition is made to a normal mode when a bit pattern detected in a designated pattern area of a frame matches an assigned pattern assigned in advance for designating its own node. The activation pattern area of the activation frame has a location where a dominant is continuous for 2 bits or more, and is a recessive bit except for a location defined as a dominant in the frame generation rule in an area before the location. The pattern is set,
2. The communication system according to claim 1, wherein the node detects the boundary point using the boundary condition that a dominant is continuous for 2 bits or more. One of the rules for generating a frame includes inserting a stuff bit in which the signal level is inverted when the same signal level continues in a predetermined bit.
In the activation pattern area of the activation frame, a bit pattern is set such that the edge that changes from recessive to dominant is the attention edge, and the number of the attention edges is the minimum (K, where K is an integer of 2 or more).
2. The communication system according to claim 1, wherein the node detects the boundary point using the boundary condition that the Kth target edge from the head of the frame is detected.   The communication system according to any one of claims 1 to 3, wherein the designated pattern area is encoded for each unit block composed of a plurality of bits.   A CAN (Controller Area Network) is used as a communication protocol in the communication path, an area before a DLC of a data frame in the CAN is used as the start pattern area, and a data field is used as the designated pattern area. The communication system according to any one of claims 1 to 4. Connected to a communication path that performs communication using NRZ code (Non Return to Zero), predetermined activation in the sleep mode, which is an operation mode for stopping communication through the communication path and suppressing power consumption When a frame is transmitted to the communication path, a node configured to shift to a normal mode, which is an operation mode capable of performing communication via the communication path, transmits and receives signals via the communication path. Transceiver used in
The signal level of the communication path exceeds the period corresponding to the allowable number of consecutive bits that is the maximum number of consecutive bits of the same signal level allowed by the generation rule of the frame transmitted to the communication path. A state in which the recessive signal level continues in a recessive state is set as a standby state, and after the communication path is in a standby state, a timing at which the dominant signal level in the communication path changes to a dominant is detected as a start timing. Timing detection means;
When the operation mode is a sleep mode, when the start timing is detected by the start timing detection unit, an end timing detection unit that detects, as an end timing, a location where the bit pattern of the frame satisfies a preset boundary condition;
Period length determination for determining whether the period length from the start timing detected by the start timing detection means to the end timing detected by the end timing detection means is equal to or greater than a preset activation length Means,
When the period length determining means determines that the period length is equal to or greater than the activation length, the period length determination means compares the code pattern indicated in the preset designated pattern area of the frame with a preset allocation pattern. Code pattern determination means for outputting a wake-up signal indicating that the activation frame has been received when the two match,
A transceiver comprising:   The transceiver according to claim 6, wherein the end timing detection unit uses, as the boundary condition, that a dominant is continuous for 2 bits or more in the frame. The end timing detection means includes
A first capacitive element capable of charging and discharging electric charge;
When the signal level of the communication path is recessive, the charging voltage of the first capacitive element is reset to an initial voltage, and when the signal level of the communication path is dominant, the first capacitive element is set to a certain level. A first charging circuit for charging with a charging current of
With
An end determination threshold set to a magnitude corresponding to a charging voltage of the first capacitive element when charging by the first charging circuit continues for a period corresponding to 2 bits, and the first capacitive The transceiver according to claim 7, wherein a region in which a dominant is continuous by 2 bits or more is detected by comparing with a charging voltage of an element. The end timing detection means includes
7. The transceiver according to claim 6, wherein an edge that changes from recessive to dominant is used as an edge of interest, and the value obtained by counting the edge of interest in the frame reaches a preset number of boundaries. . The period length determination means includes
A second capacitive element capable of charging and discharging electric charge;
When the communication path is in a standby state, the charging voltage of the second capacitive element is reset to an initial voltage, and when the communication path is in a non-standby state, the second capacitive element is charged with a certain amount. A second charging circuit for charging with current;
With
A period determination threshold that is set to a magnitude corresponding to the charging voltage of the second capacitive element when charging by the second charging circuit has continued for the startup length or longer, and the charging voltage of the second capacitive element The transceiver according to claim 6, wherein it is determined whether or not an elapsed period from the start timing is equal to or longer than the activation length. The start timing detecting means includes
A third capacitive element capable of charging and discharging electric charge;
When the signal level of the communication path is dominant, the charging voltage of the third capacitive element is reset to the initial voltage, and when the signal level of the communication path is recessive, the third capacitive element is set to a certain level. A third charging circuit for charging with the charging current,
With
A standby determination threshold set to a magnitude corresponding to a charging voltage of the third capacitive element when charging by the third charging circuit continues for a period corresponding to the allowable number of consecutive bits; The transceiver according to any one of claims 6 to 10, wherein it is determined whether or not it is in a standby state by comparing with a charging voltage of a capacitive element. The code pattern is composed of a plurality of bits separated by the target edge, with either one of the edge changing from recessive to dominant or the edge changing from dominant to recessive as the target edge, and two types of duty ratios are different. Consists of patterns,
The code pattern determination means includes
A fourth capacitive element capable of charging and discharging electric charge;
By switching a positive charge current having a constant magnitude or a negative charge current having a constant magnitude every time the signal level of the communication path changes, the charge current is supplied to the fourth capacitive element. A fourth charging circuit that charges and discharges the fourth capacitive element and resets the charging voltage of the fourth capacitive element to an initial voltage each time the edge of interest is detected;
With
Every time the edge of interest is detected, the code pattern depends on whether the charging voltage of the fourth capacitive element before the fourth charging circuit is reset is larger than a preset code determination threshold. 12. The transceiver according to claim 6, wherein it is determined whether 0 corresponds to 0 or 1. The code pattern determination means includes
A clock generation circuit that generates a clock synchronized with the received frame based on the signal on the communication path;
A decoder circuit for decoding the code pattern using the clock generated by the clock generation circuit;
The transceiver according to any one of claims 6 to 11, characterized by comprising: A transceiver according to any one of claims 6 to 13,
Communication control means for transmitting and receiving signals via the transceiver;
When a preset sleep condition is satisfied when the operation mode is the normal mode, the operation mode transitions to the sleep mode, and when the operation mode is the sleep mode, a wakeup signal is output from the transceiver. An operation mode transition means for returning the operation mode to the normal mode;
A node characterized by comprising:

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