JPS6322627B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a shotgun barrier type field effect transistor used in a high frequency circuit.

Figure 1 a to i are conventional shotgun barrier field effect transistors (hereinafter abbreviated as SBFET).
FIG. 2 is a cross-sectional view showing main steps of an example of a manufacturing method. First, as shown in Figure 1a, semi-insulating GaAs
On a semiconductor substrate having a substrate 1 and an active layer 2 made of n-type GaAs, as shown in FIG. remove,
As shown in FIG. 3c, metal for forming the source electrode 3 and drain electrode 5 is deposited. Subsequently, when the photoresist film 6 is removed, the metal layer thereon is removed, and a source electrode 3 and a drain electrode 5 are formed as shown in FIG. Next, as shown in figure e, the photoresist film 6 is covered only in the areas necessary for the operation of the SBFET, other unnecessary operating layers are etched, and the photoresist film 6 is removed, resulting in the structure shown in figure f. . Furthermore, as in the case of the source/drain, as shown in FIG. By depositing the photoresist film and removing the photoresist film, an SBFET with the structure shown in Figure i is completed.

Conventional products manufactured using the above manufacturing method
The SBFET has a drawback that the saturation drain current Idss of the SBFET varies greatly due to variations in the thickness and impurity concentration of the n-type active layer 2 of the semiconductor substrate. It is well known that fluctuations in Idss have a significant impact on SBFET performance, and controlling Idss to a predetermined value is extremely important for improving SBFET productivity. In conventional manufacturing methods, there was no easy way to set Idss to a predetermined value.

This invention has been made in view of the above points, and involves forming a plurality of n-type active layer portions having different thicknesses by etching in locations other than where an SBFET pattern is to be formed on a semiconductor substrate, and each By forming a monitor pattern electrode on the surface of an n-type active layer with a thickness of , and comparing the current flowing between the monitor pattern electrodes with the etching time of the active layer,
The present invention provides a method for determining the etching time of an n-type active layer that provides a predetermined saturation current. An embodiment of the method of this invention will be described below with reference to the drawings.

FIG. 2 is a sectional view showing the process of an SBFET which is an embodiment of the present invention. Using a semiconductor substrate having an n-type active layer formed thicker than the thickness that provides a predetermined Idss, a plurality of active layer parts with different thicknesses are formed by selective etching, and the source electrode 3 and drain electrode 5 are formed. At the same time, monitoring electrodes 7 are formed on the surface of the active layer of each thickness. Next, we measured the current flowing between each monitoring electrode and created a characteristic diagram showing the amount of etching of the active layer over time, as shown in Figure 3. Derive the etching time te that gives the inter-monitor current Idss ₀ as obtained. Once te is known, the steps up to the gate electrode formation shown in FIG. 4 are carried out in the same manner as in the conventional method. Here, as shown in FIG. 5, the active layer portion where the gate electrode is to be formed is etched for a period of time te to form a recess, and then the gate electrode 4 is formed in the same manner as in the conventional method, resulting in the structure shown in FIG. SBFET is completed.

In the SBFET manufactured as described above, the n-type active layer is formed to have a predetermined thickness determined from the current flowing through the monitor electrode 7. As a result, it becomes possible to suppress variations in Idss, which was difficult with conventional methods, and it becomes possible to improve the productivity of SBFETs.

As described above, the SBFET manufacturing method according to the present invention has the effect of easily improving the productivity of SBFETs.

[Brief explanation of the drawing]

Figures 1 a to i are cross-sectional views showing the conventional SBFET manufacturing method in the order of steps, and Figure 2 is a cross-sectional view of the method according to the present invention.
3 is a characteristic diagram of the embodiment of the present invention, and FIGS. 4, 5, and 6 are sectional views showing the continuation of the process of the present invention. It is. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n
form operation layer, 3 is a source electrode, 4 is a gate electrode, 5
6 is a drain electrode, 6 is a photoresist film, and 7 is a monitoring electrode. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A step of locally reducing the thickness of an active layer formed on a semiconductor substrate to form a plurality of active layer regions with different thicknesses, from electrodes facing each other on the active layer of each thickness. forming a monitor pattern electrode, and measuring the current flowing between the monitor pattern electrodes for each active layer thickness; the etching time and the current flowing between the monitor pattern electrodes when forming an active layer region of each thickness; A shot barrier type electric field characterized in that it includes the steps of: deriving an etching time such that a desired saturated drain current can be obtained from the relationship; and etching a portion of the active layer where a gate electrode is to be formed for the determined etching time. Method of manufacturing effect transistors.