JPS5895869A - Manufacture of schottky barrier field effect transistor - Google Patents
Manufacture of schottky barrier field effect transistorInfo
- Publication number
- JPS5895869A JPS5895869A JP19470981A JP19470981A JPS5895869A JP S5895869 A JPS5895869 A JP S5895869A JP 19470981 A JP19470981 A JP 19470981A JP 19470981 A JP19470981 A JP 19470981A JP S5895869 A JPS5895869 A JP S5895869A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- active layer
- thicknesses
- current
- monitoring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 230000005669 field effect Effects 0.000 title claims description 4
- 230000004888 barrier function Effects 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 abstract description 7
- 238000012544 monitoring process Methods 0.000 abstract description 7
- 229920006395 saturated elastomer Polymers 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 102000001690 Factor VIII Human genes 0.000 description 1
- 108010054218 Factor VIII Proteins 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、高周波ｕ路に用いるショットキバリア形紙
界効果トランジスタの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a Schottky barrier type paper field effect transistor used in a high frequency U-path.
第１ 図（ａ）〜（１）は従来のショットキバリア形電
界効果トランジスタ（以下、８ＢＦＥＴと略称する）の
製造方法の一例の主要工程を示、す断面図である。FIGS. 1(a) to 1(1) are cross-sectional views showing the main steps of an example of a method for manufacturing a conventional Schottky barrier field effect transistor (hereinafter abbreviated as 8BFET).
ます、第１−（ａ）に示すように半絶縁性ＧａＡ３基板
（１）とｎ形のＧａＡｓから成る動作層（２）を有する
半導体基板上に、同図（ｂｌに示すようにソース−極（
３）およびドレイン電極（５）を形成すべき部分のフォ
トレジスト膜（６）を写真製版技術によって除去し、同
図（ｃｌに示すようにソースｈ ｆＩｉ（３）およびド
レイン゛ｍ １ｄＪＩ （５）を形成するための金属を
蒸着する。続いて、フォトレジスト膜（６）を除去する
とその上の金一層が除去されて、同図（ｄ）に示すよう
にソース１１ 極（３）とドレイン電極（５）が形成さ
れる。次に、同図（ｅｌに示すように５ＢＦＥＴの動作
に必要な部分のみフォトレジスト膜（６）を覆い、他の
不要動作層をエツチングし、フォトレジスト膜（６）を
除去すｎは同図（ｆ）に示すようになる。さらに、同図
（−に示すようにソース・ドレインの場合と同様に、ゲ
ートｖＩＬ極を形成すべき部分のフォトレジスト膜（６
）を除去し、−囚（旬に示すようにゲート＆ 極（４）
を形成するための金属を蒸暑し、フォトレジスト膜を除
去すれは、同図（１）に小すような構造の８ＢＦ１！ｉ
Ｔが完成する。First, as shown in 1-(a), a source-electrode is placed on a semiconductor substrate having a semi-insulating GaA3 substrate (1) and an active layer (2) made of n-type GaAs, as shown in the same figure (bl). (
3) and the photoresist film (6) where the drain electrode (5) is to be formed are removed by photolithography, and the source h fIi (3) and drain electrode (5) are removed as shown in the same figure (cl). Then, when the photoresist film (6) is removed, the gold layer on it is removed, and the source 11 electrode (3) and the drain electrode are removed as shown in FIG. (5) is formed.Next, as shown in the same figure (el), only the portion necessary for the operation of the 5BFET is covered with the photoresist film (6), other unnecessary operating layers are etched, and the photoresist film (6) is etched. ) is removed as shown in figure (f).Furthermore, as shown in figure (-), as in the case of the source/drain, the photoresist film (6
), remove the -prisoner (gate & pole (4) as shown in Shun)
The process of heating the metal and removing the photoresist film to form the 8BF1! i
T is completed.
以上の製造方法によって製作された従来の５ＥＰＴＩ’
では、半導体基板のｎ形動作層（２）の厚みと不純ｉ＃
１度のばらつきによって、８ＢＦＥＴの飽和ドレイン電
流Ｉ（１８１１が大きくはらつく欠点を有していた。Conventional 5EPTI' manufactured by the above manufacturing method
Now, the thickness of the n-type active layer (2) of the semiconductor substrate and the impurity i#
It had a drawback that the saturation drain current I (1811) of the 8BFET fluctuated greatly due to a one-degree variation.
工ａＳＳの変動は、８ＢＦＥＴの性能に東大な影曽を及
ぼす拳はよく知らｎており、工ａＳＳを所定値に制仰す
る事は８ＢＩＰＰＴの生産性を向上させるためには非常
に電装な事柄であったが、従来の製造方法では１ｄ６８
を所定値に設定する簡単な方法がなかった。It is well known that fluctuations in ΔSS have a huge impact on the performance of 8BFETs, and controlling ΔSS to a predetermined value is a very important electrical component in order to improve the productivity of 8BIPPT. However, in the conventional manufacturing method, 1d68
There was no easy way to set it to a predetermined value.
この発明は上記の点に鏝みてなされたものであシ、半導
体基板上のＳＢＦ’ｌｌ！Ｔパターンを形成すべき以外
の場所にエツチング等によって複数個の異なる季みを有
するｎ形動作層部分を形成し、それぞれの牟みのｎ形動
作層の表向にモニタパターン電極を形成し、モニタパタ
ーン電極間を流れる電流を創作層の岸みと対照する１＃
によシ、所定飽和篭° 流が得られるｎ形動作層の厚み
を決定する方法を提供するものである。以下、図に従っ
て、この発明方法の一実施例を説明する。This invention was made in consideration of the above points, and is based on SBF'll on a semiconductor substrate! Forming a plurality of n-type active layer portions having different seasons by etching or the like in locations other than where the T-pattern should be formed, forming a monitor pattern electrode on the surface of each square n-type active layer, Contrast the current flowing between the monitor pattern electrodes with the shore of the creative layer 1#
Additionally, a method is provided for determining the thickness of an n-type operating layer that provides a predetermined saturated cage flow. An embodiment of the method of the present invention will be described below with reference to the drawings.
第２図はこの発明の一実施例である８ＢＦ１１１ｉＴの
工程を示す断面図である。所定のＩｄｅｓが得らｎる厚
み以上に厚く形成さ口たｎ形動作層を有する半導体基板
を用い、選択エツチングにより、複数の異なる厚みの動
作層部分を形成し、ソース亀ｍ（３）。FIG. 2 is a sectional view showing the process of 8BF111iT, which is an embodiment of the present invention. Using a semiconductor substrate having an open n-type active layer formed to be thicker than the thickness n that provides a predetermined Ides, a plurality of active layer portions having different thicknesses are formed by selective etching, and the source layer m(3) is formed.
ドレイン電極（５）の形成と同時に、それぞれの厚みの
動作層の表面にモニタ用電極（７）を形成する。次に、
各モニタ用電極間を流ｎる電流を測定し、第８因に示す
ように、動作層のエツチング量を時間で表した特性図を
作成し、ゲート電極を形成した場合に所定の工ａＳＳが
得らｎるようなモニタ間電流工ａＳＳ＠を与えるエツチ
ング時間ｔｏを導出する。Simultaneously with the formation of the drain electrode (5), a monitoring electrode (7) is formed on the surface of the active layer of each thickness. next,
The current flowing between each monitoring electrode was measured, and as shown in factor 8, a characteristic diagram showing the amount of etching of the active layer in terms of time was created. Derive the etching time to which gives the monitor-to-monitor current aSS@ such that n is obtained.
ｔｅが判明すれは、従来と同様の方法で第４図に示した
ゲート電極形成前までの工程を実施する。Once te is known, the steps up to the gate electrode formation shown in FIG. 4 are carried out in the same manner as in the conventional method.
ここで、第５図に示すようにゲート電極を形成すべき動
作層部分をｔｏの時間のみエツチングし７、凹部を形成
した後、従来と同様にゲート電極（４）を形成し第６１
に示す構造の８ＢＦ’ＦｉＴが完成する。Here, as shown in FIG. 5, the active layer portion where the gate electrode is to be formed is etched for a period of time 7 to form a recessed portion, and then the gate electrode (4) is formed in the same manner as in the prior art.
8BF'FiT having the structure shown in is completed.
上記のように製造された８ＢＦ’ＢＴは、ｎ形動作層の
与みがモニタ亀＆（７）を流れる電流から決定された所
定率みに形成されている。この結果、従来方法では困難
であったｌ１ａｓのばらつきの抑制が可能となり、８Ｂ
ＦＥＴの生産性の向上が図ｎる事となる。In the 8BF'BT manufactured as described above, the n-type active layer is formed at a predetermined rate determined from the current flowing through the monitor turtle & (7). As a result, it is possible to suppress variations in l1as, which was difficult with conventional methods, and 8B
This will greatly improve the productivity of FETs.
以上述べたように、この発明に係る８ＢＦ’ＥＴの製造
方法によｎは、簡単に８ＢＦＥＴの生産性の向上が可能
となる効果がある。As described above, the method for manufacturing 8BF'ET according to the present invention has the effect of easily improving the productivity of 8BFET.
第１図（ａ）〜（１）は従来の８ＢＦｊＥＴの製造方法
を示す工程順の断面図、第２図はこの発明に係るＥＩＢ
ＦＢＴの製造方法の一実施例を示す工程の断面図、第８
図はこの発明による実施例の特性図、第４図、第５１、
第６図はこの発明の工程の続きを示す断面図である。
図において、（１）は半絶縁性ＧａＡ３基板、（２）は
ｎ形動作層、（３）はり曲玉電極、（４）はゲート電極
、（５）はドレイン電極、（６）はフォトレジストＩｉ
ｋ、（７）はモニタ用ｗＩＬ極である。
なお、図中、同一符号は同一または相当部分を示す。
代理人 葛 野 信 −FIGS. 1(a) to (1) are cross-sectional views showing the process order of the conventional 8BFjET manufacturing method, and FIG. 2 is an EIB according to the present invention.
Cross-sectional view of a process showing an example of an FBT manufacturing method, No. 8
The figures are characteristic diagrams of embodiments according to the present invention, Fig. 4, Fig. 51,
FIG. 6 is a sectional view showing the continuation of the process of this invention. In the figure, (1) is a semi-insulating GaA3 substrate, (2) is an n-type active layer, (3) is a curved ball electrode, (4) is a gate electrode, (5) is a drain electrode, and (6) is a photoresist. Ii
k, (7) is a monitoring wIL pole. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Shin Kuzuno −
Claims (1)
し、複数の異なる厚みの動作層領域を形成する工程。各
々の厚みの動作１−上にモニタパターン電極を形成し、
このモニタパターン電極間を流れる電流を測定し、動作
層厚みとモニタパターン電極間を流れる電流の関係から
、所望値の電流に対する動作層厚みを導出する工程。ゲ
ート電極を形成すべき動作層部分を導出さ口た動作層厚
みになるまで薄くする工程を含むことを特徴とするショ
ツ”トキパリア形電界効果トランジスタのｈａ方法。A process of locally reducing the thickness of an active layer formed on a semiconductor substrate to form a plurality of active layer regions with different thicknesses. Form a monitor pattern electrode on operation 1- of each thickness,
A step of measuring the current flowing between the monitor pattern electrodes and deriving the active layer thickness for a desired value of current from the relationship between the active layer thickness and the current flowing between the monitor pattern electrodes. 1. A method for producing a short-circuit field effect transistor comprising the step of thinning an active layer portion in which a gate electrode is to be formed to a thickness of the active layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19470981A JPS5895869A (en) | 1981-11-30 | 1981-11-30 | Manufacture of schottky barrier field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19470981A JPS5895869A (en) | 1981-11-30 | 1981-11-30 | Manufacture of schottky barrier field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5895869A true JPS5895869A (en) | 1983-06-07 |
| JPS6322627B2 JPS6322627B2 (en) | 1988-05-12 |
Family
ID=16328943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19470981A Granted JPS5895869A (en) | 1981-11-30 | 1981-11-30 | Manufacture of schottky barrier field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5895869A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63184368A (en) * | 1986-08-26 | 1988-07-29 | Agency Of Ind Science & Technol | Manufacture of compound semiconductor fet |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984377A (en) * | 1972-12-18 | 1974-08-13 | ||
| JPS5279881A (en) * | 1975-12-26 | 1977-07-05 | Nec Corp | Production of gaas schottky barrier gate type field effect transistor |
-
1981
- 1981-11-30 JP JP19470981A patent/JPS5895869A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984377A (en) * | 1972-12-18 | 1974-08-13 | ||
| JPS5279881A (en) * | 1975-12-26 | 1977-07-05 | Nec Corp | Production of gaas schottky barrier gate type field effect transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63184368A (en) * | 1986-08-26 | 1988-07-29 | Agency Of Ind Science & Technol | Manufacture of compound semiconductor fet |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6322627B2 (en) | 1988-05-12 |
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