JP3582948B2 - Method for setting etching conditions and method for manufacturing field effect transistor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for setting an etching condition and a method for manufacturing a field effect transistor (hereinafter, sometimes referred to as an FET) having a recess structure.
[0002]
[Prior art]
Some FETs have a so-called recess structure in which a gate electrode is provided in a recess formed by dug a part of a substrate.
[0003]
As a conventional typical method for manufacturing an FET having a recess structure, there is a method described below (literature: "CY Chang, Francis Kai," GaAs High-Speed Devices ", pp. 327-328, 1994, Wiley Inter. Science)).
[0004]
(A) First, silicon (Si) as an n-type impurity is ion-implanted into a predetermined region of a semi-insulating GaAs substrate, and then heat treatment is performed to form an island-shaped active region made of n-type GaAs. A semiconductor substrate having a semi-insulating GaAs region surrounding the periphery of the n-type GaAs active region is formed.
[0005]
(B) Thereafter, a source electrode and a drain electrode are formed at predetermined intervals on the n-type GaAs active region.
[0006]
(C) After that, at least a first opening for forming a gate electrode having a cross section of an overhang shape on the semiconductor substrate and a second opening for forming an electrode wiring connected to the first opening are formed. A resist pattern having an opening is formed so as to cover the source and drain electrodes and the first opening is located between the source and drain electrodes.
[0007]
(D) Then, using the resist pattern as a mask, the portion of the semiconductor substrate exposed from each opening is etched using an etching solution (etchant) composed of a mixed solution of phosphoric acid, hydrogen peroxide and water. To form a recess.
[0008]
(E) Finally, after a gate electrode forming material is vacuum-deposited, the resist pattern is removed to form a gate electrode and an electrode wiring in the recess.
[0009]
[Problems to be solved by the invention]
However, when a plurality of FETs are manufactured by the above-described conventional method, if the dimensions of the n-type GaAs active region and the dimensions of the resist pattern are different, the threshold voltage is different for each manufactured FET, and the threshold voltage of each FET is different. The threshold voltage could not be set to the desired value.
[0010]
The inventor of the present application has conducted various studies on the cause and found the following phenomena (1) and (2). FIG. 12 and FIG. 13 are diagrams for explaining these phenomena. FIGS. 12A and 12B show a state immediately before the step (d) in the above-mentioned conventional method, that is, an island-shaped n-type GaAs active region 10 and a half surrounding the periphery of the n-type GaAs active region 10. A first opening 24 for forming a gate electrode and a second opening 26 for forming an electrode wiring connected to the first opening 24 are formed on a semiconductor substrate 14 having an insulating GaAs region 12 thereon. 2 shows a state in which a resist pattern 22 having an opening 20 formed is formed. FIG. 12A is a plan view, and FIG. 12B is a cross-sectional view showing a cut surface taken along a line II in FIG. 12A. FIG. 13 shows a state in which the portion of the semiconductor substrate 14 exposed from the opening 20 is etched using an etchant composed of a mixed solution of phosphoric acid, hydrogen peroxide and water using the above-described resist pattern 22 as a mask. In the distribution of the etching depth, the horizontal axis indicates the position along the line II in FIG. 12A, and the vertical axis indicates the etching depth. The positions a to c shown on the horizontal axis in FIG. 13 are the positions a to c in FIG.
[0011]
(1) n type GaAs active region etching rate (R _n ), The etching rate (R) of the semi-insulating GaAs region whose distance from the boundary between the n-type GaAs active region and the semi-insulating GaAs region is within D _i ) Is larger.
[0012]
(2) Etching rate R _i Is the surface area (S1) of the n-type GaAs active region (hereinafter, referred to as a first region) exposed from the first opening and the n-type GaAs active region from the semi-insulating region exposed from the second opening. The larger the ratio S2 / S1 to the surface area (S2) of the region (hereinafter, referred to as a second region) whose distance from the boundary between the GaAs active region and the semi-insulating GaAs region is within D (hereinafter, referred to as a second region), is larger.
[0013]
Here, during the description of such phenomena (1) and (2), the etching rate (R _n 13) corresponds to the etching depth in the range of {circle around (1)} in FIG. 13, and the distance from the boundary between the n-type GaAs active region and the semi-insulating GaAs region is within D. Etching rate (R _i ) Corresponds to the etching depth in the range of (2) in FIG. The surface area (S1) of the first area is the surface area of the area indicated by S1 in FIG. 12A, and the surface area (S2) of the second area is indicated by S2 in FIG. The surface area of the area.
[0014]
Further, the inventor of the present application has conducted various studies on the causes of such phenomena (1) and (2), and found that a reaction based on the “principle of the voltaic battery” occurs at the time of etching. By taking into account that the electric resistance of the semi-insulating GaAs region is represented by a distributed constant (refer to the document: “Heinz K. Henisch,“ Semiconductor contacts ”, pp. 16-17, 1984, Clarendon Press), the following is considered. It can be explained as follows. "Principle of Volta battery" means that when two electrodes (positive electrode and negative electrode) connected by a conductive wire are immersed in an electrolytic solution, one of the electrodes (negative electrode) is dissolved in the electrolytic solution to generate electrons. Is transferred to the other electrode (positive electrode), and the electrons reduce positive ions in the electrolyte. Further, the fact that the electric resistance of the semi-insulating GaAs region is represented by a distributed constant means that the electric resistance of the semi-insulating GaAs region is, for example, a network using a large number of resistors, as shown in FIG. It is expressed in a shape.
[0015]
During etching, the n-type GaAs active region functions as a positive electrode, the semi-insulating GaAs region functions as a negative electrode, and the etchant functions as an electrolyte. For this reason, at the time of etching, the semi-insulating GaAs region dissolves in the etchant, and the generated electrons move inside the semi-insulating GaAs region to the n-type GaAs active region. At this time, since the electric resistance of the semi-insulating GaAs region is represented by a distributed constant, the larger the distance from the boundary between the n-type GaAs active region and the semi-insulating GaAs region, the more the semi-insulating GaAs region becomes an etchant. It is difficult for electrons generated by dissolving to the inside of the semi-insulating GaAs region to move to the n-type GaAs active region. For this reason, the dissolution of the semi-insulating GaAs region into the etchant is more likely to occur closer to the boundary between the n-type GaAs active region and the semi-insulating GaAs region, and from the boundary between the n-type GaAs active region and the semi-insulating GaAs region. The semi-insulating GaAs region whose distance is within D effectively contributes to the reaction based on the "Volta cell principle". From this, the etching rate of the n-type GaAs active region (R _n ), The etching rate (R) of the semi-insulating GaAs region whose distance from the boundary between the n-type GaAs active region and the semi-insulating GaAs region is within D _i ) Is larger (the phenomenon (1) described above). Further, the dissolution of the semi-insulating GaAs region in the etchant increases as the amount of electrons traveling inside the semi-insulating GaAs region and moving to the n-type GaAs active region increases, that is, as the surface area (S2) of the second region increases. Easy to happen. From this, the etching rate R _i Is larger as the ratio S2 / S1 between the surface area (S1) of the first region and the surface area (S2) of the second region is larger (the phenomenon (2) described above).
[0016]
As described above, when a plurality of FETs are manufactured by the conventional method, if the dimensions of the n-type GaAs active region, the dimensions of the resist pattern, and the like are different, the threshold voltage differs for each manufactured FET. Although the threshold voltage could not be set to a desired value, this is due to the occurrence of the phenomena (1) and (2) described above, and can be explained as follows.
[0017]
The etching rate of the n-type GaAs active region (R _n ), The etching rate (R) of the semi-insulating GaAs region whose distance from the boundary between the n-type GaAs active region and the semi-insulating GaAs region is within D _i ) Is larger (phenomenon (1) above), so that the etching rate of the n-type GaAs active region located near the boundary between the n-type GaAs active region and the semi-insulating GaAs region also increases accordingly. This can be understood from the fact that the etching depth in the range (3) in FIG. 1C is larger than the etching depth in the range (1) in FIG. 1 (C). And the etching rate R _i Is larger as the ratio S2 / S1 between the surface area (S1) of the first region and the surface area (S2) of the second region is larger (phenomenon (2) described above). Similarly, the etching rate of the n-type GaAs active region located near the boundary with the GaAs region also increases as the ratio S2 / S1 between the surface area (S1) of the first region and the surface area (S2) of the second region increases. . For this reason, if the dimensions of the n-type GaAs active region, the dimensions of the resist pattern, and the like are different, the etching profile at the position along the II line in FIG. From this, if the dimensions of the n-type GaAs active region and the dimensions of the resist pattern are different, the threshold voltage differs for each manufactured FET, and the threshold voltage of each FET can be set to a desired value. could not.
[0018]
Therefore, on the premise that the above-described phenomena (1) and (2) occur, when manufacturing a plurality of FETs, the etching conditions for setting the threshold voltage of each FET to a desired value. It has been desired to develop a method of manufacturing an FET having a recessed structure by a method of setting the thickness and the etching conditions set by such a method.
[0019]
[Means for Solving the Problems]
The method for setting etching conditions and the method for manufacturing an FET having a recess structure according to the present invention are based on the premise that the above-described phenomena (1) and (2) occur.
[0020]
According to the first method for setting etching conditions of the present invention, a semiconductor substrate having an island-shaped active region formed by doping impurities and a semi-insulating semiconductor region surrounding the periphery of the active region is provided on a semiconductor substrate. Located on the active area Exposing only the active area A first opening for forming a gate electrode; , Connected to the first opening and located on the semi-insulating semiconductor region Exposing only the semi-insulating semiconductor region portion Forming a resist pattern having at least an opening composed of a second opening for forming an electrode wiring, and then forming a recess by wet etching the portion of the semiconductor substrate exposed from the opening using the resist pattern as a mask; In setting the etching conditions for the wet etching, the surface area of the active region exposed from the first opening is defined as S1, and the distance from the boundary between the active region and the semi-insulating semiconductor region is D. And dividing the semi-insulating semiconductor region exposed from the second opening into a second region and a third region from the boundary side, and when the surface area of the second region is S2, the value of D is changed. The value of S2 / S1 is determined for each combination of the value of D and the value of S2 by changing the value of S2 for each value of. Both, the boundary between the active region and the semi-insulating semiconductor region Pinch The value of S2 / S1 at which the etching rate in the active region and the semi-insulating semiconductor region becomes substantially uniform is set as the etching condition.
[0021]
The value of D is such a value that the semi-insulating semiconductor region whose distance from the boundary between the active region and the semi-insulating semiconductor region is within D effectively contributes to the reaction based on the principle of the "Volta battery". It is desirable to determine such a value, but actually, it is not easy to determine such a value. Therefore, according to the first method of setting the etching conditions of the present invention, first, the value of D is determined to be an appropriate value, and the value of S2 is changed at the value of D to thereby combine the value of D with the value of S2. The value of S2 / S1 is obtained for each. Then, by changing the value of D from the initial value to a slightly different value and changing the value of S2 at the new value of D, the value of S2 / S1 for each combination of the value of D and the value of S2 Ask for. Thereafter, the same operation is repeated. The value of S1 changes depending on the shape of the first opening, and the value of S2 changes depending on the shape of the second opening. However, since the value of S1 is predetermined by design, the value of S2 is changed. Thus, the value of S2 / S1 is determined for each combination of the value of D and the value of S2. Then, from among the plurality of S2 / S1 values obtained, at least the etching rate in the active region and the semi-insulating semiconductor region near the boundary between the active region and the semi-insulating semiconductor region. Is set as the etching condition so that S2 / S1 becomes substantially uniform.
[0022]
For example, as the value of S2 / S1 is smaller, the etching rate in the active region and the semi-insulating semiconductor region around the boundary between the active region and the semi-insulating semiconductor region becomes substantially uniform. . This is because the etching rate of the semi-insulating semiconductor region whose distance from the boundary between the active region and the semi-insulating semiconductor region is within D is larger as the ratio S2 / S1 between S1 and S2 is larger. This is because the etching rate of the active region located near the boundary between the active region and the semi-insulating semiconductor region also increases as the ratio S2 / S1 between S1 and S2 increases.
[0023]
According to the first method for fabricating a FET of the present invention, an island-shaped active region formed by doping impurities and a semi-insulating semiconductor region surrounding the active region are formed on a semiconductor substrate. A resist having an opening comprising at least a first opening for forming a gate electrode located on the active region and a second opening for forming an electrode wiring connected to the first opening and located on the semi-insulating semiconductor region; A step of forming a pattern, a step of forming a recess by wet etching a portion of the semiconductor substrate exposed from the opening using the resist pattern as a mask, and a step of forming a gate electrode and an electrode wiring in the recess. A method of manufacturing an FET having a recess structure, wherein wet etching is performed under etching conditions set by the first method for setting etching conditions. That.
[0024]
When a recess is formed by wet etching under such etching conditions, the etching rate in the vicinity of the active region and the semi-insulating semiconductor region around the boundary between the active region and the semi-insulating semiconductor region is substantially reduced. It becomes uniform uniformly. Therefore, the etching profile is substantially flat over both the active region and the semi-insulating semiconductor region. That is, the etching depth is substantially uniform over the entire area exposed from the opening. Therefore, when a plurality of FETs are manufactured by the first manufacturing method of the FET according to the present invention, the threshold voltage of each manufactured FET is the same even if the size of the active region and the size of the resist pattern are different. . That is, the threshold voltage of each manufactured FET can be made the same.
[0025]
According to the second method of setting etching conditions of the present invention, a plurality of island-shaped active regions formed by doping impurities and a semi-insulating semiconductor region surrounding the periphery of the active region are provided at the upper part. A semiconductor substrate includes at least a first opening for forming a gate electrode located on an active region and a second opening for connecting to the first opening and forming an electrode wiring located on a semi-insulating semiconductor region. Forming a resist pattern having a plurality of openings, and thereafter, using the resist pattern as a mask, wet etching the portion of the semiconductor substrate exposed from each of the openings to form a recess, and the etching conditions of the wet etching. Is set, S1 is the surface area of the active region exposed from the first opening, and D is the distance from the boundary between the active region and the semi-insulating semiconductor region. The semi-insulating semiconductor region exposed from the second opening is fractionated into second and third regions from the boundary between the active region and the semi-insulating semiconductor region, and the surface area of the second region is defined as S2. Then, by changing the value of D and changing the value of S2 for each value of D, the value of S2 / S1 for each combination of the value of D and the value of S2 is obtained, and a plurality of obtained S2 / S1 values are obtained. The value of S2 / S1 at which the etching profile in the active region is substantially the same for each active region is set as the etching condition from among the values of S1.
[0026]
In the second method of setting the etching conditions according to the present invention, the value of S2 / S1 for each combination of the value of D and the value of S2 is determined by the same method as the method of setting the first etching condition. Then, from among a plurality of obtained S2 / S1 values, the value of S2 / S1 at which the etching profile in the active region portion becomes substantially the same for each active region is set as the etching condition.
[0027]
For example, if the values of S2 / S1 for each opening are all the same, it is considered that the etching profile in the active region is substantially the same for each active region. This is because the degree of occurrence of the reaction based on the “Volta battery principle” is considered to be the same for each opening.
[0028]
According to the second method of manufacturing a FET of the present invention, a semiconductor having a plurality of island-shaped active regions formed by doping impurities and a semi-insulating semiconductor region surrounding the periphery of the active region is provided at the top. On the substrate, at least an opening comprising a first opening for forming a gate electrode located on the active region and a second opening for connecting to the first opening and forming an electrode wiring located on the semi-insulating semiconductor region. Forming a resist pattern having a plurality of, a step of forming a recess by wet etching a portion of the semiconductor substrate exposed from each of the openings using the resist pattern as a mask, and forming the gate electrode and the electrode wiring in the recess. Forming a plurality of FETs having a recess structure, wherein the wet etching is performed by a method of setting a second etching condition. And performing at grayed conditions.
[0029]
When a recess is formed by wet etching under such etching conditions, the etching profile in the active region portion becomes substantially the same for each active region. Therefore, when a plurality of FETs are manufactured by the second method for manufacturing FETs of the present invention, the threshold voltage of each manufactured FET becomes the same even if the size of the active region, the size of the resist pattern, and the like are different. . That is, the threshold voltage of each manufactured FET can be made the same.
[0030]
According to the third method of setting etching conditions of the present invention, a plurality of island-shaped active regions formed by doping impurities and a semi-insulating semiconductor region surrounding the periphery of the active region are provided at the upper part. A semiconductor substrate includes at least a first opening for forming a gate electrode located on an active region and a second opening for connecting to the first opening and forming an electrode wiring located on a semi-insulating semiconductor region. Forming a resist pattern having a plurality of openings, and thereafter, using the resist pattern as a mask, wet etching the portion of the semiconductor substrate exposed from each of the openings to form a recess, and the etching conditions of the wet etching. Is set, S1 is the surface area of the active region exposed from the first opening, and D is the distance from the boundary between the active region and the semi-insulating semiconductor region. The semi-insulating semiconductor region exposed from the second opening is fractionated into second and third regions from the boundary between the active region and the semi-insulating semiconductor region, and the surface area of the second region is defined as S2. Then, by changing the value of D and changing the value of S2 for each value of D, the value of S2 / S1 for each combination of the value of D and the value of S2 is obtained, and a plurality of obtained S2 / S1 values are obtained. The value of S2 / S1, in which the etching profile in the active region portion is substantially different for each active region, is set as the etching condition from among the values of S1.
[0031]
In the third method of setting etching conditions according to the present invention, the value of S2 / S1 for each combination of the value of D and the value of S2 is determined by the same method as the method of setting the first etching condition. Then, from among the plurality of obtained S2 / S1 values, the value of S2 / S1 at which the etching profile in the active region is substantially different for each active region is set as the etching condition.
[0032]
For example, when the value of S2 / S1 is different for each opening, it is considered that the etching profile in the active region portion is substantially different for each active region. This is because the degree of occurrence of the reaction based on the “principle of the voltaic battery” is considered to be different for each opening.
[0033]
According to the third method of manufacturing a FET of the present invention, a semiconductor having a plurality of island-like active regions formed by doping impurities and a semi-insulating semiconductor region surrounding the periphery of the active region is provided at the top. On the substrate, at least an opening comprising a first opening for forming a gate electrode located on the active region and a second opening for connecting to the first opening and forming an electrode wiring located on the semi-insulating semiconductor region. Forming a resist pattern having a plurality of, a step of forming a recess by wet etching a portion of the semiconductor substrate exposed from each of the openings using the resist pattern as a mask, and forming the gate electrode and the electrode wiring in the recess. Forming a plurality of FETs having a recess structure, wherein the wet etching is performed by a method of setting a third etching condition. And performing at grayed conditions.
[0034]
When a recess is formed by wet etching under such etching conditions, an etching profile in an active region portion is substantially different for each active region. Therefore, when a plurality of FETs are manufactured by the third method of manufacturing an FET according to the present invention, the threshold voltages of the manufactured FETs are different. That is, the threshold voltage of each manufactured FET can be changed.
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the drawings used in the following description, each component merely schematically shows its shape, size, and positional relationship so that the present invention can be understood. Further, in each of the drawings used for the description, the same components are denoted by the same reference numerals, and the overlapping description may be omitted. Also, in the plan view, certain components are not cross-sections but are highlighted with hatching patterns. In addition, numerical conditions such as a used material, a forming method, and a heat treatment temperature described in the following description are merely preferable examples of the embodiment of the present invention. Therefore, it should be understood that the present invention is not limited to the embodiments described below.
[0038]
1. First embodiment
FIG. 1 to FIG. 5 are manufacturing process diagrams of an FET having a recess structure, which are provided for describing this embodiment. In each figure, (A) is a plan view, and (B) is a cross-sectional view showing a cut surface taken along line II in (A). Hereinafter, a method of manufacturing an FET having a recess structure will be described with reference to FIGS.
[0039]
First, silicon (Si) as an n-type impurity is ion-implanted into a predetermined region of a semi-insulating GaAs substrate, and then heat treatment is performed at about 800 ° C. to form an island-shaped active region 10 made of n-type GaAs. Then, a semiconductor substrate 14 having a semi-insulating GaAs region 12 surrounding the periphery of the n-type GaAs active region 10 is formed (FIGS. 1A and 1B). The portion of the semi-insulating GaAs substrate into which silicon (Si) has been ion-implanted is the n-type GaAs active region 10, and the portion of the semi-insulating GaAs substrate without ion-implanting is the semi-insulating GaAs region 12.
[0040]
Next, a source electrode 16 and a drain electrode 18 made of gold (Au) or a gold-germanium (Au-Ge) alloy are formed at predetermined intervals on the n-type GaAs active region 10 by using a lift-off method (FIG. 1). 2 (A) and (B)).
[0041]
Next, a resist pattern 22 having an opening 20 having a cross section of an overhang shape is formed on the semiconductor substrate 14 so as to cover the source electrode 16 and the drain electrode 18 (FIGS. 3A and 3B). The opening 20 comprises first, second and third openings 24, 26 and 28. The first opening 24 is for forming a gate electrode, the second opening 26 is for forming an electrode wiring, and the third opening 28 is such that the length of the first opening 24 in the gate width direction is n. The GaAs active region 10 is provided to extend from the first opening 24 so as to be equal to the length in the gate width direction of the GaAs active region 10. In addition, the second opening 26 is composed of a lead wiring forming opening 30 and a gate electrode pad forming opening 32 in order from the first opening 24 side. The first opening 24 is formed so as to be located on the n-type GaAs active region 10 between the source electrode 16 and the drain electrode 18, and the second opening 26 is located on the semi-insulating GaAs region 12. It is formed as follows. The openings 30, 24, and 28 are continuously formed at equal widths in the gate length direction and are formed as elongated rectangles as a whole, and the openings 32 are formed as rectangles wider in the gate length direction.
[0042]
Length L of first opening 24 in the gate length direction ₁ Is, for example, 0.1 to 0.5 μm, and the length W in the gate width direction is ₁ Is, for example, 10 to 100 μm. Also, the length L of the lead-out wiring forming opening 30 in the gate length direction is set. ₂ Is, for example, 0.1 to 0.5 μm, and the length W in the gate width direction is ₂ Is, for example, 10 μm. The length L of the gate electrode pad forming opening 32 in the gate length direction ₃ Is, for example, 2 to 4 μm, and the length W in the gate width direction is ₃ Is, for example, 2 to 4 μm. However, the length L of the first opening 24 in the gate length direction ₁ And the length L in the gate length direction of the lead-out wiring forming opening 30 ₂ And the same size.
[0043]
In a later step, a gate electrode is formed in a portion of the recess exposed from the first opening 24, and a lead wire and a gate electrode pad are formed in a portion of the recess exposed from the second opening 26. An electrode wiring is formed.
[0044]
At this stage, the n-type GaAs active region 10 and the semi-insulating GaAs region 12 surrounding the periphery of the n-type GaAs active region 10 are formed on the semiconductor substrate 14 on the n-type GaAs active region 10. At least a first opening 24 for gate electrode formation located on the region 10 and a second opening 26 for electrode wiring formation connected to the first opening 24 and located on the semi-insulating GaAs region 12. A resist pattern 22 having an opening 20 is formed.
[0045]
Next, using the resist pattern 22 as a mask, the portion of the semiconductor substrate 14 exposed from each of the openings 24 to 28 is etched using an etchant composed of a mixture of phosphoric acid, hydrogen peroxide and water. Thus, a recess 34 is formed (FIGS. 4A and 4B).
[0046]
Finally, after aluminum (Al) as a gate electrode forming material is vacuum-deposited, the resist pattern 22 is removed to form a gate electrode 36 and an electrode wiring 38 made of aluminum (Al) in the recess 34 ( (FIG. 5 (A) and (B)). The gate electrode 36 is formed in the portion of the recess 34 exposed from the first opening 24, and the electrode wiring 38 is formed in the portion of the recess 34 exposed from the second opening 26. The electrode wiring 38 includes a lead wiring 40 and a gate electrode pad 42. As described above, the FET having the recess structure is manufactured.
[0047]
In this embodiment, the etching rate in the n-type GaAs active region 10 and the semi-insulating GaAs region 12 around the boundary 44 between the n-type GaAs active region 10 and the semi-insulating GaAs region 12 is reduced. The etching conditions for forming the recess 34 by wet etching are set so as to be uniform.
[0048]
More specifically, the semi-insulating GaAs region 12 whose distance from the boundary 44 between the n-type GaAs active region 10 and the semi-insulating GaAs region 12 is within D is effectively a reaction based on the principle of the "voltaic cell". The length W of the lead-out wiring forming opening 30 in the gate width direction. ₂ And W ₂ > D. For example, when the distance D is about 5 μm, the length W ₂ Is set to 10 μm.
[0049]
Thus, the length W in the gate width direction of the lead-out wiring forming opening 30 is obtained. ₂ And W ₂ > D, the surface area (S1) of the n-type GaAs active region 10 (first region) exposed from the first opening 24 and the semi-insulating surface exposed from the second opening 26 The ratio S2 / S1 of the surface area (S2) of the region (second region) in which the distance from the boundary 44 between the n-type GaAs active region 10 and the semi-insulating GaAs region 12 is within D in the conductive GaAs region 12 is Since the size becomes smaller, the etching rate in the n-type GaAs active region 10 and the semi-insulating GaAs region 12 around the boundary 44 between the n-type GaAs active region 10 and the semi-insulating GaAs region 12 is uniform. It is considered to be. Note that S2 / S1 becomes smaller because of L ₂ Is a very small value of 0.1 to 0.5 μm, so that D × L ₂ This is because the surface area (S2) of the second region represented by the following expression also has a small value.
[0050]
Further, in this embodiment, the etching is performed on the n-type GaAs active region 10 and the semi-insulating GaAs region 12 near the boundary 44 between the n-type GaAs active region 10 and the semi-insulating GaAs region 12. Since the etching conditions at the time of forming the recess 34 by wet etching are set so that the speed is uniform, the etching profile substantially covers both the n-type GaAs active region 10 and the semi-insulating GaAs region 12. Becomes flat. That is, the etching depth is substantially uniform over the entire area exposed from the opening 20. Therefore, when a plurality of FETs are manufactured by the method of this embodiment, the threshold voltage of each manufactured FET becomes the same even if the size of the n-type GaAs active region 10 and the size of the resist pattern 22 are different. . That is, the threshold voltage of each manufactured FET can be made the same.
[0051]
2. Second embodiment
FIG. 6 is a plan view showing a manufacturing process of two FETs having a recessed structure for explaining this embodiment, and shows the process steps shown in FIG. 3 in the first embodiment. That is, FIG. 6 shows a semiconductor substrate having two island-shaped n-type GaAs active regions 10a and 10b and a semi-insulating GaAs region surrounding the n-type GaAs active regions 10a and 10b on a semiconductor substrate. 2 shows a state in which a resist pattern 22 having two openings 20a and 20b is formed.
[0052]
In FIG. 6, reference numeral 24a denotes a first opening constituting one opening 20a, and reference numeral 24b denotes a first opening constituting the other opening 20b. Reference numeral 26a denotes a second opening that forms one opening 20a, and reference numeral 26b denotes a second opening that forms the other opening 20b. Reference numeral 28a denotes a third opening that forms one opening 20a, and reference numeral 28b denotes a third opening that forms the other opening 20b. Reference numeral 30a denotes an opening for forming a lead-out wiring forming one second opening 26a, and reference numeral 30b denotes an opening for forming a lead-out wiring forming the other second opening 26b. Reference numeral 32a denotes an opening for forming a gate electrode pad forming one second opening 26a, and reference numeral 32b denotes an opening for forming a gate electrode pad forming the other second opening 26b. Reference numerals 16a and 16b indicate source electrodes, and reference numerals 18a and 18b indicate drain electrodes.
[0053]
The first opening 20a constituting one opening 20a is formed so as to be located on the n-type GaAs active region 10a between the source electrode 16a and the drain electrode 18a, and the second opening 26a has a semi-insulating property. It is formed so as to be located on the GaAs region. Similarly, the first opening 20b forming the other opening 20b is formed so as to be located on the n-type GaAs active region 10b between the source electrode 16b and the drain electrode 18b, and the second opening 26b is formed. It is formed so as to be located on the semi-insulating GaAs region. The openings 24a and 28a are continuously formed at equal widths in the gate length direction and are formed as elongated rectangles as a whole. The opening 30a is formed as a middle width rectangle in the gate length direction, and the opening 32a is formed as a gate. It is formed as a rectangle that is wide in the longitudinal direction. The openings 30b, 24b, and 28b are continuously formed at equal widths in the gate length direction and are formed as elongated rectangles as a whole, and the openings 32a are formed as rectangles wider in the gate length direction.
[0054]
In this embodiment, two FETs are manufactured by a method similar to that of the first embodiment. However, the etching conditions for forming the recess by wet etching are set so that the etching profile in the n-type GaAs active region is substantially the same in the two n-type GaAs active regions 10a and 10b. ing.
[0055]
More specifically, the semi-insulating GaAs region whose distance from the boundary 44 between the n-type GaAs active region and the semi-insulating GaAs region is within D effectively contributes to the reaction based on the "Volta cell principle". In this case, the length in the gate length direction of the first opening 24a forming one opening 20a is L. _a1 And the length in the gate width direction is W _a1 And the length of the first opening 24b constituting the other opening 20b in the gate length direction is L _b1 And the length in the gate width direction is W _b1 And the length in the gate length direction of the lead-out wiring forming opening 30a forming one second opening 26a is L _a2 And the length in the gate width direction is W _a2 And the length in the gate length direction of the lead-out wiring forming opening 30b constituting the other second opening 26b is L _b2 And the length in the gate width direction is W _b2 And W _a2 > D and W _b2 > D, (L _a2 × D) / (L _a1 × W _a1 ) = (L _b2 × D) / (L _b1 × W _b1 ).
[0056]
Thus (L _a2 × D) / (L _a1 × W _a1 ) = (L _b2 × D) / (L _b1 × W _b1 ), The degree of occurrence of a reaction based on the “principle of the voltaic cell” is considered to be the same in the two openings 20a and 20b. Therefore, the etching profile in the n-type GaAs active region is It is considered that the n-type GaAs active regions 10a and 10b are substantially the same.
[0057]
In this embodiment, the recess is formed by wet etching so that the etching profile in the n-type GaAs active region is substantially the same in the two n-type GaAs active regions 10a and 10b. Are set. Therefore, when two FETs are manufactured by the method of this embodiment, even if the sizes of the two n-type GaAs active regions 10a and 10b and the size of the resist pattern 22 are different, the two FETs manufactured are different. The threshold voltage will be the same. That is, the threshold voltages of the two manufactured FETs can be made equal.
[0058]
3. Third embodiment
In this embodiment, two FETs are manufactured by a method similar to that of the first embodiment. However, the etching conditions for forming the recess by wet etching are set such that the etching profile in the n-type GaAs active region is substantially different between the two n-type GaAs active regions.
[0059]
More specifically, using the reference numerals in FIG. 6, the semi-insulating GaAs region whose distance from the boundary 44 between the n-type GaAs active region and the semi-insulating GaAs region is within D is effectively “ In the case where it contributes to the reaction based on the principle of the voltaic battery, the length of the first opening 24a constituting one opening 20a in the gate length direction is L _a1 And the length in the gate width direction is W _a1 And the length of the first opening 24b constituting the other opening 20b in the gate length direction is L _b1 And the gate width direction length is W _b1 And the length in the gate length direction of the lead-out wiring forming opening 30a forming one second opening 26a is L _a2 And the gate width direction length is W _a2 And the length in the gate length direction of the lead-out wiring forming opening 30b constituting the other second opening 26b is L _b2 And the gate width direction length is W _b2 And W _a2 > D and W _b2 > D, (L _a2 × D) / (L _a1 × W _a1 )> (L _b2 × D) / (L _b1 × W _b1 ).
[0060]
Thus (L _a2 × D) / (L _a1 × W _a1 )> (L _b2 × D) / (L _b1 × W _b1 ), It is considered that the degree of occurrence of the reaction based on the “principle of the voltaic cell” is different between the two openings 20a and 20b, so that the etching profile in the portion of the n-type GaAs active region is two. It is considered that the n-type GaAs active regions 10a and 10b substantially differ from each other. It is considered that the extent to which a reaction based on the "Volta battery principle" occurs in one opening 20a is greater than the extent to which a reaction based on the "Volta battery principle" occurs in the other opening 20b.
[0061]
Further, in this embodiment, wet etching is performed so that the etching profile in the portion of the n-type GaAs active region is substantially different between the two n-type GaAs active regions 10a and 10b. Etching conditions are set. Therefore, when two FETs are manufactured by the method of this embodiment, the threshold voltages of the two manufactured FETs are different. When the degree of occurrence of the reaction based on the "Volta cell principle" in one opening 20a is larger than the degree of occurrence of the reaction based on the "Volta cell principle" in the other opening 20b, the FET manufactured on the side of one opening 20a The threshold voltage is located on the more positive side than the threshold voltage of the FET manufactured on the other opening 20b side. That is, the threshold voltage of the FET manufactured on one opening 20a side can be set to be more positive than the threshold voltage of the FET manufactured on the other opening 20b side.
[0062]
4. Fourth embodiment
7 to 10 are views showing the steps of manufacturing an FET having a recess structure, which are provided for describing this embodiment. 7, 9 and 10, (A) is a plan view, and (B) is a cross-sectional view showing a cut section taken along line II in (A). FIGS. 8A to 8C are cross-sectional views showing cuts at positions corresponding to cross sections taken along line II in FIG. 7A. Hereinafter, a method of manufacturing the FET having the recess structure will be described with reference to FIGS.
[0063]
First, after a semiconductor substrate 14 is formed by the same method as in the first embodiment, a source electrode 16 and a drain electrode 18 are formed on the n-type GaAs active region 10 at predetermined intervals.
[0064]
Next, a first resist pattern 46 having an opening 20 having an overhanging cross section is formed on the semiconductor substrate 14 so as to cover the source electrode 16 and the drain electrode 18 (FIGS. 7A and 7B). )). The opening 20 comprises first, second and third openings 24, 26 and 28. The first opening 24 is for forming a gate electrode, and the second opening 26 is for forming an electrode wiring. The opening 20 is formed so as to be located on the n-type GaAs active region 10. The first opening 24 is formed so as to be located between the source electrode 16 and the drain electrode 18.
[0065]
At this stage, a gate electrode forming region is formed on a semiconductor substrate 14 having an island-shaped n-type GaAs active region 10 and a semi-insulating GaAs region 12 surrounding the periphery of the n-type GaAs active region 10. A first resist pattern 46 having at least an opening 20 composed of a first opening 24 and an electrode wiring forming second opening 26 connected to the first opening 24 forms an n-type GaAs active region. It is formed so as to be located on the region 10.
[0066]
Next, using the first resist pattern 46 as a mask, the portions of the semiconductor substrate 14 exposed from the openings 24 to 28 are etched using an etchant composed of a mixture of phosphoric acid, hydrogen peroxide and water. Then, a recess 34 is formed by etching (FIG. 8A).
[0067]
Next, after aluminum (Al) as a gate electrode forming material is vacuum-deposited, the first resist pattern 46 is removed, so that the gate electrode 36 and the electrode wiring 38 made of aluminum (Al) are formed in the recess 34. (FIGS. 8B and 8C). The gate electrode 36 is formed in the portion of the recess 34 exposed from the first opening 24, and the electrode wiring 38 is formed in the portion of the recess 34 exposed from the second opening 26.
[0068]
Next, after forming a second resist pattern 48 covering a portion of the n-type GaAs active region 10 used as an operation layer of the FET so as to cover the gate electrode 36, the source electrode 16 and the drain electrode 18, the second resist pattern 48 is formed. Oxygen (O) or boron (B) is ion-implanted into portions of the semiconductor substrate 14 that are not covered with the resist pattern 48 and the electrode wiring 38 (FIGS. 9A and 9B). By ion implantation of oxygen (O) or boron (B), the portion of the n-type GaAs active region 10 not covered with the second resist pattern 48 and the electrode wiring 38 is made semi-insulating.
[0069]
Finally, the second resist pattern 48 is removed (FIG. 10). As described above, the FET having the recess structure is manufactured.
[0070]
When the first resist pattern 46 is formed so that the opening 20 is located on the n-type GaAs active region 10, only the n-type GaAs active region 10 is exposed from the opening 20. Therefore, when a recess is formed by wet-etching the portion of the semiconductor substrate 14 exposed from the opening 20, a reaction based on the "principle of the voltaic cell" does not occur, and the etching profile becomes flat. That is, the etching depth becomes uniform over the entire area exposed from the opening 20. Therefore, when a plurality of FETs are manufactured by the method of this embodiment, even if the dimensions of the n-type GaAs active region 10 and the dimensions of the first resist pattern 46 are different, the threshold voltage of each manufactured FET is different. Will be the same. That is, the threshold voltage of each manufactured FET can be made the same.
[0071]
Next, a modified example of this embodiment will be described. FIG. 11 is a manufacturing process diagram of an FET having a recess structure for describing a modification of this embodiment, and shows the process steps shown in FIG. 7 in the fourth embodiment. FIG. 11A is a plan view, and FIG. 11B is a cross-sectional view showing a cut surface taken along a line II in FIG. 11A.
[0072]
As shown in FIGS. 11A and 11B, in a modification of this embodiment, an etching amount monitoring element 50 for monitoring the etching depth when forming a recess by wet etching is to be manufactured by FET. It is formed adjacent to the region 52. The etching amount monitoring element 50 is formed by performing the steps up to the resist pattern forming step in the FET manufacturing method described in the first embodiment. However, this etching amount monitoring element 50 is formed in accordance with the manufacturing process of the FET according to the fourth embodiment described above.
[0073]
That is, the n-type GaAs active region 54 for monitoring is formed simultaneously with the formation of the n-type GaAs active region 10. In short, the n-type GaAs active region 10 and the monitoring n-type GaAs active region 54 are formed by ion-implanting silicon (Si) as an n-type impurity into the same semi-insulating GaAs substrate and then performing a heat treatment at 800 ° C. . The semi-insulating GaAs substrate 56 in the region where the etching amount monitoring element 50 in which silicon (Si) is not ion-implanted is formed is the monitoring semi-insulating GaAs region 56, and the monitoring semiconductor substrate 58 is the monitoring n-type GaAs. It comprises an active region 54 and a semi-insulating GaAs region 56 for monitoring. The monitor source electrode 60 and the monitor drain electrode 62 are formed simultaneously on the monitor n-type GaAs active region 54 when the source electrode 16 and the drain electrode 18 are formed. Further, the monitor resist pattern 64 covering the monitor source electrode 60 and the monitor drain electrode 62 is simultaneously formed using the same resist film when forming the first resist pattern 46 covering the source electrode 16 and the drain electrode 18. Form.
[0074]
An opening 66 is formed in the monitor resist pattern 64, and the opening 62 is formed of first to third openings 68 to 72. The first opening 68 is formed so as to be located in the n-type GaAs active region 54 for monitoring between the source electrode 60 for monitoring and the drain electrode 62 for monitoring, and the second opening 70 is semi-insulating for monitoring. It is formed so as to be located on the GaAs region 56.
[0075]
Here, the monitor semi-insulating GaAs region 56 whose distance from the boundary between the monitor n-type GaAs active region 54 and the monitor semi-insulating GaAs region 56 is within D is effectively "the principle of the voltaic battery". And the surface area (S1) of the monitoring n-type GaAs active region 54 (first region) exposed from the first opening 68 and the monitor exposed from the second opening 70 Surface area (S2) of a region (second region) in which the distance from the boundary between the n-type GaAs active region 54 for monitoring and the semi-insulating GaAs region 16 for monitoring is within D in the semi-insulating GaAs region 56 for monitoring. Are set so that the ratio S2 / S1 is about 1/20.
[0076]
In order to make the etching depth when forming a recess by wet etching using such an etching amount monitoring element 50 a predetermined size, first, one of the wirings penetrates the monitoring resist pattern 64. In the same manner, the other wiring is connected to the monitor drain electrode 62 through the monitor resist pattern 64. When a recess is formed by wet etching, a voltage is applied between the monitor source electrode 60 and the monitor drain electrode 62, and at this time, a voltage is applied between the monitor source electrode 60 and the monitor drain electrode 62. The value of the flowing current is monitored, and when the current value reaches a predetermined value, the wet etching is terminated. Here, since the ratio S2 / S1 between S1 and S2 is as small as about 1/20, and the degree of occurrence of a reaction based on the "principle of the voltaic battery" is small, the etching depth is equal to the entire area exposed from the opening 66 , And thus the etching depth of the region exposed from the opening 66 is the same as the etching depth of the region exposed from the opening 20. Therefore, the value of the current flowing between the monitor source electrode 60 and the monitor drain electrode 62 is monitored, and when the current value reaches a predetermined value, the wet etching is terminated, thereby exposing from the opening 20. The region can have a predetermined etching depth.
[0077]
The steps after the step of forming the recess by wet etching are performed in the same manner as in the above-described fourth embodiment.
[0078]
Obviously, the present invention is not limited to the above embodiments.
[0079]
For example, in each of the above-described embodiments, a GaAs substrate is used as a substrate, but another III-V compound semiconductor substrate may be used, or a III-V compound semiconductor layer formed by crystal growth may be used. May be.
[0080]
Further, in each of the above-described embodiments, the n-type GaAs active region is formed by ion-implanting silicon (Si) into the semi-insulating GaAs substrate and then performing heat treatment. However, silicon (Si) is formed during crystal growth of the GaAs layer. ) May be formed by adding an n-type impurity. Although the semi-insulating GaAs region is a portion of the semi-insulating GaAs substrate where silicon (Si) is not ion-implanted, oxygen, boron, protons, etc. are ion-implanted into the n-type GaAs active region to achieve semi-insulation. It is good also as the area which did.
[0081]
Further, in each of the embodiments described above, the description has been made using the manufacturing process of the FET having the n-type channel. However, the present invention can be applied to the manufacturing process of the FET having the P-type channel.
[0082]
In the above-described second and third embodiments, the description has been made using the manufacturing process of two FETs. However, the present invention can be applied to the manufacturing process of three or more FETs.
[0083]
In each of the embodiments described above, the case where the recess is formed by wet etching has been described. ₆ , CF ₄ It can also be applied to the case where a recess is formed by dry etching using reactive plasma such as described above.
[0084]
【The invention's effect】
As is apparent from the above description, according to the method for setting the first etching condition of the present invention, the surface area of the active region exposed from the first opening is defined as S1, and the active region and the semi-insulating semiconductor region are separated from each other. When the distance from the boundary is D, the semi-insulating semiconductor region exposed from the second opening is divided into the second and third regions from the boundary side, and the surface area of the second region is S2. By changing the value of D and changing the value of S2 for each value of D, the value of S2 / S1 for each combination of the value of D and the value of S2 is determined, and a plurality of obtained values of S2 / S1 are obtained. Of the S2 / S1 at least in which the etching rate is substantially uniform in the active region and the semi-insulating semiconductor region near the boundary between the active region and the semi-insulating semiconductor region. Set values as etching conditions
[0085]
When a recess is formed by wet etching under such etching conditions, the etching rate in the vicinity of the active region and the semi-insulating semiconductor region around the boundary between the active region and the semi-insulating semiconductor region is substantially reduced. It becomes uniform uniformly. Therefore, the etching profile is substantially flat over both the active region and the semi-insulating semiconductor region. That is, the etching depth is substantially uniform over the entire area exposed from the opening. Therefore, when a plurality of FETs are manufactured by the first manufacturing method of the FET according to the present invention, the threshold voltage of each manufactured FET is the same even if the size of the active region and the size of the resist pattern are different. . That is, the threshold voltage of each manufactured FET can be made the same.
[0086]
According to the second method for setting etching conditions of the present invention, the surface area of the active region exposed from the first opening is S1, and the distance from the boundary between the active region and the semi-insulating semiconductor region is D. By the way, the semi-insulating semiconductor region exposed from the second opening is divided into the second and third regions from the boundary between the active region and the semi-insulating semiconductor region, and the surface area of the second region is defined as S2. Then, by changing the value of D and changing the value of S2 for each value of D, the value of S2 / S1 for each combination of the value of D and the value of S2 is obtained, and a plurality of obtained S2 / S1 values are obtained. Among the values of S1, the value of S2 / S1 at which the etching profile in the active region portion becomes substantially the same for each active region is set as the etching condition.
[0087]
When a recess is formed by wet etching under such etching conditions, the etching profile in the active region portion becomes substantially the same for each active region. Therefore, when a plurality of FETs are manufactured by the second method for manufacturing FETs of the present invention, the threshold voltage of each manufactured FET becomes the same even if the size of the active region, the size of the resist pattern, and the like are different. . That is, the threshold voltage of each manufactured FET can be made the same.
[0088]
According to the third method for setting etching conditions of the present invention, the surface area of the active region exposed from the first opening is S1, and the distance from the boundary between the active region and the semi-insulating semiconductor region is D. By the way, the semi-insulating semiconductor region exposed from the second opening is divided into the second and third regions from the boundary between the active region and the semi-insulating semiconductor region, and the surface area of the second region is defined as S2. Then, by changing the value of D and changing the value of S2 for each value of D, the value of S2 / S1 for each combination of the value of D and the value of S2 is obtained, and a plurality of obtained S2 / S1 values are obtained. From the values of S1, the value of S2 / S1 where the etching profile in the active region portion is substantially different for each active region is set as the etching condition.
[0089]
When a recess is formed by wet etching under such etching conditions, an etching profile in an active region portion is substantially different for each active region. Therefore, when a plurality of FETs are manufactured by the third method of manufacturing an FET according to the present invention, the threshold voltages of the manufactured FETs are different. That is, the threshold voltage of each manufactured FET can be changed.
[Brief description of the drawings]
FIGS. 1A and 1B are manufacturing process diagrams of an FET having a recess structure provided for describing a first embodiment; FIGS.
FIGS. 2A and 2B are manufacturing process diagrams of the FET having a recessed structure, which are used for describing the first embodiment and follow FIG. 1;
FIGS. 3A and 3B are manufacturing process diagrams of the FET having the recessed structure, which are used for describing the first embodiment and follow FIG. 2;
FIGS. 4A and 4B are manufacturing process diagrams of the FET having the recessed structure, which are used for describing the first embodiment and follow FIG. 3;
FIGS. 5A and 5B are manufacturing process diagrams of the FET having the recess structure, which are provided for describing the first embodiment and follow FIG. 4;
FIG. 6 is a manufacturing process diagram of two FETs having a recess structure, which is used for describing the second and third embodiments.
FIGS. 7A and 7B are manufacturing process diagrams of an FET having a recess structure for explaining a fourth embodiment; FIGS.
FIGS. 8A to 8C are manufacturing process diagrams of the FET having the recessed structure, which are used for describing the fourth embodiment and are continued from FIG. 7;
FIGS. 9A and 9B are manufacturing process diagrams of an FET having a recess structure, following FIG. 8, for explaining the fourth embodiment;
FIGS. 10A and 10B are manufacturing process diagrams of an FET having a recess structure, following FIG. 9, for explaining the fourth embodiment;
FIGS. 11A and 11B are manufacturing process diagrams of an FET having a recess structure, for explaining a modification of the fourth embodiment; FIGS.
FIGS. 12A and 12B are diagrams for explaining a conventional phenomenon.
FIG. 13 is a diagram for explaining a conventional phenomenon.
[Explanation of symbols]
10, 10a, 10b: n-type GaAs active region
12: semi-insulating GaAs region
14: Semiconductor substrate
16, 16a, 16b: source electrode
18, 18a, 18b: drain electrode
20, 20a, 20b: Opening
22: Resist pattern
24, 24a, 24b: first opening
26, 26a, 26b: second opening
28, 28a, 28b: third opening
30, 30a, 30b: lead-out wiring forming openings
32, 32a, 32b: opening for gate electrode pad
34: Recess
36: Gate electrode
38: Electrode wiring
40: Leader wiring
42: Gate electrode pad
44: Boundary
46: First resist pattern
48: Second resist pattern

Claims (6)

Exposing only the active region portion located on the active region on a semiconductor substrate having an island-shaped active region formed by doping impurities and a semi-insulating semiconductor region surrounding the active region at the top thereof A first opening for forming a gate electrode to be formed, and a second opening for forming an electrode wiring which is connected to the first opening and exposes only the semi-insulating semiconductor region located on the semi-insulating semiconductor region. Forming a resist pattern having at least an opening consisting of, and thereafter, using the resist pattern as a mask, wet etching the portion of the semiconductor substrate exposed from the opening to form a recess, In setting the etching conditions for
The surface area of the active region exposed from the first opening is defined as S1, and the surface is exposed from the second opening at a distance D from the boundary between the active region and the semi-insulating semiconductor region. When the semi-insulating semiconductor region is divided into a second region and a third region from the boundary side, and the surface area of the second region is S2,
By changing the value of D and changing the value of S2 for each value of D, the value of S2 / S1 for each combination of the value of D and the value of S2 is determined. Among the values of S2 / S1, the value of S2 / S1 at which the etching rate in at least the active region and the semi-insulating semiconductor region sandwiching the boundary becomes substantially uniform is set as the etching condition. A method for setting etching conditions, characterized in that: Exposing only the active region portion located on the active region on a semiconductor substrate having an island-shaped active region formed by doping impurities and a semi-insulating semiconductor region surrounding the active region at the top thereof A first opening for forming a gate electrode to be formed, and a second opening for forming an electrode wiring which is connected to the first opening and exposes only the semi-insulating semiconductor region located on the semi-insulating semiconductor region. Forming a resist pattern having an opening comprising at least: a step of forming a recess by wet etching a portion of the semiconductor substrate exposed from the opening using the resist pattern as a mask; and forming a gate in the recess. Including a step of forming an electrode and electrode wiring, in a method of manufacturing a field-effect transistor having a recess structure,
A method for manufacturing a field effect transistor, wherein the wet etching is performed under etching conditions set by the method for setting etching conditions according to claim 1. A semiconductor substrate having a plurality of island-shaped active regions formed by doping impurities and a semi-insulating semiconductor region surrounding a periphery of the active region; Forming a resist pattern having a plurality of openings each including at least a first opening and a second opening for forming an electrode wiring connected to the first opening and located on the semi-insulating semiconductor region; Thereafter, in order to form a recess by wet etching the portion of the semiconductor substrate exposed from each of the openings using the resist pattern as a mask, in setting the etching conditions of the wet etching,
The surface area of the active region exposed from the first opening is defined as S1, and the surface is exposed from the second opening at a distance D from the boundary between the active region and the semi-insulating semiconductor region. When the semi-insulating semiconductor region is divided into a second region and a third region from the boundary side, and the surface area of the second region is S2,
By changing the value of D and changing the value of S2 for each value of D, the value of S2 / S1 for each combination of the value of D and the value of S2 is determined. The value of S2 / S1 at which the etching profile at the active region becomes substantially the same for each active region is set as the etching condition from among the values of S2 / S1. Setting method. Forming a gate electrode located on the active region on a semiconductor substrate having a plurality of island-shaped active regions formed by doping impurities and a semi-insulating semiconductor region surrounding the periphery of the active region; Forming a resist pattern having a plurality of openings each having at least a first opening and a second opening for electrode wiring formation connected to the first opening and located on the semi-insulating semiconductor region; A step of forming a recess by wet etching a portion of the semiconductor substrate exposed from each of the openings using the resist pattern as a mask, and a step of forming a gate electrode and an electrode wiring in the recess. In a method for manufacturing a plurality of field effect transistors having a recess structure,
A method for manufacturing a field-effect transistor, wherein the wet etching is performed under etching conditions set by the method for setting etching conditions according to claim 3. A semiconductor substrate having a plurality of island-shaped active regions formed by doping impurities and a semi-insulating semiconductor region surrounding a periphery of the active region; Forming a resist pattern having a plurality of openings each including at least a first opening and a second opening for forming an electrode wiring connected to the first opening and located on the semi-insulating semiconductor region; Thereafter, in order to form a recess by wet etching the portion of the semiconductor substrate exposed from each of the openings using the resist pattern as a mask, in setting the etching conditions of the wet etching,
The surface area of the active region exposed from the first opening is defined as S1, and the surface is exposed from the second opening at a distance D from the boundary between the active region and the semi-insulating semiconductor region. When the semi-insulating semiconductor region is divided into a second region and a third region from the boundary side, and the surface area of the second region is S2,
By changing the value of D and changing the value of S2 for each value of D, the value of S2 / S1 for each combination of the value of D and the value of S2 is determined. The setting of the etching condition, wherein the value of S2 / S1 in which the etching profile in the active region is substantially different for each active region is set as the etching condition from among the values of S2 / S1. Method. Forming a gate electrode located on the active region on a semiconductor substrate having a plurality of island-shaped active regions formed by doping impurities and a semi-insulating semiconductor region surrounding the periphery of the active region; Forming a resist pattern having a plurality of openings each having at least a first opening and a second opening for electrode wiring formation connected to the first opening and located on the semi-insulating semiconductor region; A step of forming a recess by wet etching a portion of the semiconductor substrate exposed from each of the openings using the resist pattern as a mask, and a step of forming a gate electrode and an electrode wiring in the recess. In a method for manufacturing a plurality of field effect transistors having a recess structure,
A method for manufacturing a field effect transistor, wherein the wet etching is performed under etching conditions set by the method for setting etching conditions according to claim 5.

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