JPH10107043A - Field effect semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect semiconductor device which can be operated highly efficiently at a low power supply voltage and can be manufactured with a high yield. SOLUTION: An n<-> -type area 10 having a carrier concentration lower than that in an n-type channel area 3 is formed by ion implantation in part of the channel area 3 so that the area 10 can reach a prescribed depth. Then a gate electrode 8 is formed on the channel area 3 including the area 10 so as to control the flow of an electric current with a depletion layer 11 formed around the area 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect type semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in portable terminals, the battery voltage has been reduced. Therefore, the transmission system power amplifier of the portable terminal is required to operate at a low power supply voltage. On the other hand, a transmission power amplifier consumes a large amount of power, and is required to operate with high efficiency.

In order to operate a power amplifier at a low power supply voltage, it is effective to reduce the on-resistance by shortening the gate length of an FET (field effect transistor) which is a basic element. However, when the gate length is reduced, the contact area between the gate electrode and the channel region is reduced, and the gate breakdown voltage is reduced. As a result, a problem arises in that a large output cannot be taken out and the efficiency is reduced.

Therefore, an IEDM (International Electr
on Device Meeting) 95, pages 181 to 184, a method of providing a V-shaped groove by etching a part of a channel region immediately below a gate electrode in a spike shape.

FIG. 10 is a schematic sectional view showing a structure of a conventional GaAs-MESFET (metal-semiconductor field effect transistor) having a V-shaped groove in a channel region. In FIG. 10, high-concentration n-type regions (n ⁺ regions) 22 are formed at predetermined intervals on the surface of a semi-insulating GaAs substrate 21, and n-type channel regions 23 are formed between these high-concentration n-type regions 22. Have been. A source electrode 24 a and a drain electrode 24 b are formed on the high-concentration n-type region 22, respectively, and a gate electrode 25 is formed on the n-type channel region 23. An insulating film 26 is formed between the source electrode 24a and the gate electrode 25 and between the drain electrode 24b and the gate electrode 25.

The n-type channel region 2 immediately below the gate electrode 25
3, a V-shaped groove 27 extending from the interface with the gate electrode 25 to the inside is formed. In this FET, when a predetermined voltage is applied to the gate electrode 25, the V-shaped groove 27
Depletion layer 28 is formed around. In this case, the effective gate length for controlling the current flow in the n-type channel region 23 is determined by the width L1 of the depletion layer 28 around the V-shaped groove 27. Therefore, the gate electrode 25 and the n-type channel region 2
The effective gate length can be shortened without reducing the contact area with the gate electrode 3, and the on-resistance can be reduced while keeping the gate breakdown voltage high. As a result, an FET that can operate with high efficiency and a low power supply voltage is realized.

[0007]

However, in the above-mentioned conventional FET, an etching technique is used to provide the V-shaped groove 27 in the n-type channel region 23 immediately below the gate electrode 25. It is difficult to control depth and width accurately. For this reason, there is a problem that the reproducibility of the characteristics of the FET is low and the manufacturing yield is reduced.

An object of the present invention is to provide a field effect type semiconductor device which can operate with high efficiency and a low power supply voltage and can be manufactured with high yield, and a method of manufacturing the same.

[0009]

According to a first aspect of the present invention, there is provided a field effect type semiconductor device having a gate electrode formed on a channel region of one conductivity type. A depletion layer forming region having a carrier concentration lower than that of the channel region or a conductivity type opposite to the one conductivity type is formed in a part of the channel region so as to reach a predetermined depth from an interface with the gate electrode. is there.

The depletion layer forming region may be an impurity region having a lower carrier concentration than the channel region, an intrinsic region having a carrier concentration of almost 0, or an impurity region having a conductivity type opposite to that of the channel region. It may be.

In this field-effect type semiconductor device, since a low carrier concentration or reverse conductivity type depletion layer forming region is formed in a part of the channel region, when a predetermined voltage is applied to the gate electrode, the depletion layer is formed. A depletion layer is formed around the formation region. In this case, the effective gate length for controlling the current flow in the channel region is determined by the width (length in the channel length direction) of the depletion layer around the depletion layer formation region.

Therefore, the effective gate length can be reduced without reducing the contact area between the gate electrode and the channel region, and the on-resistance can be reduced while keeping the gate breakdown voltage high. Furthermore, since the width and depth of the depletion layer formation region can be accurately controlled,
The reproducibility of the characteristics of the field effect type semiconductor device is improved.

As a result, a field effect semiconductor device which can operate with high efficiency and a low power supply voltage and has a high production yield is realized. In the field-effect semiconductor device according to the second invention, a first gate electrode having a Schottky barrier of a predetermined height is formed on the channel region, and the first gate electrode is formed on at least one side of the first gate electrode in the direction of the channel length. First
A second gate electrode having a lower Schottky barrier than that of the first gate electrode is formed.

In this field-effect type semiconductor device, the first and second gate electrodes having a lower Schottky barrier than the first gate electrode are formed on at least one side of the first gate electrode. When a predetermined voltage is applied to the second gate electrode, the depletion layer formed below the first gate electrode becomes deeper than the depletion layer formed below the second gate electrode. In this case, the effective gate length for controlling the current flow in the channel region is determined by the width (length in the channel length direction) of a depletion layer formed below the first gate electrode.

Therefore, the effective gate length can be reduced without reducing the contact area between the gate electrode and the channel region, and the on-resistance can be reduced while keeping the gate breakdown voltage high. Further, since the width of the first gate electrode can be accurately controlled, the reproducibility of the characteristics of the field effect semiconductor device is improved.

As a result, a field-effect semiconductor device which can operate with high efficiency and a low power supply voltage and has a high manufacturing yield can be obtained. The method of manufacturing a field-effect semiconductor device according to a third aspect of the present invention includes the step of forming a depletion layer forming region having a carrier concentration lower than that of the channel region or a conductivity type opposite to the one conductivity type in a part of the one conductivity type channel region. The gate electrode is formed to have a predetermined depth from the surface, and a gate electrode is formed on a channel region including a depletion layer forming region.

According to this method of manufacturing a field-effect semiconductor device, a low-carrier-concentration or reverse-conductivity-type depletion layer forming region is formed in a part of the one-conductivity-type channel region.
When a predetermined voltage is applied to the gate electrode, a depletion layer is formed around the depletion layer formation region. In this case, the effective gate length for controlling the current flow in the channel region is determined by the width (length in the channel length direction) of the depletion layer around the depletion layer formation region.

Therefore, the effective gate length can be reduced without reducing the contact area between the gate electrode and the channel region, and the on-resistance can be reduced while keeping the gate breakdown voltage high. Furthermore, since the width and depth of the depletion layer formation region can be accurately controlled,
The reproducibility of the characteristics of the field effect type semiconductor device is improved.

As a result, a field effect semiconductor device which can operate with high efficiency and a low power supply voltage and has a high production yield can be obtained. In particular, the depletion layer forming region may be formed by ion-implanting an impurity having a conductivity type opposite to the one conductivity type into the channel region. In this case, carriers of one conductivity type in the channel region are compensated for by carriers of the opposite conductivity type, so that a region for forming a depletion layer of low carrier concentration or opposite conductivity type is formed in the channel region.

The depletion layer forming region may be formed by ion-implanting an impurity for inactivating carriers into the channel region. In this case, a depletion layer forming region having a low carrier concentration is formed in the channel region by inactivating some of the carriers in the channel region.

Thus, the depth of the depletion layer forming region,
Parameters such as the width and the carrier concentration can be controlled accurately. Thus, a field-effect semiconductor device can be manufactured with a higher yield.

According to a fourth aspect of the invention, there is provided a method of manufacturing a field effect type semiconductor device, wherein a first gate electrode having a Schottky barrier having a predetermined height is formed on a channel region, and the first gate electrode is formed in a channel length direction. A second electrode having a lower Schottky barrier than the first gate electrode on at least one side of the electrode;
Is formed.

According to this method of manufacturing a field-effect semiconductor device, the second gate electrode having a lower Schottky barrier than the first gate electrode is formed on at least one side of the first gate electrode. When a predetermined voltage is applied to the first and second gate electrodes, a depletion layer formed below the first gate electrode becomes deeper than a depletion layer formed below the second gate electrode. In this case, the effective gate electrode that controls the flow of current in the channel region is determined by the width (length in the channel length direction) of the depletion layer formed below the first gate electrode.

Therefore, the effective gate electrode can be shortened without reducing the contact area between the gate electrode and the channel region, and the on-resistance can be reduced while keeping the gate breakdown voltage high. Further, since the width and depth of the first gate electrode can be accurately controlled, the reproducibility of the characteristics of the field-effect semiconductor device is improved.

As a result, a field-effect semiconductor device which can operate with high efficiency and a low power supply voltage and has a high production yield can be obtained.

[0026]

1 to 5 are process sectional views showing a method for manufacturing a field effect type semiconductor device according to a first embodiment of the present invention. In the first embodiment, a GaAs-MESFET will be described as an example of a field-effect semiconductor device.

First, as shown in FIG. 1A, an SiN film 2 having a thickness of 0.02 μm is formed on the surface of a semi-insulating GaAs substrate 1 by using a PCVD method (plasma chemical vapor deposition). I do. Next, as shown in FIG. 1B, an n-type channel region 3 is formed on the surface of the GaAs substrate 1 by ion implantation using a photoresist film (not shown) as a mask. As implantation ions, Si is used. As ion implantation conditions, an implantation energy is set to 180 keV, and an implantation dose is set to 4 × 10 ¹² cm ⁻² . n-type channel region 3
Is, for example, about 0.2 μm.

Next, as shown in FIG. 1C, a photoresist pattern 9 is formed on the SiN film 2 at the center of the n-type channel region 3, and the photoresist pattern 9 is used as a mask by ion implantation. A high-concentration n-type region (n ⁺ region) 4 is formed on the surface of the GaAs substrate 1. The width W1 of the photoresist pattern 9 is 1.7 μm. Further, Si was used as implanted ions, and the implantation conditions were as follows: implantation energy was 150 keV, and implantation dose was 5 ×.
It is set to 10 ¹³ cm ^-3 .

Thereafter, the width of the photoresist pattern 9 is reduced by etching it with oxygen plasma etching. As a result, as shown in FIG. 2D, the photoresist pattern 9 having a pattern width W2 of 0.7 μm is formed.
a is formed. Further, as shown in FIG.
By R-PCVD (Electron Cyclotron Resonance Plasma Chemical Vapor Deposition), a thickness of 0.3 μm is formed on the upper and side surfaces of the photoresist pattern 9a and on the SiN film 2.
Forming a SiO ₂ film 5.

Thereafter, as shown in FIG. 2F, the SiO ₂ film 5 on the side surface of the photoresist pattern 9a is selectively removed by immersion in a buffered hydrofluoric acid solution. In addition,
The SiO ₂ film 5 on the side surface of the photoresist pattern 9a is
It may be removed by dry etching F ₄ system.

Next, as shown in FIG. 3 (g), the width of the photoresist pattern 9a is reduced by etching it with oxygen plasma etching. As a result, the photoresist pattern 9 having a pattern width W3 of 0.3 μm
b is formed.

Next, as shown in FIG.
An SiN film 6 having a thickness of 0.1 μm is formed on the surface of the SiO ₂ film
To form Thereafter, as shown in FIG. 3I, the SiN film 6 on the side surface of the photoresist pattern 9b is removed by dipping in a buffered hydrofluoric acid solution. Note that the SiN film 6 on the side surface of the photoresist pattern 9b may be removed by CF ₄ -based dry etching.

Next, as shown in FIG. 4J, the photoresist pattern 9b and the SiO ₂ film 5 and the SiN film 6 formed thereon are removed by a lift-off method by dipping in a photoresist removing solution. . As a result, an opening 13 is formed above the n-type channel region 3.

Next, as shown in FIG.
_TwoIon implantation is performed using the film 5 and the SiN film 6 as masks.
A predetermined depth from the surface in the n-type channel region 3
n^-A region 10 is formed. As the implanted ions, Mg (ma
Gnesium) and the ion implantation conditions are as follows:
The energy was 10 keV and the implantation dose was 1 × 10 ¹²
cm^-2And n^-The depth of the region 10 is about 0.05 μm
It is.

The implanted ions are Mg, Be, which form a conductivity type opposite to that of the n-type channel region 3 in GaAs.
A p-type impurity such as (beryllium) or Zn (zinc) may be used, or B (boron), O (oxygen), Cr (chromium) for inactivating carriers in the n-type channel region 3.
May be used.

After the ion implantation, annealing is performed at a high temperature in order to electrically activate the ions in the implantation region. For example, the annealing temperature is set to 850 by using the short-time annealing method.
C. and the annealing time is 5 seconds.

Thereafter, as shown in FIG.
SiN film 6 on n-type region 4, SiO _TwoFilm 5 and SiN
After the removal of the film 2, the source
The source electrode 7a and the drain electrode 7b are formed.

Finally, as shown in FIG.
Forming a photoresist pattern for electrodes (not shown),
CF_FourAnd O_TwoEtching in mixed gas
Thereby, the SiN films 6 and 2 in the opening 13 are removed. this
When the SiO 2 in the opening 13 _TwoThe film 5 is made of CF_FourAnd O
_TwoBy plasma etching in mixed gas of
Not etched.

Thereafter, a gate electrode 8 is formed by depositing a metal for a gate electrode and removing the photoresist pattern for the gate electrode and the metal for the gate electrode thereover by a lift-off method. Thus, the gate electrode 8
N ⁻ region 10 is formed in n type channel region 3 immediately below the central portion of.

FIG. 6 is an enlarged sectional view for explaining the operation of the field effect type semiconductor device of the first embodiment. As shown in FIG. 6, in the field-effect semiconductor device of the first embodiment, a predetermined voltage is applied to gate electrode 8 because n ⁻ region 10 is formed in a part of n-type channel region 3. Then, depletion layer 11 is formed immediately below gate electrode 8 and around n ⁻ region 10. Here, the relationship between the thickness d of the depletion layer and the carrier concentration N is as follows.

D∝√ (1 / N) In this case, the current flowing between the source and the drain is mainly n
^- controlled by the depletion layer 11 of the surrounding region 10. That is, the effective gate length for controlling the current flow in n-type channel region 3 is determined by width L2 of depletion layer 11 around n ⁻ region 10.

Therefore, the effective gate length can be reduced without reducing the contact area between gate electrode 8 and n-type channel region 3. As a result, the on-resistance can be reduced while keeping the gate withstand voltage high, and operation can be performed with high efficiency and at a low power supply voltage.

Since the n ⁻ region 10 is formed by ion implantation, parameters such as the width, depth, and carrier concentration of the n ⁻ region 10 can be accurately controlled.
Therefore, the reproducibility of the characteristics is high, and the production yield is improved.

In the first embodiment, the n-type channel region is used.
In region 3, n is used as a depletion layer forming region. ^-With the area 10
However, the carrier concentration is almost 0 as a depletion layer forming region.
Intrinsic region close to
A p-type region may be provided as the region.

Next, a method of manufacturing a field-effect semiconductor device according to a second embodiment of the present invention will be described. Also in the second embodiment, GaAs is used as an example of the field-effect semiconductor device.
-MESFET will be described. 7 and 8 are process sectional views showing a method for manufacturing a field-effect semiconductor device according to a second embodiment of the present invention.

First, FIGS. 1A to 1C in the first embodiment.
The structure shown in FIG. 7A is manufactured in the same manner as in the step of FIG. In the step of FIG. 7A, annealing is performed at a high temperature in order to electrically activate ions in the ion implantation region. For example, using a short-time annealing method, the annealing temperature is set to 850 ° C., and the annealing time is set to 5 seconds.

Next, as shown in FIG.
After removing the SiN film 6, the SiO ₂ film 5 and the SiN film 2 on the mold region 4, a source electrode 7a and a drain electrode 7b are formed on the high concentration n-type region 4, respectively.

Next, as shown in FIG. 7C, a first gate electrode photoresist pattern (not shown) is formed except for the opening 13 on the n-type channel region 3, and the opening 13 is formed. The SiN film 2 having a thickness of 0.02 μm is removed by plasma etching in a mixed gas of CF ₄ and O ₂ . At the same time, the SiN film 6 is also etched, but remains after the SiN film 2 is completely removed since the SiN film 6 is thicker than the SiN film 2. At this time, the SiO ₂ film 5 in the opening 13 is hardly etched by plasma etching in a mixed gas of CF ₄ and O ₂ .

Thereafter, a first gate electrode material is vapor-deposited, the first gate electrode photoresist pattern is removed together with the first gate electrode metal thereon, and the n-type in the opening 13 is lifted off. First on channel region 3
Of the gate electrode 14 is formed. This first gate electrode 1
No. 4 is formed using a metal material having a larger Schottky barrier than a material of a second gate electrode to be described later when Schottky contact is made on n-type GaAs. For example, as the material of the first gate electrode 14, Pt (platinum), Au
(Gold) or the like. The Schottky barrier potential of Pt is 0.9
eV, and the Au Schottky barrier potential is 0.96 eV.
It is.

[0050] Finally, as shown in FIG. 8 (D), CF ₄
The SiN film 6 and the SiN film 2 in the opening 13 are removed by plasma etching in a mixed gas of O ₂ and O ₂ . At this time, the SiO ₂ film 5 maintains its original shape without being substantially etched by plasma etching in a mixed gas of CF ₄ and O ₂ .

Further, a second gate electrode material is formed on the entire surface by sputtering. Then, a second gate electrode photoresist pattern (not shown) is formed, and the second gate electrode material is removed by dry etching except for the second gate electrode formation region above the n-type channel region 3. I do. Thereby, the second gate electrode 15 is formed on the upper surface and the periphery of the first gate electrode 14. As a material of the second gate electrode 15, a material that has a smaller Schottky barrier than the first gate electrode material when shot contact is made on n-type GaAs is used. For example, W (tungsten) is used as a material of the second gate electrode 15. The Schottky barrier potential of W is 0.65 eV. Note that a deposition and a lift-off method may be used as a method for forming the second gate electrode 15.

The second gate electrode 15 is formed so as to cover the upper surface and the periphery of the first gate electrode 14, and the second gate electrode 15 contacts the n-type channel region 3 on both sides of the first gate electrode 14. Is obtained.

FIG. 9 is an enlarged sectional view for explaining the operation of the field effect type semiconductor device of the second embodiment. As shown in FIG. 9, in the field-effect semiconductor device of the second embodiment, a second gate electrode 15 having a lower Schottky barrier than the first gate electrode 14 is provided around the first gate electrode 14. When a predetermined voltage is applied to the first gate electrode 14 and the second gate electrode 15,
Immediately below the first gate electrode 14 and the second gate electrode 1
5, a depletion layer 16 is formed. In this case, the depletion layer immediately below the first gate electrode 14 is the second gate electrode 15
Deeper than the depletion layer immediately below. The source
The current flowing between the drains is mainly due to the first gate electrode 14.
Is controlled by That is, the effective gate length for controlling the current flow in the n-type channel region 3 is determined by the width L3 of the depletion layer 16 formed below the first gate electrode 14.

Accordingly, the effective gate length can be reduced without reducing the contact area between the first and second gate electrodes 14 and 15 and the n-type channel region 3. At this time, an electric field between the gate and the source and between the gate and the drain is applied to both the first gate electrode 14 and the second gate electrode 15. As a result, it is possible to reduce the on-resistance while keeping the gate withstand voltage high, and it is possible to operate with high efficiency and a low power supply voltage. Also,
Since the width (the length in the channel length direction) of the first gate electrode 14 can be accurately controlled, the reproducibility of characteristics is high and the manufacturing yield is high.

In the first and second embodiments, the field effect type semiconductor device having an n-type channel region has been described. However, the present invention is also applicable to a field effect type semiconductor device having a p-type channel region. .

The present invention is not limited to MESFETs, but can be applied to various field effect semiconductor devices having a gate electrode formed on a channel region. For example, the present invention
It is also possible to apply to an EMT (high electron mobility field effect transistor).

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a field-effect semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view illustrating the method for manufacturing the field-effect semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a process sectional view illustrating the method for manufacturing the field effect semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the field-effect semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the field-effect semiconductor device according to the first embodiment of the present invention.

FIG. 6 is an enlarged cross-sectional view for explaining the operation of the field-effect semiconductor device according to the first embodiment.

FIG. 7 is a process sectional view illustrating the method for manufacturing the field-effect semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the field-effect semiconductor device according to the second embodiment of the present invention.

FIG. 9 is an enlarged cross-sectional view for explaining the operation of the field-effect semiconductor device according to the second embodiment.

FIG. 10 is a schematic sectional view showing the structure of a conventional field-effect semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semi-insulating GaAs substrate 3 n-type channel region 4 high-concentration n-type region 5 SiO ₂ film 2, 6 SiN film 7 a source electrode 7 b drain electrode 8 gate electrode 10 n ⁻ region 14 first gate electrode 15 second gate electrode

Claims (6)

[Claims] 1. A field effect semiconductor device having a gate electrode formed on a channel region of one conductivity type, wherein a part of the channel region below the gate electrode has a lower carrier concentration than the channel region or the one conductivity type. A field-effect semiconductor device, wherein a depletion layer forming region of a conductivity type opposite to that of the mold is formed so as to reach a predetermined depth from an interface with the gate electrode. 2. A first gate electrode having a Schottky barrier having a predetermined height is formed on a channel region, and the first gate electrode is disposed on at least one side of the first gate electrode in a channel length direction. A second gate electrode having an even lower Schottky barrier. 3. A depletion layer forming region having a carrier concentration lower than that of the channel region or a conductivity type opposite to the one conductivity type in a part of the one conductivity type channel region so as to reach a predetermined depth from the surface. Forming a gate electrode on the channel region including the depletion layer forming region. 4. The field effect semiconductor device according to claim 3, wherein said depletion layer forming region is formed by ion-implanting an impurity of a conductivity type opposite to said one conductivity type into said channel region. Manufacturing method. 5. The method according to claim 3, wherein the depletion layer forming region is formed by ion-implanting an impurity for inactivating carriers into the channel region. 6. A first gate electrode having a Schottky barrier having a predetermined height is formed on a channel region, and a first gate electrode is formed on at least one side of the first gate electrode in a channel length direction. Forming a second gate electrode having an even lower Schottky barrier.