JPS63226176A - Clamping circuit - Google Patents

Abstract

PURPOSE:To normally execute the subsequent clamp operation by detecting a state of an error of a frame synchronizing signal, when a normal frame synchronizing signal is not detected from a digital signal, and switching the potential in accordance with its detecting output. CONSTITUTION:A clamp level switching circuit 10 obtains an output A of a frame synchronizing signal detecting circuit 8 and an output B of the uppermost digit of an A/D converting circuit 4, selects one of three clamp potentials V0, V+ and V- and applies it to a clamping circuit 2. That is, when a normal frame synchronizing signal F is not detected, a state of an error of its frame synchronizing signal F is detected, and in accordance with its detecting output A, the clamp potential is switched automatically from the normal value, and when the synchronizing signal is detected correctly, the potential is reset to the normal clamp potential V0. In such a way, the frame synchronizing signal F is detected exactly.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention is applicable to positive polarity synchronization in which the synchronization signal is within the range of the video signal level, such as a high-definition TV signal band-compressed by a multiplex subsampling method. The present invention relates to a circuit for partially DC clamping the analog video signal before digital conversion, in order to digitally convert the analog video signal of the format and detect a synchronization signal from the digital signal.

(b) Conventional technology The high-definition TV signal mentioned above proposed by NHK is
For example, as introduced in "Nikkeiko L. Ktronics March 12, 1984 issue, pages 112-116,"
This is a positive polarity synchronous type analog video signal as described above. That is, the high-definition TV signal with , as shown in FIG.
H), and a frame synchronization signal (F) consisting of repeated pulses inserted in the 605th line and the 606th line with mutually opposite polarities.

FIG. 3 shows the main parts of a high-definition TV receiver that receives such a high-definition TV signal and reproduces high-definition video, and has the general configuration as follows.

That is, (1) is an input terminal for a high-quality video signal (hereinafter simply referred to as video signal), (2) is a clamp circuit that performs DC clamping using a clamp pulse, which will be described later, and (3) is a circuit that cuts unnecessary high-frequency components. (4) is an A/D conversion circuit that converts the output signal into an 8-bit parallel digital signal representing 256 gradations; (5) performs interframe interpolation, intrafield interpolation, and Digital processing unit that performs TCI decoding, etc. (6
) is a D/A converter that restores the output signal to an analog video signal and supplies it to the picture tube (7).

On the other hand, (8) obtains the most significant digit of the output signal of the A/D conversion circuit (4), detects the frame synchronization signal (F), and uses the signal (F) as a reference to detect the horizontal synchronization pulse (HP).
) and a frame synchronization signal detection circuit that creates vertical synchronization pulses (VP), (9) is a frame synchronization signal detection circuit that creates horizontal and vertical synchronization pulses (VP),
HP ) (V P ) is obtained and a preset clamp pulse (C
This is a clamp pulse generation circuit that generates P).

Here, the frame synchronization signal (F) of the detection circuit (8)
The detection operation will be explained in detail. That is, the low level and high level of the freight synchronization signal (F) (Fig. 4) correspond to the amplitude of the video signal of 25% (64/255) and 75% (
192/255), so when this synchronization signal (F) is A/D converted, the low level and high level become 01000000 and 11000, respectively.
It becomes 000. Therefore, when the frame synchronization signal (F) is correctly output from the A/D conversion circuit (4), the most significant bits "0" and "1" of the output signal of this circuit (4) are regularly output a specified number of times. This is used to detect the frame synchronization signal (F).

On the other hand, the clamp circuit (2) performs the following operation as preliminary processing for detecting such a frame synchronization signal. That is, a signal at a level of 50% of the amplitude of the video signal is inserted as a reference level for clamping at a predetermined position within the vertical blanking period of the video signal, and the clamp circuit (2) uses the aforementioned clamp pulse. (CP), the above reference level is set to the center of the input voltage range (R) of the A/D conversion circuit (4) by a clamp potential (vo).
It is designed to be clamped to.

Therefore, if the reference level (50%) is correctly clamped to the clamp potential (■.) as shown in (a) of FIG. 5(a), the frame synchronization signal (F) is Since it is located precisely within 25% to 75% of the voltage range (R), its high and low levels can be converted into the aforementioned digital values by the A/D converter circuit (4), and therefore the synchronizing signal (F ) is detected as described above. In addition, in an unstable state such as immediately after the start of reception, the level near the reference level (frame synchronization signal (F)
(in the range of 25 to 75%) is clamped to the clamp potential (vo), the synchronization signal (F)
cannot be converted to the regular digital value mentioned above, but the most significant digit is "1" and "0" repeatedly as in normal times, so the frame synchronization signal (F) can be detected in this case as well. .

However, if we consider a situation in which the video signal continues for several fields, for example, the entire screen becomes black or white, immediately after the start of reception, etc., before the frame synchronization signal (F) is detected. , in that state, the clamp pulse generation circuit (9
Since the clamp pulse (CP) from ) is not at the regular timing position, the black level or white level of the video signal will be clamped to the aforementioned predetermined clamp potential by this pulse (CP). That is, (b) in FIG. 5(a) is a case where the black level (0%) is clamped to the above-mentioned clamp potential (vo), and in this case, the frame synchronization signal (F) is within the input voltage range ( R
) (the broken line portion in the figure is cut by the limiter), the most significant digit of the digitized frame synchronization signal (F) is always “
1', making it impossible to detect the synchronizing signal (F).

(c) Problems to be solved by the invention The present invention has been made with the above-mentioned points in mind, and it is possible to reliably detect a frame synchronization signal even in a transient state such as immediately after the start of reception. The purpose is to ensure that subsequent clamping operations are performed normally.

Means for Solving Problems In the present invention, when a normal frame synchronization signal is not detected, the mode of error in the frame synchronization signal is detected,
The clamp potential is automatically switched from the normal value in accordance with the detection output, and returns to the normal clamp potential when the synchronization signal is correctly detected.

(E) Effect According to the above configuration, even in the above-mentioned transient state, the video signal is clamped so that the frame synchronization signal is always located at a predetermined level within the input voltage range of the A/D conversion circuit. , whereby the frame synchronization signal is accurately detected.

(f) Embodiment FIG. 1 shows an embodiment in which the present invention is applied to the above-mentioned high-quality TV receiver, and the same parts as in the conventional example shown in FIG. 3 are given the same numbers. Only the characteristic parts will be explained. That is, in this embodiment, (10) is a clamp level switching circuit provided according to the present invention, and this circuit connects the output (A) and A of the frame synchronization signal detection circuit (8).
Obtain the output (B) of the most significant digit of the /D conversion circuit <4>, select one of the three clamp potentials (Vo) (V+) (V-), and apply it to the clamp circuit (2). It has become.

That is, the clamp level switching circuit (10) has a D flip-flop (11) as shown in FIG. 2(a).
)(12), Antogame-1-(15)(16) and 1st
It consists of ~3rd analog switches (17), (18), and (19), and the frame period timing pulse (T
P) to latch the detection output (A).
When the Q output of the flop (12) is 11', the first analog switch (17) is closed and the normal clamp potential (v
o), the Q output is "0", and the other D flip latches the most significant digit output (B) of the A/D conversion circuit (4) with the timing pulse (TP). - When the Q output of the flop (11) is "0", the output of the AND gate (16) becomes 1'', closes the second analog switch (18), outputs the upper clamp potential (V+), and similarly During the D flip, the Q output of the flop (12) is “0” and the Q output of the D flip flop (11) is “1”.
”, the output of the AND gate (15) becomes “1”, closes the third analog switch (19), and outputs the lower clamp potential (V-). At that time, the D flip
One of the flops (12) is initialized at power-on so that its Q output is always set to "1" immediately after the start of reception.

Here, the regular clamp potential (vo) is set in exactly the same way as in the case of Fig. 3, but the upper clamp potential (V+
) is set to a potential higher than the normal clamp potential (vo) by the amplitude of the input video signal (Figure 5) (50%),
The lower clamp potential (V-) is set to a potential lower than the above amplitude.

Therefore, in the clamp circuit (2), if the black level of the input video signal is erroneously clamped to the normal clamp potential (vo) as shown in FIG. The most significant digit output (B
) is always "l", and at this time, the frame synchronization signal detection output (A) becomes "0°" indicating "no detection", and the output of the AND gate (15) becomes "1", so the third analog switch (19) is closed and the lower clamp potential (V-) is applied to the clamp circuit (2) instead of the above (vo). Therefore, the previous black level is now as shown in FIG. 5(a).
As shown in ()1), the frame synchronization signal (F) in the video signal is clamped to the above potential (V-).
/D conversion circuit (4) input voltage range (R) of 25 to 75
% and is detected by the frame synchronization signal detection circuit <8), whose detection output (A) becomes 1°' indicating "detection". Once the frame synchronization signal (F) is detected, a clamp pulse (CP) with regular timing is generated from the clamp pulse generation circuit (9), so this pulse <cp> causes the clamp circuit (2) to
now clamps the 50% reference level within the vertical blanking period. At this time, the normal clamp pressure (V, ) is applied to the clamp circuit (2) as described above, so the reference level is that V. Therefore, frame synchronization signal detection and clamping operations are performed normally thereafter. Furthermore, if the white level of the input video signal is erroneously clamped to the clamp potential (vo), the normal operating state is returned by once switching to the upper clamp potential (V+) in the same way.

By the way, the above embodiment is effective when the black level (0%) or white level (100%) of the input video signal is erroneously clamped as described above, but when the input video signal is 0 to 100%, If levels within 25% or between 75 and 100% are incorrectly clamped, malfunctions will occur. This is because, as shown in (d) of Fig. 5(b), the input video signal is
The level (L>) that is within 25% is incorrectly set to the clamp potential (v
o), the A/D conversion circuit (4)
The output (B) of the most significant digit does not always connect "1", for example, it becomes "0" in the black level part.Then, the timing pulse (TP) of the frame period mentioned above
is naturally asynchronous when the frame synchronization signal (F) is not detected, so the black level part is latched by the D flip-flop (11), and the Q output changes from "1" to 0. This is because there is a risk that it will reverse to ``.

Therefore, FIG. 2(b) shows another embodiment of a lamp level switching circuit that is also effective in such a case. In order to detect the error mode of the frame synchronization signal (F) using the output of the digit (B) and the output of the second digit from the most significant digit (C), the D flip-flop ( 11) and the inverter (13) are deleted, and a NOR gate (20), an AND gate (21), an RS clip-flop (22), and two D flip-flops (23) and (24) are newly provided.

That is, in this embodiment, the clamp circuit (2>
In this case, if a certain level (L) consisting of 0 to 25% of the input video signal is mistakenly clamped to the clamp voltage (■.) as shown in (d) of Figure 5(b), it will be clamped. Since the video signal level exists in the range of 25 to 100%, the most significant digit output (B) of the A/D conversion circuit (4) does not always connect 1 as mentioned above, but for example, During the period of the frame synchronization signal (F) (present in the range of 50 to 100%), the outputs (B) and (C) of the A/D conversion circuit (4) can both be 1. Once these outputs (B) and (C) become "1°", the output of the AND gate (20) becomes "1'', and at this time the output of the NOR gate (21) becomes O", so the RS flip - The flop (22) is set, and the Q output of the D flip-flop (23), which latches its Q output "1" with the aforementioned timing pulse (TP), becomes "1".

On the other hand, at this time, the output (A) of the frame synchronization signal detection circuit (8) is "0°" and the D flip-flop (12
) is also 0", so the AND gate (1
5) output becomes “1” and lower clamp potential (V-)
is selected. Immediately after that, even if the above-mentioned utilities (B) and (C) once become "0°'" and the RS flip-flop (22) is temporarily reset by the output of the NOR gate (21), the above-mentioned D flip-flop Since the Q output of the flop (23) is connected to "1", the frame synchronization Nobuo (F) is detected by the detection circuit (8) and the Q output of the D flip-flop (12) becomes 1". This state will be maintained until the situation is resolved. In this state, the level (L) of the input video signal is clamped to the lower clamp potential (V-) as shown in (e) of FIG. 5(b).

Furthermore, if a certain level within 75 to 100% of the input video signal is erroneously clamped to the clamp potential <vo), the output (B) (C) of the A/D conversion circuit (4)
) become "0", the output of the NOR gate (21) becomes "1" and the RS flip-flop (22) is reset, thereby selecting the upper clamp potential (V+). The operation is clear from the previous explanation.

In the circuit of FIG. 2(b), the D flip-flops (23) and (24) may be placed on the input side of the RS flip-flop (22>) instead of the positions shown.

(g) Effects of the Invention As described above, according to the clamp circuit of the present invention, part of the video signal is clamped to DC as pre-processing when A/D converting a positive synchronous type analog video signal. In this case, even if the clamping operation is performed at an incorrect level during a transitional period such as immediately after the start of reception, it can automatically shift to the normal clamping state. D conversion and synchronization signal detection performed by obtaining the output thereof can be accurately achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of a high-quality TV receiver employing the present invention, and FIGS. 2(a) and 2(b) are circuit block diagrams showing two different embodiments of the clamp level switching circuit. Fig. 3 is a block diagram of the main parts of a conventional high-definition TV receiver, Fig. 4 is a waveform diagram showing the synchronization signal part of a high-definition TV signal, and Fig. 5
Figures (a) and (b) are waveform diagrams for explaining the clamping operation. (2)...clamp circuit, (8)...frame synchronization signal detection circuit, (9)...clamp pulse generation circuit, <10)...clamp level switching circuit.

Claims (3)

[Claims] (1) Convert a positive synchronization type analog video signal in which the synchronization signal exists within the video signal level range to a digital signal, detect the synchronization signal from the digital signal to create a clamp pulse, and use this clamp pulse to In a circuit that clamps an analog video signal to a predetermined clamp potential, when a regular frame synchronization signal is not detected from the digital signal, the error state of the frame synchronization signal is detected and the circuit responds to the detection output. A clamp circuit configured to switch the clamp potential by using the clamp circuit. (2) The clamp circuit according to claim 1, wherein the error mode is detected by determining a code of the most significant digit of the digital signal. (3) Detection of the error mode is performed using the top two of the digital signals.
2. The clamp circuit according to claim 1, wherein the clamp circuit is determined by determining a digit code.