JPH07274038A - Clamping circuit - Google Patents

Abstract

PURPOSE:To perform improved DC reproduction even when distortion synchronized with horizontal synchronizing signals is superimposed on transmitted MUSE signals by the reflection of a cable or the like. CONSTITUTION:The MUSE signals are inputted thorough an amplifier 22, a capacitor 23 and the amplifier 25 to an A/D converter and the output of the A/D converter 25 is inputted to a clamp line level detection circuit 31. A clamping potential is set by detecting the reference level of a prescribed position in the loop of the circuit, a DC potential setting circuit 33, an adder 30, a D/A converter 29, a switch 28 and a resistor 27. However, since it is inaccurate when the distortion synchronized with horizontal synchronization is present, by monitoring the level of a frame line by the circuits 32 and 34, a correction voltage is generated and supplied to the adder 30 and the set clamping potential is corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit used in a MUSE receiver.

[0002]

2. Description of the Related Art A high-definition signal has a wide band and is converted into a band-compressed signal by the MUSE system before being transmitted. When this MUSE signal is decoded, direct current reproduction is performed.

The MUSE signal is transmitted in the signal format shown in FIG. As shown in the figure, 1 line is sampled at 480 points, 11 samples of which are horizontal synchronization (HD).
Is assigned to a period. The clamp operation is set to be performed during the HD period which is the horizontal synchronization signal.

FIG. 3 shows a clamp circuit for reproducing the DC component contained in the MUSE signal. The MUSE signal input to the input terminal 10 is input to the amplifier 15 via the amplifier 11 and the capacitor 12 in series. Amplifier 1
The output of 5 is an analog / digital (A / D) converter 16
Is input to and converted into a digital signal. The output of the A / D converter 16 is led to the output terminal 19 and also input to the clamp line level detection circuit 18.

The clamp line level detection circuit 18 includes the 563th line and 1125th line of the signal transmission format shown in FIG.
The clamp level defined for each 107-408 sample number on the line is detected. The detected clamp level of the clamp line level detection circuit 18 is input to the DC potential setting circuit 13. The DC potential setting circuit 13 compares the detected clamp level with the normal reference level (128/256), and the clamp level is the normal reference level (12
The clamp potential is set so as to be 8/256), and the clamp potential setting output is obtained.

Further, as shown in FIG. 4, the level (128
/ 256) also corresponds to the level of the reference phase point, which is the sixth sample point of the HD waveform. DC potential setting circuit 13
The clamp potential setting output of is a digital analog (D /
A) The converter 17 converts the analog signal. The output of the D / A converter 17 is supplied to one end of the switch 20,
The other end of the switch 20 is connected to the input end of the amplifier 15 via the clamp resistor 14. The switch 20 is controlled to be conductive in the HD period. As a result, the clamp voltage is set by the clamp resistor 14, and the output level of the amplifier 11 is set.

[0007] The clamp circuit described above performs direct current reproduction of the MUSE signal and enables decoding processing. In particular, non-linear processing such as non-linear compression / expansion, emphasis de-emphasis, etc. is performed like the MUSE signal,
In a system that restores a signal by giving complementary characteristics to both the transmitting and receiving sides, it is necessary to strictly manage the level at the receiver. Therefore, the clamp circuit is important.

[0008]

DISCLOSURE OF INVENTION Problems to be Solved by the Invention Distortion synchronized with the horizontal synchronizing signal due to reflection of a cable may be superimposed on the transmitted MUSE signal. In such a case, there is a problem that the conventional clamp circuit cannot perform good DC regeneration.

As shown in FIG. 5, the MUSE signal 563
If distortion is superimposed on the line and the 1125th line, an error occurs in the reproduced clamp level, and accurate DC reproduction cannot be performed. In particular, since the MUSE signal is subjected to the non-linear processing as described above, erroneous DC reproduction causes a great deterioration in image quality. For example, there is a problem that an offset occurs in the reproduced luminance signal and color difference signal, and the hue is converted. Therefore, an object of the present invention is to provide a clamp circuit that can perform excellent direct current reproduction at any transmission.

[0010]

SUMMARY OF THE INVENTION The present invention receives a television signal transmitted from a transmitting side with a reference DC level and a reference amplitude level set, detects the reference DC level, and detects the television signal. In the clamp circuit for reproducing the DC level, the means for detecting the reference amplitude level, obtaining an error amount thereof, and correcting the detected reference DC level in accordance with the error amount is provided.

[0011]

According to the above means, the direct current reproduction can be performed by the reference direct current level (clamp line) and the reference amplitude level, and the accurate direct current reproduction can be performed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, the MU input to the input terminal 21
The SE signal is supplied to the amplifier 22, the capacitor 23 and the amplifier 2.
4 is input in series to the A / D converter 25. Further, the output of the amplifier 22 is supplied to one end of the switch 28 via the capacitor 23 and the clamp resistor 27.
The MUSE signal digitized by the A / D converter 25 is
It is input to the clamp line level detection circuit 31 and the frame line level detection circuit 32.

The clamp line level detection circuit 31 includes the 563th line and 1125th line of the signal transmission format shown in FIG.
The clamp level defined for each 107-480 sample number on the line is detected. Clamp line level detection circuit 31 detection output (reference DC level detection output)
Is input to the DC potential setting circuit 33. The DC potential setting circuit 33 compares the clamp level with the regular reference level (128/256) and sets the clamp potential so that the clamp level becomes the regular reference level (128/256). This clamp potential is applied to the adder 30,
It is given to the input side of the amplifier 24 through the switch 28 and the resistor 27.

On the other hand, the frame line level detection circuit 32
Is a level defined for each 12-215 sample number of the first line and the second line of the signal transmission format shown in FIG. 2 (the specified level of the first line is 239/256, the specified level of the second line is 16/256) is detected and applied to the DC potential correction signal generation circuit 34. FIG. 4 shows a frame line pulse.

Here, the DC potential correction signal generating circuit 34 is
Detection level of frame pulse line (reference amplitude level)
, And the difference (error) from each reference level is averaged, inverted and output. This output is given to the adder 30 as a correction signal.

In the adder 30, the output of the DC potential correction signal generating circuit 34 and the output of the DC potential setting circuit 33 are added, and the added output is converted by the D / A converter 29 into analog Shingo. The switch 28 is supplied to the other end. The switch 28 becomes conductive each time the HD period arrives. As a result, the clamp operation is performed.

Now, when the receiving operation is performed in a state where the MUSE signal is not distorted, the level of the frame pulse line becomes zero. As a result, the DC potential supplied to the other end of the switch 28 is set by the output of the DC potential setting circuit 33.

Next, as shown in FIG. 5, when the clamp line is distorted, a positive deviation from the normal level occurs in all lines including the frame pulse line. The output of the DC potential setting circuit 33 at this time cannot be directly adopted. At this time, the output of the DC potential correction signal generation circuit 34 becomes a negative signal. The adder 30 adds the outputs of the DC potential setting circuit 33 and the DC potential correction signal generating circuit 34. Therefore, the clamp process acts to suppress the displacement of the direct current component of the input signal due to the distortion.

It is possible to configure the clamp circuit only with the signal of the DC potential correction signal generating circuit 34. Since this frame pulse line is also used as a reference signal for the transmission signal amplitude, it is difficult to actually realize it.

[0020]

As described above, according to the present invention,
Good DC reproduction can be performed even in the case where distortion synchronized with the horizontal synchronization signal is superimposed on the MUSE signal transmitted by reflection of the cable or the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a transmission format of a MUSE signal.

FIG. 3 is a diagram showing a conventional clamp circuit.

FIG. 4 is a waveform diagram shown for explaining a frame pulse line.

FIG. 5 is a waveform diagram shown for explaining a clamp line and a frame line when distortion is superimposed on the clamp line.

[Explanation of symbols]

22, 24 ... Amplifier, 23 ... Capacitor, 25 ... A / D
Converter, 27 ... Clamping resistor, 28 ... Switch, 29
... D / A converter, 30 ... Adder, 31 ... Clamp line level detection circuit, 32 ... Frame line level detection circuit, 33 ... DC potential setting circuit, 34 ... DC potential correction signal generation circuit.

Claims (2)

[Claims] 1. A clamp circuit for receiving a television signal transmitted from a transmitting side with a reference DC level and a reference amplitude level set, detecting the reference DC level, and reproducing the DC level of the television signal. 2. A clamp circuit, comprising: means for detecting the reference amplitude level, obtaining an error amount thereof, and correcting the detected reference DC level according to the error amount. 2. A reference level is set in the horizontal synchronizing signal period on the transmitting side, reference clamp level information is provided on the 563th and 1125th lines, and white and black amplitude level information is provided on the 1st and 2nd lines. A television receiver for receiving the inserted MUSE signal and reproducing a DC component based on the reference clamp level information, wherein the DC reproduction potential is set based on the reference clamp levels of the 563th line and the 1125th line. 1 means, a second means for setting a DC potential based on the amplitude level information of the first and second lines, and when reproducing the DC component of the MUSE signal using the output of the first means, A clamp circuit comprising: means for canceling a DC component error by the output of the second means.