JPH0685585B2 - Signal processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for an encoder that converts a color difference signal into a carrier color signal.

2. Description of the Related Art In recent years, video tape recorders (hereinafter abbreviated as VTRs) have been advanced in high image quality, and in the fields of broadcasting and professional VTRs, recording / reproducing by component signals has become the mainstream. However, peripheral devices often handle composite signals, and conversion with the component VTR is required. A signal processing circuit as an encoder circuit for converting a component signal into a composite signal has conventionally been constructed as shown in FIG. The color difference signals input from the terminals 20 and 24, for example, the RY signal and the BY signal are clamp circuits.
21,25 to the color signal carrier (3.579545MHz for NTSC)
Are balanced-modulated by balanced modulators (hereinafter abbreviated as BM) 22, 27, mixed by a mixer 28, and output to a terminal 29.

Problems to be Solved by the Invention However, in the above configuration, the clamp circuit 2
If it is not clamped reliably at 1,25, or if the clamp operation is not optimal due to the temperature characteristics of the clamp circuit, the temperature characteristics of the BM22,27, etc. That is, a so-called carrier leak occurs in which the color signal carrier leaks and is output even when the color difference signal is at 0 level, which causes the hue and saturation of the output color signal to change, resulting in a significant deterioration in image quality. Was.

Means for Solving the Problems In order to solve the above problems, an encoder circuit using the signal processing circuit of the present invention clamps a color difference signal by an automatic clamp circuit and then performs balanced modulation with a continuous wave signal 1. ,
The signal 2 obtained by inverting the phase of the continuous wave signal by 180 ° at a predetermined cycle and the balanced modulation output are further balanced-modulated, and the difference in the DC component of the obtained balanced modulation output at a predetermined cycle in a predetermined period is detected. Thus, the direct current level of the automatic clamp circuit is controlled. That is, the automatic clamp circuit, the first and second balanced modulators, the phase inversion circuit, the detection circuit, the first and second sample and hold circuits, the comparison circuit, the timing circuit, and the color subcarrier generation circuit. A color difference signal is input to the automatic clamp circuit, an output of the automatic clamp circuit is input to one input of the first balanced modulator, and a color signal is input to another input of the first balanced modulator. The carrier from the subcarrier generating circuit is input, the output of the first balanced modulator is output as a color signal, and at the same time, the input of the second balanced modulator is input, and the carrier is changed by the signal from the timing circuit. 180 ° every predetermined cycle
The phase inverting circuit for inverting the phase is input, the phase inverting circuit is input to the other input of the second balanced modulator, the output of the second balanced modulator is detected by the detection circuit, and The detection output is input to the first and second sample and hold circuits for alternately sampling and holding a predetermined section in a predetermined cycle by a signal from the timing circuit, and outputs of the first and second sample and hold circuits are input. The input information is compared with the comparison circuit, and the output information of the comparison circuit is fed back to the automatic clamp circuit to perform encoding without carrier leak.

Effect The present invention has the above-described configuration to detect the amount of carrier leak in the horizontal blanking interval of the color signal and control the automatic clamp circuit so as to minimize the amount of carrier leak. It is possible not to generate.

Example One example of the present invention will be described below. FIG. 1 is a block diagram of the present invention, FIG. 2 is a detailed block diagram of FIG. 1, and FIG. 3 is a waveform diagram of each part of FIG. Now, referring to FIG. The color signal e input from the input terminal 1 is optimally clamped by the automatic clamp circuit 2, is balanced-modulated with the color carrier from the color carrier generation circuit 6 by the balanced modulator BM3, and the output signal is output to the terminal 9. On the other hand, the color carrier wave is adjusted in phase by the phase adjustment circuit 15,
The phase inversion circuit 7 alternately inverts the phase based on the signal b from the timing circuit 8 and outputs it. Here, the phase inverting circuit 7 is composed of, for example, an inverter 16 and a switch 17. The output of the circuit 7 is input to the balanced modulator BM4 through the bandpass filter BPF18. On the other hand, the output signal of BM3 is input to the other input of BM4, and the signal f as a result of detecting the output of BM4 by the detection circuit 11 is output. Here, FIG. 3 shows from the case where the clamp DC level of the automatic clamp circuit is deviated to the time when it automatically becomes the optimum level. The signal f is sampled and held by the sample and hold circuits 12 and 13 by the signals c and d from the timing circuit 8,
The output is compared by the comparison circuit 14. Here, the signals c and d are alternately generated in the horizontal blanking period for each horizontal period (hereinafter abbreviated as H) as shown in FIG. Further, the signal b is a signal which repeats High and Low every 1H, whereby the switch 17 is switched. A horizontal cycle signal such as a is input to the terminal 10. Here, it is clear that the circuit blocks 11, 12, 13, 14 of FIG. 2 correspond to the detection circuit 5 of FIG.

Next, the operation of the present invention will be described. Automatic clamp circuit 2
Then, when the clamp level is slightly deviated as shown in FIG. 3, carrier leak occurs in the horizontal blanking interval of the output signal j, and as a result, the signal f is divided into direct current (hereinafter , DC) signals having different levels appear. This occurs because the phase inversion circuit 7 inverts the phase of the signal to be sent to BM4 every 1H, which is the point of the present invention. After the DC step is sampled and held by S / H 9 and 10, it is detected by the comparison circuit 14 and the automatic clamp circuit 2 is controlled so that the step disappears so that there is no difference in the DC level during the horizontal blanking period. Controlled by. That is, the color difference signal is encoded without carrier leakage.
Here, circuit examples of the automatic clamp circuit are shown in FIGS. FIG. 4 is for clamping by the FET 30 in the horizontal blanking period by the pulse from the timing circuit, and FIG. 5 is only for giving the output of the comparator 11 through the LPF. Various other circuits are conceivable, and a description thereof will be omitted.

Further, in the above embodiment, the phase adjusting circuit 15 and the BPF 18 are not directly related to the present invention and may be omitted. Further, the carrier generation circuit 6 is also unnecessary when the carrier is input from the outside, for example. In addition, the normal component color signal is an RY signal,
Since there are two channels such as BY signal, the present invention basically requires two circuits. However, it is desirable to share each block of FIGS. 6, 15, 7, 18, and 8 in FIG.

As described above, according to the present invention, after the color difference signal is clamped by the automatic clamp circuit, the continuous wave signal 1 and the balanced modulation are performed,
The signal 2 obtained by inverting the phase of the continuous wave signal by 180 ° at a predetermined cycle and the balanced modulation output are further balanced-modulated, and the difference in the DC component of the obtained balanced modulation output at a predetermined cycle in a predetermined period is detected. By controlling the DC level of the automatic clamp circuit based on the information obtained by the above, the color difference signals can always be clamped and encoded at the optimum DC level without carrier leakage, and therefore, in the component magnetic recording / reproducing apparatus. The effect is great.

[Brief description of drawings]

1 and 2 are block diagrams of an embodiment of the present invention, and FIG.
FIG. 4 is a waveform diagram of each part of FIG. 2, FIGS. 4 and 5 are concrete circuit diagrams of the automatic clamp circuit, and FIG. 6 is a block diagram of a conventional example. 2 ... Automatic clamp circuit, 3, 4 ... Balanced modulator, 5 ...
Detection circuit, 6 ... Color carrier generation circuit, 7 ... Phase inversion circuit, 8 ... Timing circuit, 18 ... Bandpass filter, 11 ... Detection circuit, 12, 13 ... Sample and hold circuit, 14 ... Comparison Circuit, 16 …… Inverter circuit, 17 …… Switch circuit.

Claims (8)

[Claims] 1. A color difference signal is clamped by an automatic clamp circuit and then balanced-modulated with a continuous wave signal 1. A signal 2 obtained by inverting the phase of the continuous wave signal by 180 ° at a predetermined cycle and the balanced modulation output. Is further subjected to balanced modulation, and the DC level of the automatic clamp circuit is controlled based on the information obtained by detecting the difference between the DC components of the obtained balanced modulation output for each predetermined period in the predetermined section. Signal processing circuit. 2. The signal processing circuit according to claim 1, wherein the predetermined period is one horizontal period signal section. 3. The signal processing circuit according to claim 1, wherein the predetermined section is a horizontal blanking section of the color difference signal. 4. An automatic clamp circuit, first and second balanced modulators, a phase inversion circuit, a detection circuit, first and second sample and hold circuits, a comparison circuit, a timing circuit, and a color. A sub-carrier generation circuit, a color difference signal is input to the automatic clamp circuit, an output of the automatic clamp circuit is input to one input of the first balanced modulator, and another output of the first balanced modulator is input. The carrier from the color subcarrier generating circuit is input to the input, the output of the first balanced modulator is output as a color signal, and at the same time, the input of the second balanced modulator is input to the input, and the carrier is timed. The signal from the circuit is input to the phase inverting circuit that inverts the phase by 180 ° at predetermined intervals, the output of the phase inverting circuit is input to the other input of the second balanced modulator, and the second balanced modulator is input. The output of the modulator is detected by the detection circuit. Then, the detected output is input to the first and second sample and hold circuits for alternately sampling and holding a predetermined section in a predetermined cycle by a signal from the timing circuit, and the first and second sample and hold circuits are provided. The carrier leak-free encoding is performed by inputting the output of the above into the comparison circuit for comparison, and by feeding back the output information of the comparison circuit to the automatic clamp circuit, the encoding without carrier leak is performed. The signal processing circuit according to the item. 5. The signal processing circuit according to claim 4, wherein the predetermined period is one horizontal period signal section. 6. The signal processing circuit according to claim 4, wherein the predetermined section is a horizontal blanking section of the color difference signal. 7. The signal processing circuit according to claim 4, wherein the color subcarrier is input to the phase inverting circuit after passing through the phase adjusting circuit. 8. The signal processing circuit according to claim 4, wherein the output of the phase inverting circuit is passed through a bandpass filter and then input to the second balanced modulator.