JPS6322393B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a nonvolatile semiconductor memory device that enables electrical rewriting.

[Technical background of the invention and its problems]

Recently, non-volatile semiconductor memory (E ² PROM), which is equipped with a floating gate and a control gate and whose stored contents can be electrically rewritten, has become popular as an alternative to conventional ultraviolet-erasable non-volatile semiconductor memory. This electrical rewriting of the memory is performed by injecting electrons into the floating gate through a thin oxide film by tunneling effect, or conversely by emitting electrons from the floating gate. Rewriting using tunnel current requires a higher voltage than that used for reading, but consumes almost no power. For this reason, a booster circuit is provided inside the chip to internally generate a high voltage different from that used for reading to perform writing and erasing. This is very easy for the user to handle, since it is only necessary to supply a single power supply of, for example, 5V externally.

An example of such an E ² PROM memory cell is shown in FIGS. 1a to 1d. a is a plan view, and b, c, and d are AA', BB', and CC' cross-sectional views of a, respectively. 1 is a p-type Si substrate, on which an n ⁺ drain 2 and source 3 are provided, a floating gate 5 is provided on the channel region with a thin gate oxide film 4 interposed therebetween, and a floating gate 5 is provided on the floating gate 5. A control gate 7 is overlapped with a gate oxide film 6 interposed therebetween. Reference numeral 8 denotes a rewriting region, which is constructed by extending the floating gate 5 through an extremely thin oxide film 9 on the n ⁺ layer on which the drain 2 extends.

The operating principle of this memory cell is as follows. First, in writing, the drain 2 and source 3 are kept at zero potential, a high voltage is applied to the control gate 7, and the potential of the floating gate 5 is increased by capacitive coupling. ⁺ Electrons from drain 2 are injected into floating gate 5. Erasing is performed by keeping the control gate 7 at zero potential and draining the drain 2.
A high voltage is applied to the floating gate 5 to emit electrons from the floating gate 5, contrary to the case of writing. In a state where electrons are injected into the floating gate 5, even if a read voltage of, for example, 5V is applied to the control gate 7, the memory cell will not turn on because its threshold voltage is high. In a state where no electrons are stored in the floating gate 5, when a read voltage is applied to the control gate 7, the memory cell is turned on. As a result, the memory cell becomes “1”,
“0” will be stored.

Such memory cells are arranged in a matrix in the row and column directions, for example, control gates are commonly connected in the row direction, and drains and sources are commonly connected in the column direction to form a memory cell array.

In order to boost the power supply voltage inside the chip to obtain a high voltage for writing and erasing, a booster circuit as shown in FIG. 2, for example, is used. This circuit uses the power supply V _CC
By applying the clocks φ 1 and _{φ 2 as} shown in _FIG . 3, the charges accumulated in the capacitor C ₁ from the load MOSFET- _Q
A high voltage is obtained at the output terminal by sequentially repeating the following operations: transferring the charge in capacitor C ₂ to the next capacitor C ₂ via MOSFET- _{Q 2} . It is something.

However, when rewriting is performed by applying a high voltage to a selected row of a memory cell array by combining such a booster circuit with an address decoder, the following problem arises. There is no problem in itself when the output of the address decoder becomes H level and a boosted high voltage is supplied to the control gate of the selected row. However, for the remaining unselected rows, the address decoder output is at L level, that is, the output stage thereof is in the on state, so current flows out from the booster circuit. Since the booster circuit shown in FIG. 2 utilizes the charge stored in the capacitor, its current supply capacity is extremely small. Therefore, if there is current outflow as described above in unselected rows, it becomes impossible to apply a sufficiently high voltage to the selected rows.

[Purpose of the invention]

The present invention has been made in view of the above points, and provides a non-volatile semiconductor memory device that can eliminate current outflow from a booster circuit and supply a sufficient boosted voltage to a memory cell array, thereby improving reliability. The purpose is to

[Summary of the invention]

The present invention provides a boosted voltage switching circuit between an address decoder and a memory cell array, supplies boosted voltage from the booster circuit only to selected rows of the memory cell array, and switches the boosted voltage to unselected rows. The present invention is characterized in that the current leakage to the output stage of the address decoder is prevented by disconnecting the address decoder.

〔Effect of the invention〕

According to the present invention, it is possible to realize a nonvolatile semiconductor memory device that eliminates unnecessary current outflow from an internal booster circuit with a small current supply capability and enables highly reliable rewriting operations.

[Embodiments of the invention]

FIG. 4 shows a memory configuration of an embodiment of the present invention. Memory cell array 11, address buffer 1
2. The basic configuration consisting of an address decoder 13, an input/output circuit 14 including an I/O buffer and a sense amplifier, a booster circuit 15 capable of generating a high voltage for rewriting, a control circuit 16 that controls these, etc. is conventional. It is similar to Memory cell array 11
is an arrangement of the memory cells described in FIG. 1, and the booster circuit 15 is a circuit as shown in FIG. The difference from the conventional one is that the address decoder 13
This is because a boost voltage switching circuit 17 is provided at the output end of the boost voltage switching circuit 17. This boosted voltage switching circuit 17 uses a high voltage (for example, V _H
= 20 V), and during reading, a read voltage approximately close to the power supply voltage is supplied to the selected row of the memory cell array 11 where the output of the decoder 13 is "1",
This circuit is designed to supply zero voltage to the remaining unselected rows in which the output of the decoder 13 is "0" without causing any current to flow out.

A specific example of the configuration of this boosted voltage switching circuit 17 is shown in FIG. FIG. 5 shows a unit circuit portion connected to one output terminal of the decoder 13,
A similar circuit will be provided at each output of the decoder 13. That is, the input terminal IN is a terminal connected to one output terminal of the decoder 13, and the output terminal
OUT is a terminal that supplies a selection signal voltage to the control gate of a selected row of the memory cell array 11. Between the input terminal IN and the output terminal OUT, an n-channel, D-type first MOSFET-Q _n1 controlled by a read/write control signal R/ is provided as a transfer gate. H is a terminal to which the output voltage of the booster circuit 15 is supplied, and between the output terminal OUT of the selection signal voltage and this boosted voltage supply terminal H, there is a p-channel, E-type
2MOSFET - Q _p1 and n channel, D type
3 MOSFET-Q _o2 are connected in series. No.
The substrate of 2MOSFET-Q _p1 is these MOSFET-
It is connected to the connection node N ₁ of Q _p1 and Q _o2 , and the
The gate of 3MOSFET-Q _o2 is controlled by the potential of the output terminal OUT. On the other hand, the output terminal OUT of the selection signal voltage is n-channel, E type.
MOSFET-Q _o3 and p channel, E type
It is connected to the input end of a CMOS inverter consisting of MOSFET-Q _p2 , and the gate of the second MOSFET-Q _p1 is controlled by the potential of the output node _N2 of this CMOS inverter. this
On the ground side of the CMOS inverter, an n-channel, E-type fourth MOSFET-Q _o4 is installed in series, and on the power supply Vcc side, a p-channel, E-type fifth MOSFET-P _p3 is installed in parallel. The gates of these fourth and fifth MOSFETs Q _o4 and Q _p3 are controlled by a complementary signal /W of the read/write control signal R/.

The operation of this switching circuit is as follows. In addition, n-channel, D type MOSFET-Q _o1 , Q _o2
Threshold is -3V, n channel, E type
The threshold values for MOSFETs Q _o3 and Q _o4 are 1V, and the threshold values for P channel and E type MOSFETs Q _p1 , Q _p2 and Q _p3 are -1 V.

First, the write mode will be explained. At this time, /W=5V and R/=0V are applied, and the boosted voltage V _H =20V is supplied to the terminal H from the booster circuit 15. Now, if the input terminal 1N is 5V, that is, the decoder output is "1", the output terminal OUT
A potential of approximately 3V lower than the gate potential of MOSFET-Q _o1 by its threshold value appears. This biases MOSFET Q _o2 to node N ₁
Approximately 6V appears. On the other hand, since /W=5V and MOSFET-Q _o4 is on and Q _p3 is off,
The CMOS inverter works, and the potential of the output terminal OUT is inverted by this CMOS inverter, and its output node _N2 becomes zero potential, which causes
MOSFETQ _p1 turns on. This results in a node
The potential of N ₁ appears at the output terminal OUT. Output end
Since the potential of OUT further changes in the direction of deepening the ON state of MOSFETs Q _o2 and Q _p1 , V _H =20V is obtained at the output terminal OUT due to this feedback operation. MOSFET-Q _o1 turns off when the potential at the output terminal OUT rises to 3V or higher, so no current flows from the increased output terminal OUT to the input terminal IN.

In this way, the voltage V _H =20V at the output terminal OUT is applied to the control gate of the selected row of the memory cell array 1, and writing is performed in response to data input from the input/output circuit 14.

Next, the decoder output is “0”, that is, the input terminal IN is
In the case of 0V, since R/=0V, the output terminal
OUT does not rise, the output node N ₂ of the CMOS inverter is 5V, the MOSFET-Q _p1 is kept off, and the boosted voltage V _H is not transmitted to the output terminal OUT. Therefore, no current flows from the booster circuit 15 to the decoder output stage with the output "0".

Next, the read mode will be explained. At this time, change this to the output terminal depending on the 5V and 0V at the input terminal IN.
It is necessary to send it to OUT. In the read mode, the booster circuit 15 does not work as a booster circuit, and the voltage is connected to the terminal H by the MOSFETs shown in FIG. 2 - Q _R , Q ₁ , Q ₂ ,
...The voltage minus the voltage drop due to Qn is supplied. Also, at this time, R/=5V, so
If the input terminal IN is 5V, this will appear at the output terminal OUT without voltage drop across MOSFET-Q _o1 , and if the input terminal IN is 0V, this will appear at the output terminal OUT.
R/W=5V turns on MOSFET-Q _o4 , Q _p3
is off, the output node _N2 of the CMOS inverter is 5V regardless of the potential of the output terminal OUT.
As a result, the MOSFET-Q _p1 is turned off, and the voltage at the terminal H does not appear at the output terminal OUT.

As a result, 5V is supplied to the control gate of the row selected by the decoder 13, and information reading is performed.

FIG. 6 shows an embodiment in which the switching circuit of FIG. 5 is stabilized in a transient state. The difference from Fig. 5 is that an n-channel, D-type MOSFET-Q _o5 is inserted between the node N ₁ and the MOSFET-Q _p1 , and an n-channel, D-type MOSFET is inserted between the node N ₁ and the power supply V _CC . This is because MOSFET-Q _o6 was inserted.

The basic operation of this circuit is the same as in Figure 5, so
Only the functions of MOSFETs Q _o5 and Q _o6 will be explained. When changing from read mode to write mode, terminal H becomes a boosted voltage V _H = 20V, and input terminal IN becomes 5V.
When the voltage changes from to 0V, the MOSFET-Q _o1
When is turned on, DC current flows from terminal H to input terminal IN. MOSFET-Q _o5 suppresses the outflow of DC current during this transient state. As a result, when the input terminal 1N becomes 5V, the output terminal
It is possible to prevent the boosted voltage V _H supplied to OUT from decreasing.

Also, when changing from write mode to read mode, the potential of terminal H does not drop sufficiently, for example.
If the voltage is around 10V, it will appear at the output terminal OUT and cause malfunction. At this time
MOSFET-Q _o6 is controlled by the output node N ₂ of the CMOS inverter to be in the on state, and even if the potential of terminal H is high, the potential of node N ₁ is controlled by the power supply V _CC
By clamping the high potential to the output terminal
Work so as not to let it go out.

In addition, in the write mode when V _H = 20V,
The output node _N2 of the CMOS inverter is 0V, therefore
Since MOSFET-Q _o6 is in the off state, the terminal H
No current flows from the MOSFET to the power supply V _CC through this MOSFET-Q _o6 . Furthermore, in the embodiments shown in FIGS. 5 and 6, a MOSFET-Q _o1 as a transfer gate is provided between the input terminal IN of the switching circuit, that is, the output terminal of the decoder and the output terminal OUT of the selection signal voltage. This can be omitted. This is because when the decoder output is "1" and a boosted potential is output to the selection signal voltage output terminal OUT, even if this is directly supplied to the decoder output stage, there will be no current outflow in the normal decoder output stage configuration, and the decoder This is because when the output is "0", MOSFET-Q _p1 blocks the supply of the boosted potential to the selection signal voltage output terminal OUT.

As described above, according to the present invention, it is possible to prevent current outflow from the booster circuit and improve the reliability of an E ² PROM equipped with an internal booster circuit.

[Brief explanation of drawings]

1A to 1D are diagrams showing the structure of an example of an electrically rewritable nonvolatile semiconductor memory cell, FIG. 2 is a diagram showing an example of an internal booster circuit of an electrically rewritable nonvolatile memory, and FIG. 4 is a diagram showing the memory configuration of an embodiment of the present invention, FIG. 5 is a diagram showing a specific configuration example of the boost voltage switching circuit of FIG. 4, and FIG. 6 is a diagram showing the clock waveform. It is a figure which shows the modification. DESCRIPTION OF SYMBOLS 11... Memory cell array, 12... Address buffer, 13... Address decoder, 14... Input/output circuit, 15... Boost circuit, 16... Control circuit, 17... Boost voltage switching circuit, Q _o1 ... First MOSFET, Q _p1 ...
2nd MOSFET, Q _o2 … 3rd MOSFET, Q _o3 , Q _p2 …
CMOS inverter, Q _o4 … 4th MOSFET, Q _p3 …
5th MOSFET.

Claims (1)

[Claims] 1. A memory cell array in which electrically rewritable non-volatile semiconductor memory cells with floating gates and control gates are arranged, an address decoder, an input/output circuit, a booster circuit capable of generating a high voltage for rewriting, and a booster circuit of this booster circuit. A memory device comprising at least an integrated switching circuit which selects an output according to the output of the address decoder and supplies the output to the memory cell array, the switching circuit comprising:
a first conductive channel, a D-type first conductive channel, which is directly connected to the output end of the address decoder or whose gate is provided with a read/write control signal;
a second conductive channel connected in series between an output terminal of a selection signal voltage connected via one MOSFET and an output terminal of the selection signal voltage and the output terminal of the booster circuit, a second E-type MOSFET, and the selection signal voltage; A first conductive channel whose gate is controlled by a signal voltage, a third D-type MOSFET, and a first conductive channel whose gate is controlled by a signal voltage;
CMOS inverter that controls the gate of 2MOSFET and the ground end side of this CMOS inverter
A first conductive channel connected in series with the MOSFET and controlled by a complementary signal of the read/write control signal; a fourth E-type MOSFET connected in parallel with the MOSFET on the power supply side of the CMOS inverter and controlled by a complementary signal of the read/write control signal; a second conductive channel gated by a second conductive channel of type E;
1. A nonvolatile semiconductor memory device, characterized in that a unit circuit including 5 MOSFETs is provided at each output terminal of the address decoder.