JP3011415B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: Object of the Invention (Field of Industrial Application) The present invention relates to an electrically rewritable nonvolatile semiconductor memory device, and more particularly to an improvement in a data latch circuit for rewriting data.

(Prior Art) Various types of non-volatile semiconductor memory devices (EPROMs) capable of electrically rewriting data are known. A device that electrically performs data writing and performs data erasing by ultraviolet irradiation is known as a UVEPROM, and a device that performs both data writing and erasing electrically is known as an EEPROM.

FIG. 6 is a block diagram showing a main configuration of an EPROM in which data can be rewritten in a page mode. The memory cell array 11 is configured such that electrically rewritable memory cells are arranged in a matrix. The memory cell is the seventh
The FETMOS type in which a thin gate insulating film is provided over the entire channel region as shown in the figure, and the FLOTOX type in which a thin gate insulating film is provided as a partially rewritten region in the region overlapping the source region 32 as shown in FIG. Good. Memory cell array 11
An address buffer 12, an address latch 13, and an address decoder 14 are provided to select the address. These circuits select a word line. On the bit line side, there are data input buffers 15,
A data latch 16 for temporarily holding the fetched data and a bit line voltage control circuit 17 for applying a boosted potential to a bit line according to the data are provided. Also, the sense amplifier 18 for reading data from the memory cell array 11 is used.
And a data output buffer 19.

FIG. 9 is a specific circuit configuration example of the data latch 16 and the bit line voltage control circuit 17 shown in FIG. Data latch 16 includes a two inverters INV _1, INV _2, is constituted by a flip-flop including a transfer gate M ₁ between the feedback transfer gates M ₂ and an input-output line (I / O line). The bit line voltage control circuit 17 is controlled by the output RING of the ring oscillator and the write control signal PROG, and includes a charge pump circuit composed of MOS transistors M ₄ and M ₃ and a capacitor M _3.
It constituted by n-channel MOS transistor M ₇ for Rubitto line driver to drive the.

FIG. 10 is a timing chart for explaining the circuit operation. The main operation will be described. Data is transferred from the outside to the I / O line, and the latch signals LATCH and ▲ ▼ become “L” level and “H” level, respectively. You. Thereafter, when the control signal PROG becomes “H” level, the output RING of the ring oscillator passes through the NAND1 and drives the charge pump circuit. Thus the boosted voltage Vpp is applied to the gate of the driving MOS transistor M _7, MOS transistors M for the drive
_The voltage potential Vpp applied to the drain ₇ is supplied to the bit line BL.

The specific operation principle of data writing in a memory cell is as follows.
There are various methods depending on the memory cell configuration, and there are various methods even with the same memory cell configuration. Although the detailed description is omitted,
Basically, one of the following three operations is used. First
The second is a method using a tunnel current between a substrate or source / drain and a floating gate, the second is a method using a hot channel injection by flowing a large channel current, and the third is
Uses avalanche decay at the drain junction. In each case, a boosted potential higher than a normal power supply voltage is used.

As described above, since data writing in the EPROM requires a potential higher than the power supply potential, a bit line voltage control circuit is required between the data latch and the memory cell array as described with reference to FIGS. The circuit configuration becomes very complicated when the gate circuits attached thereto are included. This makes EPROM even more difficult to integrate.

(Problems to be Solved by the Invention) As described above, in the conventional EPROM in which the data can be rewritten in the page mode, the configurations of the data latch and the bit line voltage control circuit are complicated. There was a problem that was preventing.

An object of the present invention is to provide an EPROM which solves such a problem and simplifies the configuration of the data latch section to enable higher integration.

[Structure of the Invention] (Means for Solving the Problems) The EPROM according to the present invention has a data latch and a bit line voltage control circuit which are virtually integrated, in other words, the bit line voltage control circuit is integrated with the data latch. It is characterized in that it is configured to be incorporated.

More specifically, the data latch of the EPROM according to the present invention includes a first CMOS inverter having an input terminal connected to a data input / output line via a first transfer gate, and a first CMOS inverter. A basic configuration is a flip-flop having an input terminal connected to the output terminal, an output terminal connected to the bit line, and a second CMOS inverter which is fed back to the first CMOS inverter via a second transfer gate. I do. Here, a normal power supply potential is used for the first CMOS inverter, but a writing high potential higher than the normal power supply potential is used for the second CMOS inverter. Then, the p-channel MO of the second CMOS inverter
A D-type n-channel MOS transistor for driving a bit line whose gate is connected to the output terminal is interposed between the source terminal of the S transistor and the aforementioned high potential for writing.

(Operation) In the data latch of the present invention, when the output of the second CMOS inverter connected to the bit line is at the “H” level, the p-channel MOS transistor of the inverter is on and the p-channel MOS transistor is turned on. A high potential is supplied to the bit line via a bit line driving D-type n-channel MOS transistor connected in series. According to the present invention, since the bit line voltage control circuit is built inseparably from the data latch, the circuit configuration becomes very simple, and the EPROM can be highly integrated as compared with the related art.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 3 shows a schematic configuration of an EPROM of one embodiment. Third
Parts corresponding to those in the figure are denoted by the same reference numerals as in FIG.
As is apparent from comparison with FIG.
The portions of the data latch 16 and the bit line voltage control circuit 17 in the figure are integrated with the data latch 20.

FIG. 1 shows a specific configuration example of the data latch 20 portion. p-channel MOS transistor Q ₂ and the n-channel MOS
First and CMOS inverter 1 formed by transistors Q _5, p-channel MOS transistor Q ₄ and the n-channel MOS transistor Q ₆ second CMOS inverter 2 composed of
Are the main parts constituting the flip-flop of the data latch. The first input terminal of the CMOS inverter 1 is connected to the I / O line via a first transfer gate Q _5.
The output terminal of the second CMOS inverter 2 is connected to the bit line BL, and also the first through the second transfer gate Q ₁
It is fed back to the input terminal of the CMOS inverter 1. First
The source terminal of the p-channel MOS transistor Q ₂ of the CMOS inverter 1 is connected to the power supply voltage Vcc. Second CMOS
The source terminal of the p-channel MOS transistor Q ₄ of the inverter 2 is connected to D-type, via a MOS transistor Q ₃ of the n-channel to the boosted potential Vpp. This n-channel MOS
Transistor Q ₃ are gate connected to the second output terminal of the CMOS inverter 2, which is a p-channel MOS transistor Q
Used together with ₄ for bit line drive.

The operation of the data latch thus configured will be described next with reference to FIG. When “H” level data appears on the I / O line and the control signals ▲ ▼ and LATCH become “H” level and “L” level, respectively, the MOS transistors Q ₅ and Q ₄ are turned on, and the MOS transistors Q ₂ and Q ₆ turns off. Therefore the second
The output terminal rises CMOS inverter 2, to further the gate of the MOS transistor Q ₃ by the potential rise is positively biased, MOS transistor Q _3, via the Q ₄ bit lines BL
Is supplied with a boosted potential Vpp. In this state, when the control signal ▼ is at the “L” level and the LATCH is at the “H” level, the flip-flop is disconnected from the I / O line and is in a state of latching data.

Next, when the I / O line data is at “L” level, the control signal LAT
When CH goes to “L” level and ▲ ▼ goes to “H” level, the MOS transistors Q ₂ and Q ₆ are turned on, Q ₄ and Q ₅ are turned off, and the source potential Vss (= 0 V) of the MOS transistor Q ₆ is Supplied to line BL. In this state, the control signal ▲
When ▼ goes low and LATCH goes high, the flip-flop is disconnected from the I / O line and latches data.

Thus, according to this embodiment, the bit latch voltage control circuit is built in the data latch, and the number of constituent elements is very small as apparent from FIG. Therefore, high integration of the EPROM is achieved.

FIG. 4 shows a data latch according to another embodiment of the present invention. Parts corresponding to those in FIG. 1 are denoted by the same reference numerals as in FIG. 1, and detailed description is omitted. In this embodiment, for example,
“H” level write potential VbitH lower than Vpp and “L”
A configuration example in the case of supplying to the level side intermediate potential VbitL bit line BL is shown. In addition to the configuration of FIG. 1, a first n-channel MOS for applying an "H" level write potential VbitH to a bit line between a flip-flop and a bit line BL.
A transistor Q _10, "L" the second n-channel MOS transistor Q ₁₂ for providing an intermediate potential VbitL level side bit lines are provided. Writing potential here "H" level side, the threshold voltage of the MOS transistor Q ₁₀ as Vth1, a VbitH <Vpp-Vth1, an intermediate potential of "L" level side, the threshold of the MOS transistor Q ₁₂ Value voltage is Vth2,
VbitL <Vpp <Vth2. The 1 MOS transistor Q ₁₀ of "H" level side write potential VbitH is applied to the drain,
The source is connected to the bit line BL, and the gate is connected to the output terminal of the second CMOS inverter 2 of the flip-flop. The second MOS transistor Q ₁₂ is D of the drain is for protection
Type, through the n-channel MOS transistor Q ₁₁ bit lines
BL, the source is supplied with the “L” level side intermediate potential VbitL, and the gate is connected to the output terminal of the first CMOS inverter 1 of the flip-flop. These MOS transistors Q ₁₀ , Q ₁₁ and Q ₁₂ have a large current driving capability. Power supply potential Vcc is applied to the gate of the MOS transistor Q ₁₁ for protection. Also the second CMO of the flip-flop
N-channel MOS transistor Q ₈ for also protecting the n-channel MOS transistors Q ₆ side of the S inverter 2 are provided. The MOS transistor source voltage Vcc to the gate of Q ₈ is being given. Still more between the bit line BL and a data latch, n-channel MOS transistor Q ₁₃ which is controlled by the write control signal ▲ ▼ as a data rewrite only when the "H" level is provided. This MOS transistor Q
₁₃ shall have the same degree of current drivability of the MOS transistor Q ₁₀ to Q _12.

The operation of the data latch in this embodiment is basically the same as in the previous embodiment. When “H” level data appears on the I / O line, the second CMOS inverter 2 of the flip-flop
Output goes to "H" level, thereby MOS transistor Q ₁₀ is turned on, the "H" level side of the write potential VbitH is supplied to the bit line BL. In the opposite case the data from the first output of the CMOS inverter 1 of the flip-flop is at "H" level, MOS transistor Q ₁₂ is turned on, "L" level side intermediate voltage VbitL is applied to the bit line BL.

When MOS transistor Q ₁₀ is turned on "H" level side write potential VbitH is supplied to the bit line BL, "H" level side write potential VbitH the MOS transistor is a MOS transistor for protection transfer to Q ₁₂ Q ₁₁ is blocked by, surface breakdown in MOS transistor Q ₁₂ is prevented. Similarly, when the second in the CMOS inverter 2 of the flip-flop, transfer to MOS transistor Q ₆ boosted potential Vpp is prevented by protection MOS transistor Q _8, preventing surface breakdown of a MOS transistor Q ₆ Is done.

According to this embodiment, the same effect as the previous embodiment can be obtained. The configuration of this embodiment is also effective when the boosted potential Vpp is used as the write potential on the “H” level side.

FIG. 5 shows a data latch of an embodiment in which the configuration of FIG. 4 is slightly modified. In this embodiment, the MO shown in FIG.
Portions corresponding to the S transistors Q ₁₁ and Q ₁₂ are arranged closer to the bit line BL than the MOS transistor Q ₁₃ . That is, the interior than the MOS transistors Q _13, during data rewriting to the "L" level of the intermediate potential VbitL control signal ▲ ▼ is controlled by the n-channel MOS transistor Q ₁₆ an intermediate potential VbitL is applied to the drain bit Connected to line BL. In addition, between the bit line BL and the ground potential Vss, a D type
n-channel MOS transistor Q ₁₄ and the E-type, n-channel MOS
Transistor Q ₁₅ are connected in series. Gates of the MOS transistors Q ₁₄ is supplied with the power supply voltage Vcc, the reset control signal RESET is supplied to the gate of the MOS transistor Q _15.

The operation of the data latch of this embodiment is basically the same as that of FIG. In the data latch of FIG.
When the “L” level side intermediate potential VbitL is supplied to the bit line, this intermediate potential cannot be higher than the power supply voltage Vcc. Since the gate of the MOS transistor Q ₁₂ is limited by Vcc, also with higher than Vcc as the intermediate potential VbitL is is not supplied to the bit line. On the other hand, in this embodiment, the flip-flop and the independent MO
Since using S transistor Q _16, by selecting the intermediate potential VbitL the "L" level side, it is possible to supply a higher intermediate potential than Vcc to the bit line BL. Further, the bit line BL can be set to Vss when the reset control signal RESET is set to the “H” level and reading and writing are not performed.

In the above embodiment, an E-type MOS transistor is used for the transfer gate between the data latch and the input / output line I / O. However, a D-type MOS transistor may be used for the transfer gate, and LATCH may be used as a control signal. Good. In this way, the data latch
The signal "▼" is not required. Also, ▲ ▼
A transfer gate may be configured in which an E-type MOS transistor controlled by LATCH and a D-type MOS transistor controlled by LATCH are connected in parallel. In this way, the data on the I / O line can be transferred to the data latch without lowering the threshold value.

[Effects of the Invention] As described above, according to the present invention, by integrating a write potential generation unit such as a boosted potential into a data latch, a conventional bit line voltage control circuit is provided separately from the data latch. The number of constituent elements is greatly reduced as compared with that of the conventional one, so that high integration of the EPROM becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a data latch section of an EPROM according to one embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation thereof, and FIG. 3 is a diagram showing a schematic configuration of the EPROM. FIG. 4 is a diagram showing a configuration of a data latch unit of an EPROM of another embodiment, FIG. 5 is a diagram showing a configuration of a data latch unit of an EPROM of another embodiment, and FIG. FIG. 7 and FIG. 8 are diagrams showing an example of a memory cell configuration of the EPROM, FIG. 9 is a diagram showing an example of the configuration of the data latch and bit line potential control circuit thereof, FIG. 10 is a timing chart for explaining the operation. 11 …… Memory cell array, 12 …… Address buffer, 13
…… Address latch, 14 …… Address decoder, 15 ……
Data input buffer, 18 Sense amplifier, 19 Data output buffer, 20 Data latch, 1st CM
OS inverter, 2 ... second CMOS inverter, Q3 ... D
Type, n-channel MOS transistor, I / O ... data input / output line, BL ... bit line, Vcc ... power supply potential, Vpp ... boosted potential, VbitH ... "H" level side write potential, VbitL ...
“L” level side intermediate potential.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 17/00

Claims (5)

(57) [Claims] 1. A memory cell array in which electrically rewritable memory cells are arranged, a first p-channel MOS transistor having a source supplied with a power supply voltage, and a first n-channel MOS having a source grounded.
A first CMOS inverter having a first input terminal and a first output terminal formed by transistors sharing the drain and gate of each other, and a second p-type transistor having a source applied with a voltage higher than the power supply voltage. A second n-channel MOS transistor and a source grounded
A second input terminal and a second input terminal each configured to share a drain and a gate of the channel MOS transistor.
A second CMOS inverter having a first output terminal and a second input terminal, wherein the first input terminal is electrically connected to the second output terminal, and the second input terminal is electrically connected to the first output terminal. A data latch circuit configured to control a voltage of a bit line of the memory cell array; a data input buffer; an I / O line electrically connected to the data input buffer; and a first input terminal A transfer gate provided between the power supply voltage and a source of the second p-channel MOS transistor; and a transfer gate provided between the source of the second p-channel MOS transistor and a voltage higher than the power supply voltage. A MOS transistor for controlling the source voltage of the P-channel MOS transistor. 2. A memory cell array in which electrically rewritable memory cells are arranged, an address buffer, an address latch, and an address decoder for selecting an address of the memory cell array, and reading bit line data of the memory cell array. Amplifier and a data output buffer, and a data input buffer and a data latch for providing rewrite data to a bit line of the memory cell array, wherein the data latch has an input terminal through a first transfer gate. A first CMOS inverter connected to an output line, a second CMOS having an output terminal connected to a bit line
An inverter, and a flip-flop having a second transfer gate connected between an output terminal of the second CMOS inverter and an input terminal of the first CMOS inverter, and a p-channel MOS transistor of the second CMOS inverter A non-volatile semiconductor memory device, wherein a write potential higher than a power supply potential is applied to the source terminal through a D-type n-channel MOS transistor having a gate connected to the output terminal. 3. A memory cell array in which electrically rewritable memory cells are arranged; an address buffer, an address latch and an address decoder for selecting an address of the memory cell array; and a bit line data of the memory cell array. Amplifier and a data output buffer, and a data input buffer and a data latch for providing rewrite data to a bit line of the memory cell array, wherein the data latch has an input terminal through a first transfer gate. A first CMOS inverter connected to the output line, and a second CMOS inverter whose output terminal is fed back to the input terminal of the first CMOS inverter via the second transfer gate.
A boosted potential is applied to a source terminal of a p-channel MOS transistor of the second CMOS inverter via a D-type n-channel MOS transistor having a gate connected to the output terminal. And the second CM is provided between the flip-flop and the bit line.
A first driving n-channel driven by the output of the OS inverter to supply a write potential on the “H” level side to the bit line
A MOS transistor; and a second driving n-channel MOS transistor driven by the output of the first CMOS inverter and supplying an intermediate potential on the “L” level side to the bit line. Non-volatile semiconductor memory device. 4. An n-channel MO of said second CMOS inverter.
4. The semiconductor device according to claim 3, wherein a D-type n-channel MOS transistor having a power supply potential applied to a gate for protecting the n-channel MOS transistor is interposed between the S transistor and the output terminal. Non-volatile semiconductor memory device. 5. A D-type n-channel MOS transistor having a power supply potential applied to a gate for protecting the n-channel MOS transistor is interposed between the second driving n-channel MOS transistor and the bit line. The nonvolatile semiconductor memory device according to claim 3, wherein: