JPH02249197A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the number of constitutional elements and to attain high integration by assembling a write potential generating part for boosting potential etc., integrally in a data latch. CONSTITUTION:The nonvolatile semiconductor memory is comprised in such a way that a bit line voltage control circuit is assembled in the data latch. In other words, the data latch of a volatile semiconductor memory device(EPROM) is provided with a first CMOS inverter 1 whose input terminal is connected to a data input/output line via a first transfer gate. Also, a flip-flop whose input terminal is connected to the output terminal of the first CMOS inverter 1 and whose output terminal is connected to a bit line and is provided with a second CMOS inverter 2 fed back to the first CMOS inverter 1 via a second transfer gate is employed as fundamental constitution. In such a way, it is possible to simplify the constitution of a data latch part, and to expedite higher integration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application)] The present invention relates to an electrically rewritable nonvolatile semiconductor memory device, and more particularly to an improvement of a data latch circuit section for data rewriting.

(Prior Art) Various types of nonvolatile semiconductor memory devices (EFROM) are known that allow electrical data rewriting. Those that write data electrically and erase data using ultraviolet irradiation are known as UVEPROMs, and those that write and erase data electrically are known as EEPROMs.
Also known as ROM.

FIG. 6 is a block diagram showing the main structure of an EPROM that allows data to be rewritten in page mode. The memory cell array 11 includes electrically rewritable memory cells arranged in a matrix. The memory cell is
As shown in FIG. 7, the FETMOS type has a thin gate insulating film provided over the entire channel region, and as shown in FIG. Either FLOTOX type may be used. In order to select an address in the memory cell array 11, an address buffer 12. An address latch 13 and an address decoder 14 are provided. On the bit line side where the word line is selected by these circuits, there is a data input buffer 15 . A data latch 16 that temporarily holds captured data and a bit line voltage control circuit 17 that applies a boosted potential to the bit line according to the data are provided. Furthermore, a sense amplifier 18 and a data output buffer 19 are provided for reading data from the memory cell array 11.

FIG. 9 shows a specific circuit configuration example of the data latch 16 and bit line voltage control circuit 17 portions of FIG. 6. The data latch 16 has two inverters INV+ and INV
2, feedback transfer gate M2 and input/output line (■
10 lines) and a flip-flop including a transfer gate M1. The bit line voltage control circuit 17 includes MO3I transistors M4. M3 and a charge pump circuit consisting of a capacitor M3, and a bit line driving n-channel MOS transistor M7 that is driven by the charge pump circuit to drive the bit line BL.
Consisted of.

FIG. 10 is a timing diagram for explaining the circuit operation. To explain the main operation, data is transferred from the outside to the J10 line, and the latch signals LATCH and LATC are
H is ``L'' level respectively.

This becomes the data latch 16 by going to “H” level.
captured and retained. After that, the control signal PROG becomes "H" level, so that the output RING of the ring oscillator passes through NANDI and drives the charge pump circuit. As a result, the boosted potential Vl)I) is used for driving and operating M
A boosted potential Vl)p applied to the gate of the OS transistor M7 and applied to the drain of the driving MOS transistor M7 is supplied to the bit line BL.

The specific operating principle of data writing in a memory cell differs depending on the memory cell configuration, and there are various methods even with the same memory cell configuration. Although detailed explanation thereof will be omitted, basically one of the following three operations is used. The first is the substrate or source.

Due to tunnel current between drain and floating gate,
The second method uses hot electron injection by flowing a large channel current, and the third method uses avalanche collapse at the drain junction. In both cases, a boosted potential higher than the normal power supply voltage is used.

In this way, writing data in an EPROM requires a potential higher than the power supply potential, as shown in FIG.

As explained with reference to FIG. 9, a bit line voltage control circuit is required between the data latch and the memory cell array, and the circuit configuration becomes extremely complicated if the gate circuits attached thereto are included. This makes it difficult to further increase the integration density of EPROMs.

(Problems to be Solved by the Invention) As described above, in the conventional EPROM that allows data to be rewritten in page mode, the configuration of the data latch and bit line voltage control circuit section is complicated, and this makes it difficult to achieve high integration. There was a problem that was blocking it.

The present invention solves these problems and provides an EPROM that has a simplified configuration of the data latch section and enables higher integration.
The purpose is to provide

[Structure of the Invention] (Means for Solving the Problems) The EPROM according to the present invention virtually integrates the data latch and the bit line voltage control circuit, in other words, the bit line voltage control circuit is integrated into the data latch. It is characterized by being configured in a built-in state.

More specifically, the data latch of the EPROM in the present invention includes a first CMOS whose input terminal is connected to a data input/output line via a first transfer and an agate.
an inverter, an input terminal is connected to the output terminal of the first CMOS inverter, an output terminal is connected to the bit line, and a second CMOS inverter is fed back to the first CMOS inverter via a second transfer gate. The basic configuration is a flip-flop having a CMOS inverter. Here, a normal power supply potential is used for the first CMOS inverter, and a high potential for writing, which is higher than the normal power supply potential, is used for the second CMOS inverter. And this second
A D-type n-channel MOS transistor for bit line driving, whose gate is connected to the output terminal, is interposed between the source terminal of the p-channel MOS transistor of the CMOS inverter and the aforementioned high potential for writing.

(Function) In the data latch of the present invention, when the output of the second CMOS inverter connected to the bit line is at H" level,
The p-channel MO5) transistor of the inverter is on, and a high potential is supplied to the bit line via a D-type n-channel MOS transistor for bit line driving connected in series to this p-channel MOS transistor. According to the present invention, since the bit line voltage control circuit is inseparably incorporated into the data latch, the circuit configuration becomes extremely simple, and higher integration of the EPROM becomes possible than in the past.

(Example) The present invention will be explained in detail below.

FIG. 3 shows a schematic configuration of an EPROM of one embodiment. Parts corresponding to those in FIG. 3 are given the same reference numerals as in FIG. 3. As is clear from a comparison with FIG. 3, in this embodiment, the data latch 16 and bit line voltage control circuit 17 in FIG. 3 are integrated into the pig latch 20.

FIG. 1 shows a specific configuration example of the data latch 20 portion. The first C composed of p-channel MO3I-transistor Q2 and n-channel MOS transistor Q5
A MOS inverter 1, a second CMOS inverter 2 constituted by a p-channel MOS transistor Q4, and an n-channel MOS transistor Q6 are the main parts constituting a data latch flip-flop. 1st CMO
The input terminal of the S inverter 1 is connected to the I10 line via a first transfer gate Q. □Second commercial
The output terminal of the OS inverter 2 is connected to the bit line BL, and is also connected to the first C through the second transfer gate Q1.
It is fed back to the input terminal of MOS inverter 1. 1st
The source terminal of p-channel MOS transistor Q2 of CMOS inverter 1 is connected to power supply potential Vcc. The source terminal of the p-channel MOS transistor Q4 of the second CMOS inverter 2 is connected to the boosted potential vpp via a D-type, n-channel MOS transistor Q3. This n-channel MOS transistor Q3 has its gate connected to the output terminal of the second CMOS inverter 2, and is used together with the p-channel MOS transistor Q3 for bit line driving.

The operation of the data latch configured in this way will be explained next with reference to FIG. "H" level data appears on the I10 line, and the control signal LATCH.

When LATCH goes to "H" level and "L" level respectively, MOS) transistors Q5 and Q4 turn on, MOS)
Ransistor Q2. Q6 is turned off. Therefore, the second commercial
The output terminal of OS inverter 2 rises, and this potential rise further biases the gate of MOS transistor Q3 positively, so that MOS transistor Q3. A boosted potential Vl)I) is supplied to the bit line BL via Q4.

In this state, the control signal LATCH is at the 'L' level, and the LA
When TcH goes to the "H" level, the flip-flop is disconnected from the I10 line and enters a state in which data is latched.

Next, when the I10 line data is at “L” level, the control signal L
When ATCH becomes "L" level, when ATCH becomes "H" level, MOS transistors Q2 and Q6 turn on, Q,
, Q are turned off, and the source potential Vss (-OV) of the MOS transistor Q6 is supplied to the bit line BL. In this state, the control signal LATCH is at “L” level LATCH
When becomes “H” level, the flip-flop becomes I10
It is disconnected from the line and the data is latched.

Thus, according to this embodiment, the bit line voltage control circuit is built into the data latch, and as is clear from FIG. 9, the number of constituent elements is greatly reduced. Therefore, the EPROM can be highly integrated.

FIG. 4 is a data latch of another embodiment of the present invention.

Components corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. In this embodiment, for example, the boosted potential Vl
) is lower than “H” level side write potential Vbitll
A configuration example is shown in which an intermediate potential V bjLL on the "L" level side is supplied to the bit line BL. In addition to the configuration shown in FIG. 1, between the flip-flop and the bit line BL,
First n-channel MOS) transistor Q for applying write potential Vbitll on the “H” level side to the bit line
+o and a second n-channel MOS transistor Q1□ for applying an intermediate potential V bjtL on the "L" level side to the bit line. Here, the "H" level side write potential is set to VbitH<Vpp-V, where the threshold voltage of MOS transistor Q+o is Vthl.
tlll te is present, the intermediate potential on the “L” level side is M
If the threshold voltage of the os transistor Q1□ is V th2, then V bitL<Vpp-Vth2. The drain of the first MOs transistor Q1o is supplied with the "H" level side write potential VbHII, and the source is supplied with the bit 1
fJBL and the second flip-flop on the gate.
The output terminal of the CMOS inverter 2 is connected thereto.

The drain of the second MOS) transistor Q12 is connected to the bit line BL via a protective D-type n-channel MOS transistor Qz, the "L" level side intermediate potential V bitL is applied to the source, and the gate has a ripple voltage. The output terminal of the first CMOS inverter of the flop is connected. These MOS) transistors Q,. , Qll and Q
Reference numeral 12 has a large current drive capability. The gate of the protective MOS transistor Q++ is connected to the power supply voltage VC.
C is given. Also the second CMO of flip-flop
A protective n-channel MOS transistor Q8 is also provided on the n-channel MOS transistor Q6 side of the S inverter 2. The power supply voltage Vcc is also applied to the gate of this MOS transistor Q8. Furthermore, between the bit line BL and the data latch, there is further provided an n-channel MOS transistor Q13 which is controlled by a write control signal READ which becomes "H° level" only when data is rewritten.This MOS transistor QI3 is MOS) transistor Q, + o-Q l
It is assumed that the current driving capacity is about the same as that of 2.

The operation of the data latch in this embodiment is basically the same as in the previous embodiment. When “H” level data appears on the +10 line, the output of the second CMOS inverter 2 of the flip-flop becomes “H” level, and this causes the MOS
) The transistor Q+o is turned on, and the write potential VbitH on the "H" level side is supplied to the bit line BL. In the case of reverse data, since the output of the first CMOS inverter 1 of the flip-flop is at "H" level, MOS transistor Q+2 is turned on, and the "L" level side intermediate potential V
bjtL is applied to bit line BL.

When transistor Q+o (MOS) is turned on and the H" level side write potential VbitH is supplied to the bit line BL, the transfer of the "H" level side write potential Vbitn to the MOS transistor Q12 is transferred to the protection MOS transistor Q1. □ prevents surface breakdown in the MOS transistor Q1□.Similarly, at this time, the second CMOS inverter 2 of the flip-flop transfers the boosted potential Vl)I) to the MOS transistor Q6. is blocked by the protection MOS transistor Q8,
Surface breakdown in MOS transistor Q6 is prevented.

This embodiment also provides the same effects as the previous embodiment. The configuration of this embodiment is also effective when the boosted potential Vl)I) is used as the write potential on the "H" level side.

FIG. 5 shows a data latch of an embodiment in which the configuration of FIG. 4 is slightly modified. In this example, the MO in FIG.
The part corresponding to S transistor QllIQ+'2 is MO
S) It is arranged closer to the bit line BL than the transistor QI3. That is, an n-channel MOS whose drain is supplied with an intermediate potential VbitL, which is controlled by a control signal READL which becomes an intermediate potential VbitL of "L" level at the time of data rewriting, is internally provided by the MOS transistor Q+3.
A transistor Q+6 is connected to the bit line BL. Further, a D type, n channel MOS transistor Q14 and an E type, n channel MOS transistor QCs are connected in series between the bit line BL and the ground potential VS2.

MOS) The gate of transistor QI4 is connected to the power supply voltage VCC.
is applied, and a reset control signal RESET is applied to the gate of the MOS transistor Q+5.

The operation of the data latch in this embodiment is basically the same as that in FIG. In the data latch in Figure 4, “
When supplying the L” level side intermediate potential VbitL to the bit line, this intermediate potential cannot be made higher than the power supply voltage Vec.MOS) When the gate of transistor Q12 is connected to VC
Since it is limited by C, the intermediate potential V bitL is set as VC
This is because even if a voltage higher than C is used, it will not be supplied to the bit line. On the other hand, in this embodiment, although a MOS transistor Q16 independent from the flip-flop is used, by selecting the intermediate potential V'bitL on the "L" level side, an intermediate potential higher than VCC is applied to the bit line B.
It can be supplied to L. In addition, the reset control signal RE
When SET is set to "H" level and no reading or writing is performed, the bit line BL can be set to Vss.

In the above embodiment, an E-type MOS transistor is used for the transfer gate between the data latch and the input/output line 110, but it is also possible to use a D-type MOS transistor for this transfer gate and use LATCH as the control signal. If you do this, the data latch section will have an L
The ATCH signal is no longer needed. Also, LATCH
E type MOS transistor and LAT controlled by
A transfer gate may be configured in which 0247MO5) transistors controlled by CH are connected in parallel. In this way, the data of the 10 lines can be transferred to the data latch without the threshold value dropping.

[Effects of the Invention] As described above, according to the present invention, by integrally incorporating a write potential generation section such as a boosted potential into the data latch, it is possible to improve the conventional method in which a bit line voltage control circuit is provided separately from the data latch. The number of constituent elements is significantly reduced compared to that of conventional EPROMs, thus making it possible to achieve high integration of EPROMs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a data latch section of an EPROM according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining its operation, and FIG. 3 is a diagram showing a schematic configuration of the EPROM. , FIG. 4 is a diagram showing the configuration of a data latch section of an EPROM of another embodiment, FIG. 5 is a diagram showing a configuration of a data latch section of an EPROM of another embodiment, and FIG. 6 is a diagram of a conventional EPROM. 7 and 8 are diagrams showing an example of the memory cell configuration of the EPROM, FIG. 9 is a diagram showing an example of the configuration of the data latch and bit line potential control circuit, and FIG. FIG. 10 is a timing diagram for explaining the operation. 11... Memory cell array, 12... Address buffer, 13... Address latch 14... Address decoder, 15... Data input buffer, 18... Sense amplifier, 19... Data output buffer, 2o...
- Data latch, 1...first CM'OS inverter, 2...second CMOS inverter, Q3...D type. n-channel MO5I-transistor, Ilo...data input/output line, BL...bit line, Vee...power supply potential, Vl)I)...boosted potential, Vbitll..."H
"Level side write potential, V bitL..."L" level side intermediate potential. Applicant's agent Patent attorney Takeshi Suzue

Claims (5)

[Claims] (1) A memory cell array in which electrically rewritable memory cells are arranged; an address buffer, an address latch, and an address decoder for selecting an address of the memory cell array; and a memory cell array for reading bit line data of the memory cell array. It includes a sense amplifier, a data output buffer, and a data input buffer and a data latch that supply rewrite data to the bit line of the memory cell array, and the data latch applies a potential different from a power supply potential necessary for data rewriting to the bit line. 1. A nonvolatile semiconductor memory device comprising a flip-flop having a built-in bit line voltage control circuit. (2) A memory cell array in which electrically rewritable memory cells are arranged; an address buffer, an address latch, and an address decoder for selecting an address of the memory cell array; and a memory cell array for reading bit line data of the memory cell array. A sense amplifier, a data output buffer, and a data input buffer and data latch that provide rewritten data to the bit line of the memory cell array, the data latch having an input terminal connected to the data input/output line via a first transfer gate. the first CMO connected to
a flip-flop having an S inverter, a second CMOS inverter having an output terminal connected to a bit line, and a second transfer gate connected between an output terminal of the second CMOS inverter and an input terminal of the first CMOS inverter. A write potential higher than the power supply potential is applied to the source terminal of the p-channel MOS transistor of the second CMOS inverter via a D-type n-channel MOS transistor whose gate is connected to the output terminal. A nonvolatile semiconductor memory device characterized by: (3) A memory cell array in which electrically rewritable memory cells are arranged; an address buffer, an address latch, and an address decoder for selecting an address of the memory cell array; and a memory cell array for reading bit line data of the memory cell array. A sense amplifier, a data output buffer, and a data input buffer and data latch that provide rewritten data to the bit line of the memory cell array, the data latch having an input terminal connected to the data input/output line via a first transfer gate. the first CMO connected to
The S inverter is configured by a flip-flop having a second CMOS inverter whose output terminal is fed back to the input terminal of the first CMOS inverter via a second transfer gate, and a p-channel MOS transistor of the second CMOS inverter. A boosted potential is applied to the source terminal of the second C through a D-type n-channel MOS transistor whose gate is connected to the output terminal, and between the flip-flop and the bit line, the second C
a first driving n-channel MOS transistor that is driven by the output of the MOS inverter and supplies a write potential on the "H" level side to the bit line; and a first drive n-channel MOS transistor that is driven by the output of the first CMOS inverter and supplies a write potential on the "L" level side to the bit line. A second driving n-channel MOS that supplies an intermediate potential of
A nonvolatile semiconductor memory device characterized by comprising a transistor. (4) n-channel MO of the second CMOS inverter
This n-channel MO is connected between the S transistor and the output terminal.
4. The nonvolatile semiconductor memory device according to claim 3, further comprising a D-type n-channel MOS transistor to which a power supply potential is applied to the gate for protecting the S transistor. (5) A D-type n-channel MOS transistor to which a power supply potential is applied to the gate for protecting the n-channel MOS transistor is interposed between the second driving n-channel MOS transistor and the bit line. The nonvolatile semiconductor memory device according to claim 3, characterized in that: