JPS6069897A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the reliability of an E<2>PROM provided with an internal boosting circuit by providing a boosted voltage switching circuit between an address decoder and a memory cell array and supplying a boosted voltage in the boosting circuit only to a selected row of the memory cell array and cutting off the boosted voltage to non-selected rows to prevent a current from being flowed out to the output stage of the address decoder. CONSTITUTION:A boosted voltage switching circuit 17 is provided in the output terminal of an address decoder 13, and a high voltage (for example, VH=20V) obtained by boosting a power source voltage is supplied to a selected row, for which the output of the decoder 13 is ''1'', of a memory cell array 11 in case of rewrite, and a read voltage approximating the power source voltage is supplied there in case of read; and zero voltage is supplied to left non-selected rows, for which the output of the decoder 13 is ''0'', without flowing-out of the current.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a nonvolatile semiconductor memory device that enables electrical rewriting.

[Technical background of the invention and its problems]

Recently, non-volatile semiconductor memory IJ (B
2FROM) has become popular in place of the conventional ultraviolet erasable nonvolatile semiconductor memory. This electrical rewriting of the memory is performed by injecting electrons into the floating gate through a thin oxide film by tunneling effect, or conversely by emitting electrons from the floating gate. Rewriting using tunnel current requires a higher voltage than that used for reading, but it consumes almost no power.

For this reason, a booster circuit is provided inside the chip to internally generate a high voltage different from that used for reading to perform writing and erasing.

This is very easy for the user to handle, since a single power supply of, for example, 5V can be applied externally.

An example of such an E2PR/OM memory cell is shown in Fig. 1 (at to (d). (a) is a plan view, and (b)
, (C), (dl is (al's A - A/
, B-B', and CC' sectional views. 1 is p
A type Si substrate, on which an n+ drain 2 and source 3 are provided, a floating gate 5 is provided in the channel region, via a thin gate oxide UX 4, and a gate oxide film 6 is further provided on the floating gate 5. A control gate 7 is superimposed therebetween. Reference numeral 8 denotes a rewriting region, in which a floating gate 5 is inserted via an ultra-thin oxide film 9 on the n layer in which the drain 2 is extended.
It is constructed by extending.

The operating principle of this memory cell is as follows. First, writing is performed by keeping the drain 21 and source 3 at zero potential, and applying a high voltage to the control gate 7 to close the floating gate 5 by capacitive coupling.
The potential of the ultra-thin oxide film 9 is increased in the rewrite area 8.
Electrons from the n+ drain 2 are injected into the floating gate 5 through the n+ drain 2. For erasing, the control gate 7 is kept at zero potential, a high voltage is applied to the drain 2, and electrons from the floating gate 5 are emitted, contrary to the case of writing. In a state where electrons are injected into the floating gate 5, even if a read voltage of, for example, 5V is applied to the control gate 7, the memory cell will not turn on because its threshold voltage is high. When no electrons are stored in the floating gate 5, when a read voltage is applied to the control gate 7, the memory cell is turned on. This makes the memory cell
I 11 , 16 @ will be memorized.

Such memory cells are arranged in a matrix in the row and column directions, for example, control gates are commonly connected in the row direction, and drains and sources are commonly connected in the column direction to form a memory cell array.

In order to boost the power supply voltage inside the deep to obtain a large voltage for writing and erasing, a booster circuit as shown in FIG. 2, for example, is used. This circuit uses electric power source V. By applying locks φ1 and φ2 as shown in FIG.
By sequentially repeating the operations of transferring the charge to the next capacitor C1 via MOSFET-Q, , and transferring the charge of this capacitor C1 to the next capacitor C3 via MOSFET-Q2, a high voltage is obtained at the output terminal. It is something.

However, when rewriting is performed by applying a high voltage to a selected row of a memory cell array by combining such a booster circuit with an address decoder, the following problem arises. There is no problem in itself when the output of the address decoder becomes H level and the boosted high voltage is supplied to the control gate of the selected row. However, for the remaining unselected rows, the address decoder output is at L level, that is, the output stage thereof is in the on state, so current flows out from the booster circuit. Since the booster circuit shown in FIG. 2 utilizes the charge stored in the capacitor, its current supply capacity is extremely small. Therefore, if there is a current outflow as described above in unselected rows, it becomes impossible to apply a sufficiently high voltage to the selected rows.

[Purpose of the invention]

The present invention has been made in view of the above points, and provides a nonvolatile semiconductor memory device that eliminates current outflow from a booster circuit and can supply a sufficient boosted voltage to a memory cell array, thereby improving reliability. The purpose is to

[Summary of the invention]

The present invention provides a boosted voltage switching circuit between an address decoder and a memory cell array, and supplies the boosted voltage from the booster circuit only to a selected row of the memory cell array.
The first feature of the non-selective feature is that the boosted voltage is cut off to prevent N and R from flowing to the output stage of the address decoder.

〔Effect of the invention〕

According to the present invention, it is possible to realize a nonvolatile semiconductor memory device that eliminates unnecessary current outflow from an internal booster circuit (which has a small current supply capacity) and enables highly reliable rewriting operations.

[Embodiments of the invention]

FIG. 4 shows a memory configuration of an embodiment of the present invention. Memory cell array 4+1. Address/-f-f-f2, address decoder 13, I/O/(input/output circuit 14 including sofa and sense amplifier, booster circuit 15 capable of generating high voltage for rewriting, and control circuit for controlling these) The basic configuration consisting of 16, etc. is the same as the conventional one.The memory cell array 4+7 is an arrangement of the memory cells explained in FIG. 1, and the booster circuit j5 is a circuit as shown in FIG. 2. The difference is that the address decoder j3
This is because a boost voltage switching circuit 17 is provided at the output end of the boost voltage switching circuit 17. This boosted voltage switching circuit 17 uses a high voltage (for example, VH = 20 V) which is the boosted power supply voltage for rewriting, and a read voltage close to the power supply voltage for reading, so that the output of decoder j3 is 111. This circuit is designed to supply a selected row of a certain memory cell array 11, and supply zero voltage to the remaining unselected rows for which the output of decoder J3 is 10W without causing any current outflow.

A concrete example of the construction of this boosted voltage switching circuit 17 is shown in FIG. FIG. 5 shows a unit circuit portion connected to one output terminal of the decoder 13.

A similar circuit will be provided at each output of the decoder 3. That is, the input terminal IN is a terminal connected to one output terminal of the decoder 3, and the output terminal OUT is a terminal that supplies a selection signal voltage to the control gate of a selected row of the memory cell array 11. Between this input terminal IN and output terminal OUT.

The first Mo8FET-Qpt of the n-channel type I) controlled by the exposure/write control signal R/W
is provided as a transfer gate.

11 is a terminal to which the output voltage of the booster circuit 15 is supplied, and between the output terminal OUT of the selection signal voltage and this boosted voltage supply terminal H, there is a p-channel, E type 27<2 Mo8
FF3 T-Qp 1 and n channel, m of D9 Eve
3 Mo8FET-Q, , are connected in series.

@2 Mo8FET-Q, ps substrate is these Mo8F
It is connected to the connection node N1 of ET-Qpt + Qnt, and the gate of the third Mo8 FET-Q (12 is controlled by the 7! position of the output terminal OUT.On the other hand, the output of the selection signal voltage The end OUT'T is an n-channel, E type Mo8FET-QrtS and a p-channel, E
The second Mo8FET-Q is connected to the input terminal of a CMOS inverter of the type Mo8IT-Q, and is connected to the input terminal of a CMOS inverter consisting of the second Mo8FET-Q, by the potential of the output node N of this CMOS inverter.
The gate of pl is controlled.

On the ground side of this CMOS inverter, an n-channel, E-type fourth Mo8 FET-Qn 4 is provided in series, and on the power supply VCC side, a p-channel, E-type fifth Mo8 FET-Pp is provided in parallel. I was being treated,
These 4th. 5th Mo8 FET-Qna, Q
The gate of p s is controlled by the complementary signal π/W of the read/write control signal B/W. The operation of this switching circuit is as follows.

In addition, n-cha J, /L/, D type MO8FET -
Ql 1゜Qn2 threshold is -3y, n channel, E
Type MO8FET-Qns, Qna threshold is IV, P channel, B tie 7' Mo8FET-Qp
The threshold value of t 1 Qpt −Qps is −1v.

First, to explain the write mode, in this case π/
W-OV and R/W=5V are applied, and a boosted voltage VH=20V is supplied to the terminal H from the booster circuit f5. Now, if the input terminal IN is 5V, that is, the decoder output is M11, the output terminal OUT is Mo8FET-Qn.
Potential 3V lower than the gate potential of t by that threshold
appears.

As a result, Mo 8 F ET -Qn 2 is biased, and about 6≈ appears at node N1. On the other hand, π
Since /W=0■, MOS FET-Qn4 is on and Qps is off, the CMOS inverter works, and the potentials of the outputs Mi and lOUT are inverted by this CMOS inverter and the output node N, becomes zero potential, which turns on MOS FET-Qpt. As a result, the potential of the node N1 appears at the output terminal OUT. The potential of the output iM OUT is further MOSFE
Since T-Q5□2 and Q,1 change in the direction of deepening the on state, v1□=20 V is obtained at the output terminal OUT by this feedback operation. MO8]? ]
0T-Qo turns off when the potential at the output terminal OUT rises to 3V or higher, so no current flows from the increased output i71 (XJT to the IN side).

In this way, the voltage VI (-20v) at the output terminal OUT is applied to the control gate of the selected row of the memory cell array 1,
Writing is performed in response to data input from the input/output circuit t4.

Next, the decoder output is l □ l, that is, the input terminal IN is Ov
Since Y%/W=OV, the output terminal OUT
does not rise, the output node N of the CMOS inverter is 5V, MO8FET-Qpt is kept off, and the boosted voltage VH is not transmitted to the output terminal OUT.

Therefore, no current flows from the booster circuit 15 to the decoder output stage of the output 101.

Next, the read mode will be explained. At this time, it is necessary to output this to the output terminal OUT according to the 5V and QV of the input terminal IN. In the read mode, the booster circuit 15 does not work as a booster circuit, and the voltage is supplied to the terminal H from the MOS shown in FIG.
FET-QR.

The voltage obtained by subtracting the voltage drop due to Q, , Q, , . . . Qn is supplied. Also at this time, R/W=sV
Therefore, if the input terminal IN is 5V, MO8F E
At T -Qn t, this appears at the output terminal OUT without any voltage drop, and when the input terminal IN is OV, this appears at the output terminal OUT.
appears in MOSFET by R,/W=5V
-Q, is on and Qps is off, so CM
The output node N of the OS inverter is 5V regardless of the potential of the output terminal OUT, so that the MO8FET
-Qp t is in the off state, and the terminal H Tit [
No IE appears at the output terminal OUT.

As a result, 5V is supplied to the control gate for the row selected by the decoder 13, and information reading is performed.

FIG. 6 shows an embodiment in which the switching circuit of FIG. 5 is stabilized in a transient state. The difference from FIG. 5 is that node N1
An n-channel, D-type MO8FE T-Q n * is inserted between the node N1 and the power supply vcc, and an n-channel, D-type MOS is inserted between the
This is because F ET -Q n 6 was inserted.

The basic operation of this circuit is the same as in Figure 5, so the MOS
Only the functions of FID'I'-0, ns, and Qna will be explained. When changing from the read mode to the write mode, the voltage at the terminal II increases to 1 voltage Vn = 20 V, and when the input terminal IN changes from 5 to OV, -
When the instantaneous MOS FET-QnI turns on, a direct current flows from the terminal H to the input terminal Ill. MO8FBT-Qn' suppresses the outflow of the direct current in this transient state. As a result, the input terminal ZN
It is possible to prevent the boosted voltage ■H supplied to the output terminal OUT from decreasing when the voltage becomes 5■.

Also, when changing from write mode to read mode,
If the potential of the terminal H does not drop sufficiently and is, for example, about IOV, this will be outputted to the output terminal OUT, causing malfunction. At this time, MOSFET -Qn is CMOS
It is turned on under the control of the output node N2 of the inverter, and even if the potential of the terminal H is high, the potential of the node N is clamped to the power supply voc, thereby preventing a high potential from being outputted to the output terminal OUT.

In addition, in the write mode of VH=20V, CMO
The output node Nt of the S inverter is OV, therefore MOSF
Since ET-Qn is in the off state, no current flows from the terminal H through MOSFET-Qn to the power supply VCa.

As explained above, according to the present invention, current leakage from the booster circuit is prevented, and the E"FRO equipped with an internal booster circuit is
The reliability of M can be improved.

[Brief explanation of drawings]

Figure 1 is a diagram showing the structure of an example of an electrically rewritable non-volatile semiconductor memory cell, and Figure 2 is a diagram showing an example of an internal booster circuit of a non-volatile memory that can be changed at the !T notice. , FIG. 3 is a diagram showing the clock waveform, FIG. 4 is a diagram showing the memory configuration of an embodiment of the present invention, and FIG.
A diagram showing a specific configuration example of the boost voltage switching circuit shown in FIG.
The figure shows a modification thereof. 11... Memory cell array, 12... Address buffer, )3... Address decoder, 14... Input/output circuit. 15... Boost circuit, 16... Control circuit, 17...
Boost voltage switching circuit, Qn,...first MOSFET
, Qpi...2nd MO8F B'1. ' , c＞,
nt”・3rd MOSFET, Qns, Qpt
``'crt, tos in park, Qn+...4th M
OSFET, Qps...5th M-O8F DT. Applicant's representative Patent attorney Takehiko Suzue Figure 1 (C) (d) Figure 2 Figure 3 φ 1937 1. Commissioner of the Japan Patent Office Kazuo Wakasugi 1.7B Indication Patent Application 1982- 16411.2 No. 2, Name of the invention Non-volatile semiconductor memory device 3, Relationship to the case of person acting as assistant market Patent applicant (307) Tokyo Shibaura Electric Co., Ltd. (2 others) 4. Agent 11 Tokyo Port Ward Toranomon IJ Exit 26 No. 5 No. 17 Mori Building ('+ rtli tl) Add the following sentence next to "Konohanai." on the 17th line of the page. 5 and 6, the input terminal IN of the switching circuit, that is, the output terminal of the decoder, and the output terminal O of the selection signal voltage.
MO8FF as a transfer gate between UT
;T-Qnl is provided, but it can be omitted. This is because when the decoder output is 1'' and a boosted potential is output to the selection signal voltage output terminal OUT, even if this is directly supplied to the decoder output stage, there is no current outflow in the normal decoder output stage configuration, and the decoder Output is +t On
This is because the supply of the boosted potential to the selection signal voltage output terminal OUT is blocked by the moment MO8TFgT-Qp. 2. r,'r r'li, claim 1'tl floating JJj
A memory cell array formed of an 11-1 memory rewritable non-volatile semiconductor memory cell having an H gate and a control gate, an address decoder, and an input/output circuit of 14, t'
4. A memory which is formed by integrating at least a booster circuit that can generate a high voltage for 4-channel switching, and a switching circuit that selects the output of this booster circuit according to the output of the address decoder and supplies it to the memory cell array. The switching circuit comprises a first conductive channel connected directly to the output end of the address decoder or a first conductive channel to which a read/write control signal is applied to the output terminal of the address decoder, the first of D type] MO
Selection signal '? connected via SFET? 1. A second conductive TK channel connected in series between the output terminal of the 4I voltage, the output terminal of the selection signal voltage, and the output terminal of the external pressure circuit.
H type 21st (first conductive channel whose dart is controlled by 408FE T and the selection signal voltage, ■)
Type: s h+OSF Iv 'r and the selection signal voltage are input, and the second M
A CMOS inverter that controls the gate of the M08FET, a first conductive channel connected in series with the ground end side M08FET of the CMOS inverter and controlled by a complementary signal of the readout 7 store control signal, and a fourth MO of the E type.
SFET and MO8F on the power supply side of the CMOS inverter
a second conductive channel E which is connected in parallel with ET and whose gate is controlled by a complementary signal of the read/1i inclusion control signal;
A non-volatile semiconductor memory device characterized in that a unit circuit comprising a fifth MOSFET of type 1 is provided at each output terminal of the address decoder. 1 Inclusive procedural amendment Showa' 5 < 9.10. Foot 7 ``1 Patent application 1987-1641122 Title of invention Non-volatile semiconductor memory device: Relationship with Party B and former IT of Kiura City Patent applicant (307) Toshiba Corporation (and 2 others) 11. Agent 5, voluntary action (11i Contents of amendment (1) rQptJ on page 9, line 2 of the specification is corrected to "Qnl". (2) Same. rR/W=, OV on page 10, line 13. Correct R/W=5vJ to "n/w=5V, R/W=OVJ." (3) Correct rOVJ on page 11, line 1 as " 5v,” he corrected.

Claims (1)

[Claims] A memory cell array consisting of electrically rewritable nonvolatile semiconductor memory cells having floating gates and control gates, an address decoder, an input/output circuit, a booster circuit capable of generating a high voltage for rewriting, and the output of this booster circuit. A memory device comprising at least a small-scale switching circuit that selects and supplies the output of the address decoder to the memory cell array according to the output of the address decoder, and the switching circuit has an input that is supplied with the output of the address decoder. a first conductive channel, a D-type first M08FBT, which is provided between the output terminal of the selection signal voltage and the output terminal of the booster circuit and whose gate is provided with a read/write control signal; a second conductive channel connected in series between the E-type second M08F]flT- and a first conductive channel whose gate is controlled by the selection signal voltage;
a D-type third MOSFET; a CMOS inverter that receives the selection signal voltage and controls the gate of the second MOSFET with its inverted output;
S the first conductive channel connected in series with the M08FET on the ground end side of the inverter and controlled by the complementary signal of the read/write control signal; the fourth MO8FB'l' of the E type;
and a fifth E-type conductive channel connected in parallel with the MO8FET on the power supply side of the CMOS inverter and whose gate is controlled by a complementary signal of the read/write control signal.
A nonvolatile semiconductor memory device characterized in that a unit circuit including a MOSFET is provided at each output terminal of the address decoder.