JPH0719475B2 - Sense amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention has a field effect transistor (hereinafter referred to as IGFET) having an insulated gate structure as a main constituent element, and is capable of operating even when the power supply voltage changes. The present invention relates to a sense amplifier circuit suitable for an electrically writable / erasable non-volatile memory device (hereinafter referred to as an EEPROM) capable of stably reading information written in a memory cell.

[Conventional technology]

FIG. 5 is a circuit diagram of a conventional example of a memory cell and a sense amplifier circuit for reading information written in the memory cell.

The circuit of this conventional example is a P-channel IGFET Q whose source is connected to the power supply CC and whose drain and gate are commonly connected to the point A.
Digit line point D with ₁ and point B as input and point C as output, which changes according to the information written in memory cell MC
Inverting amplifier I ₁ that amplifies the voltage of
The source is at point B, the gate is N-channel IGFET Q ₂ connected to the output point C of the inverting amplifier I ₁ , and the drain is at point B,
The gate is on the Y address line Y ₁ , and the source is on the digit line point D.
Connected to the memory cell M _11, ..., and N-channel type IGFET Q ₃ for selecting the Y address of Mn _1, drain read voltage
In V _READ , the gate is connected to the Y address line Y ₁ , the source is connected to the point G, the N-channel IGFET Q ₄ for selecting the Y address of the memory cells Mm ₁₁ , ..., Mmn ₁ , and the drain is connected to the point G. , The gate is connected to the X address line X ₁ , the source is connected to the point F ₁ which is the gate of the memory cell Mm ₁₁ , and the N channel type IGFET Q ₅ for selecting the X address of the memory cell Mmn ₁ and the drain are the points. D
, The gate is connected to the X address line X ₁ , the source is connected to the point E ₁ , the selection cell Ms ₁₁ of the N-channel type IGFET, the drain is connected to the point E ₁ , the gate is connected to the point F _1, and the source is grounded. a memory cell Mm ₁₁ that is, a drain and a gate to the point G to the X address line Xn, the source is connected to Fn point is the gate of the memory cell Mmn _1, selects the X address of the memory cells Mmn ₁ N-channel type IGFET Q ₆ and N-channel type with drain connected to point D, gate connected to X address line Xn, and source connected to point En
IGFET selection cell Msn ₁ and storage cell Mmn whose drain is connected to point En, gate to point Fn, and source to ground
₁ , a source connected to the power supply CC, a gate connected to the point A, a drain connected to the point H, a P-channel IGFET Q ₇ , a drain connected to the point H, a gate connected to the power supply CC, and a source connected to the ground. N-channel IGFET Q ₅₈ and P-channel IGFE with source connected to power supply CC, gate connected to point H and drain point I
TQ ₉ , an N-channel IGFET Q ₁₀ having its drain connected to point I, its gate connected to point H, its source connected to ground, and an inverting amplifier I ₂ whose input is connected to point I and whose output is connected to point J. Composed of. Although not shown, the substrate of the P-channel IGFET is connected to the power source CC, and the substrate of the N-channel IGFET is connected to the ground. In addition, all P channel type IGFE
T, all N-channel IGFETs are enhancement type. The selection cell Ms ₁₁ and the storage cell Mm _{11 form a} memory cell M ₁₁ , and the selection cell Msn ₁ and the storage cell Mmn _{1 form a} memory cell Mn ₁ .

The operation and design method of the sense amplifier circuit shown in FIG. 5 will be described. For simplicity of explanation, P channel type
The threshold of IGFET is the same for all IGFETs and V _TP , and the threshold of N-channel IGFET is the same for all IGFETs and V
_TN . Further, L represents the gate length of the IGFET, W represents the gate width of the IGFET, and represents the current drive capacity of the IGFET. Is simply written as W / L. In the following description, the state in which the memory cell is written is defined as “1”, and at this time, the threshold value V _TN of the memory cell shifts from the initial state to negative (eg, −5V), The threshold value of the memory cell at this time is defined as V _TN (W), and the erased state of the memory cell is defined as “0”. At this time, the threshold value of the memory cell is positive from the initial state. (For example, + 5V), and the threshold value of the memory cell at this time is V
_TN (E).

The memory cell used in the EEPROM is one that injects (erases) electrons from the drain through the thin oxide film into the floating gate, or emits (writes) electrons from the floating gate, so that writing / erasing is repeated. Since the electrons are trapped at the interface between the oxide film and the floating gate or the oxide film and the drain,
As shown in the figure, the absolute value of the threshold shift decreases as the programming / erasing is repeated.

The read voltage V _READ is set to V _TN (E ₁ ) and V _TN so that the standard of the number of times of repetition (100,000 times in this example) is satisfied.
It is set near the center of (W ₁ ). (In this example, V _READ
= 0V. (1) Operation of Sense Amplifier Circuit When a memory cell including a memory cell in which “1” is written is selected, a current (current value is I _ON ) flows through the memory cell and a point D, The voltage at point B drops. The voltage at point D at this time is V
_{Let D} (L). The voltage change at the point B is detected by the inverting amplifier I ₁ , the voltage at the point C rises, and finally becomes near the power supply voltage. At this time, IGFET Q ₂ becomes conductive, and W / L of IGFET Q ₂ becomes
It is designed to be large enough so that the voltage at point B can be transferred to point A. Therefore, the voltage at point A is from (V _CC −V _TP ) to V
It descends near _D (L). The voltage at point A at this time is V
_A (W) The W / L of IGFET Q ₇ is the voltage V
_The current value flowing in IGFET Q ₇ when _A (W) is applied is IGF
The voltage at point H is "H" and the voltage at point I is "H" because it is designed so as to be sufficiently larger than the current value I _REF5 flowing through ET Q ₅₈ , as shown in (2) below. The voltage at L "and point J becomes" H ".

When the memory cell including the memory cell in which "0" is written is selected, the memory cell becomes non-conductive because the threshold value of the memory cell is higher than the read voltage V _READ . The voltage is ( _CC −
Equilibrate with V _TP ). The voltage at point A at this time is V _A (E). Since IGFET Q ₁ and Q ₇ are both designed to have the same threshold value, IGFET Q ₇ becomes non-conducting and the charge charged in the capacitance added to point H is discharged by IGFET Q _58. Therefore, the voltage at the point H is "L", the voltage at the point I is "H", the point J
Voltage becomes "L".

(2) Sense Amplifier Circuit Design Method A conventional sense amplifier circuit design method will be described with reference to FIGS. 5, 6, 7, 8, and 9.

The curve represented by M in FIG. 7 is the current-voltage characteristic of the memory cell in which "1" is written when V _CC = 5V, and the curve represented by N is 10 cycles of write-erase. The curve represented by O for the current-voltage characteristics of the memory cell in which "1" is written when V _CC = 5V after 10,000 times is the curve when V _CC = 5V.
The load characteristics of GFET Q ₁ are shown respectively. 100,000 write - the repetition of the erase current flowing "1" is written storage cell is changed to I _ON (min) from I _ON. This sense amplifier circuit is designed in consideration of the decrease in the current flowing in the memory cell after the write-erase is repeated 100,000 times. Unless otherwise specified, I _ON (min) is called a current flowing through a memory cell. V _A (W ₁ ) is when V _CC = 5V,
The voltage at point A when a memory cell including a memory cell in which "1" is written is selected, V _A (W ₂ ) is V after the write-erase operation is repeated 100,000 times. the voltage of the point a in a case where when _CC = 5V "1" is selected memory cell including a memory cell that was written, V _a (E _1), when the V _CC = 5V, "0"
6 shows the voltage at point A when a memory cell including a memory cell in which is written is selected. V _A (E) = V
It is a _CC -V _TP. The value of V _A (W ₂ ) is determined by the W / L of IGFFET Q ₁ . That is, by increasing the W / L IGFFET Q _1, the value of V _A (W) is to approach the in V _A (E _1), the IGFET Q ₁
By reducing the W / L, the value of V _A (W) is away from V _A (E _1). W / L of the IGFET Q ₅₈ when the V _CC = 5V, the current I _REF5 flowing through the IGFET Q ₅₈ flows in the memory cell current I _ON (min)
Is designed to be equal to. IGFET Q ₁ and Q ₇ are so constitute a current mirror, when designing the W / L of IGFET Q ₇ equal to the W / L of Q _1, so that the flow I _ON (min) is in IGFET Q ₇ However, in this example, the W / L of IGFET Q ₇ is set to Q so that the inverting amplifier composed of IGFET Q ₇ and Q ₅₈ operates stably.
Designed to be three times the ₁ of the W / L.

Curve expressed by P in FIG. 8 is, IGFET Q ₁ the W / L of IGFET Q ₇
If designed to 3 times the W / L of the load characteristics of IGFET Q ₇ when the V _CC = 5V, the curve represented by N, when V _CC = 5V, storage of "1" is written The current-voltage characteristics of the cell are shown respectively. The voltage V _H (2) at the intersection of the curves P and N is V
_{When CC} = 5V, the voltage at point H is shown when a memory cell including a memory cell in which "1" is written is selected. IG
By making the W / L of FET Q ₇ three times the W / L of IGFET Q ₁ ,
The "H" level at the point H can be output stably.

The curve indicated by Q in Fig. 9 is the IGFET Q ₇ and Q when V _CC = 5V.
₈ shows the inverting voltage characteristic of the inverting amplifier composed of ₅₈ and ₅₈ . When V _CC = 5V, the logic threshold of the inverting amplifier composed of IGFET Q ₇ and Q _{58 is} between V _A (W ₂ ) and V _A (E), and this sense amplifier circuit is V _CC. It can be seen that the information written in the memory cell can be detected stably at = 5V.

As described above, the sense amplifier circuit of this example has V _CC = 5
It is designed based on the characteristics of each IGFET at V.

On the other hand, the read voltage V _READ is determined only by the device characteristics of the memory cell, so even if the power supply voltage changes, V _READ
The value of _READ must be constant.

If it changes depending on the power supply voltage, the value of V _READ cannot fall between V _TN (E ₁ ) and V _TN (W ₁ ). In this example, it is assumed that the value of V _READ is always 0V even if the power supply voltage changes. Therefore, in this example, since the memory cell operates in the saturation region, even if the power supply voltage rises (for example, V _CC = 8V), the current flowing in the memory cell in which “1” is written does not flow. I _ON
(Min) is reached, and the current is assumed to be the same as when V _CC = 5V, and the discussion proceeds.

(3) from Figure 5 the operation of the sense amplifier circuit of the present example in which changes from operating V _CC = 5V sense amplifier circuit when changed to V _CC = 8V from V _CC = 5V to V _CC = 8V first This will be described with reference to FIG.

The curve represented by R in FIG. 10 shows the power supply voltage dependence of the current flowing through the IGFET Q ₅₈ . When V _CC = 5V, the current that flows during design is I _ON (min), but when V _CC = 8V, it rises to I ₅ .

Curve represented by S in FIG. 11, when the V _CC = 8V, the current of the memory cell for "1" has been written - voltage characteristics curve represented by T, when the V _CC = 8V, Q ₁ It shows the load characteristics of. V
_A (W ₃ ) is the voltage at point A when a memory cell including a memory cell in which “1” is written is selected when V _CC = 8V,
V _A (E ₂ ) shows the voltage at point A when a memory cell including a memory cell in which “0” is written is selected when V _CC = 8V. The curve represented by U in FIG. 12 is V _CC = 8
At V, the curve showing the load characteristics of IGFET Q ₇ by V is V _CC
It shows the current-voltage characteristics of IGFET Q ₅₈ when ＝ 8V. When V _CC = 8V, the current flowing through IGFET Q ₇ is V _CC
= 5V, the same current as 3I _ON (min), but IGF
Since the current flowing through the ET Q ₅₈ is I ₅ as shown in FIG. 10, the current-voltage characteristic of the IGFET Q ₅₈ is the curve represented by U in FIG. Therefore, the voltage at the point H when the memory cell including the memory cell in which "1" is written is selected is V _H (3)
Becomes As is clear from comparing FIG. 8 and FIG. 12, when the power supply voltage rises, the gm of IGFET Q ₅₈ rises compared to the gm of IGFET Q ₇ , so the “H” level at point H becomes When V _CC = 8V, the "H" level at point H becomes V _H
It becomes (3). The curve represented by W in FIG. 13 shows the inverting voltage characteristic of the inverting amplifier composed of IGFETs Q ₇ and Q ₅₈ when V _CC = 8V. When V _CC = 8V, the voltage at point A depends on V _A (E ₂ ) and V according to the information written in the memory cell.
_It oscillates between _A (W ₃ ), but the voltage at this time H is “L” and V
_{Amplify H} (3). Since V _H (3) is less than the logic threshold value [V _I ] of the inverting amplifier composed of Q ₉ and Q ₁₀ in the next stage, this sense amplifier circuit malfunctions when V _CC = 8V. .

[Problems to be solved by the invention]

As mentioned above, when V _CC = 5V, this sense amplifier circuit is designed. However, when the power supply voltage rises, IGFET Q ₇ and Q
The characteristics of the inverting amplifier composed of ₅₈ and ₅₈ deviate from the designed values, and the information in the memory cell in which "1" is written cannot be read out stably. Therefore, if the power supply voltage rises, this sense amplifier circuit Has the drawback of malfunctioning. That is, there is a drawback that the characteristics of the conventional inverting amplifier greatly vary with respect to the power supply voltage.

In addition to the conventional example shown in FIG. 5, instead of the IGFET Q ₅₈ ,
There is also a circuit example (dummy cell type sense amplifier circuit) in which a dummy cell having the same structure and characteristics as the memory cell is connected, but the memory cell has a floating gate and has a thin gate oxide film, so it is possible to manufacture an EEPROM. inside,
Electrons are injected into the floating gate, and the threshold value of the memory cell that does not perform write-erase varies in each memory cell. Therefore, since the inverting voltage characteristic of the inverting amplifier composed of the IGFET Q ₇ and the dummy cell varies depending on the chip, the dummy cell type sense amplifier circuit is not suitable for the EEPROM.

An object of the present invention is to provide a sense amplifier circuit suitable for an EEPROM which requires that the read voltage of a memory cell be constant with respect to a power supply voltage.

[Means for solving problems]

To this end, the sense amplifier circuit according to the present invention includes a first conductive channel type first transistor connected between a power supply terminal and a circuit point and having a gate connected to the circuit point, the circuit point and a digit. A second transistor of a reverse conduction channel type connected between an input point of a current flowing through the line and an inverting amplifier having an input and an output connected to the input point and the gate of the second transistor, respectively;
A third transistor of the first conductive channel type, the gate of which is connected between the power supply terminal and the output point and whose gate is connected to the gate of the first transistor, and the gate of which is connected between the output point and the reference terminal In a sense amplifier circuit having a reverse conduction channel type fourth transistor that receives a reference voltage, a voltage stabilized against a variation in a power supply voltage between the power supply terminal and the reference terminal is generated, and the voltage is used as the reference voltage. A reference voltage circuit for supplying to the gate of the fourth transistor is provided, and the current supplied by the fourth transistor in response to the reference voltage is stabilized against variations in the power supply voltage.

That is, since the reference voltage generation circuit is configured so that the reference voltage hardly changes even when the power supply voltage rises, the current flowing in the memory cell is constant, that is, the read voltage of the memory cell is constant, and The malfunction of the amplifier circuit is prevented.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a memory cell and an embodiment of a sense amplifier circuit according to the present invention.

Since the memory cell MC is exactly the same as the conventional memory cell MC shown in FIG. 5, the description thereof will be omitted. Also,
The same parts as those in FIG. 5 are designated by the same symbols as in FIG. 5 to simplify the description.

The sense amplifier circuit of this embodiment has a P-channel IGFET Q ₁₁ whose source is connected to the power supply CC and whose gate is grounded, and an N-channel whose drain and gate are commonly connected to the drain of the P-channel IGFET Q _11. Type IGFET Q ₁₂ and drain and gate are common to the source of N-channel type IGFET Q ₁₂ ,
It has a reference voltage generation circuit REF composed of an N-channel type IGFET Q ₁₃ whose source is connected to the ground. Furthermore, the source is input to the power supply CC, the P-channel IGFET Q ₁ whose drain and gate are commonly connected to the circuit point A, the drain to the circuit point A, the gate to the output CC of the inverting amplifier I ₁ , and the source to the input. N-channel IGFET Q ₂ connected to point B respectively
And an inverting amplifier I ₁ having an input at the input point B, a P-channel IGFET Q ₇ having a source connected to the power supply CC, a gate point A, and a source connected to the output point H, and a drain to the output point H, The gate has an output V _REF of the reference voltage generating circuit REF, and the N-channel type IGFET Q ₁₈ whose source is connected to the ground.
At the output point H, the source is connected to the power source CC, the drain is connected to the point I, the gate of the P-channel type IGFET Q ₉ , the drain is connected to the circuit I, and the source is connected to the ground N.
Connected to the gate of channel type IGFET Q ₁₀ ,
Is connected to the input of an inverting amplifier I ₂ whose output is connected to point J.

Next, the operation and design method of this embodiment will be described with reference to FIGS.
This will be described with reference to FIGS. 3, 3 and 4.

(1) Operation of the sense amplifier circuit of this embodiment In the sense amplifier circuit of this embodiment, the gate is connected to the reference voltage V _REF in place of the IGFET Q ₅₈ whose gate is connected to the power supply CC in the conventional example. since those configurations having IGFET Q _18, operation of the sense amplifier circuit of this embodiment, in terms of operation of the described (1) a sense amplifier circuit of the "prior art", the Q ₁₈ in place of Q ₅₈ Since the current is the same as that of the current I _REF1 flowing in Q ₁₈ instead of I _REF5 , the description thereof will be omitted.

(2) Design method reference voltage generating circuit REF of the sense amplifier circuit of this embodiment, the W / L of the IGFET Q ₁₁ of IGFET Q ₁₂
W / L and W / L of IGFET Q ₁₃ are made sufficiently small so that V _REF ≈ 2 V _TN (V _TN is the threshold of IGFET Q ₁₂ and Q ₁₃ ) even if the power supply voltage rises. For example, To design. The W / L of IGFET Q ₁₈ is the same as in the case of the conventional example when V _CC = 5V in consideration of the decrease in the current flowing in the memory cell in which “1” is written due to repeated write-erase. Design the current I _REF1 flowing through IGFET Q ₁₈ to be equal to I _ON (min). The W / L of IGFET Q ₁ is the same as the case of the conventional example, and IGFET Q ₁ when V _CC = 5V represented by O in FIG. 7 is used.
And the current-voltage characteristic of the memory cell in which "1" is written when V _CC = 5V, which is represented by N. The W / L of IGFET Q ₁ of this embodiment is the IGF of the conventional example shown in FIG.
It is assumed to be the same as the W / L of ET Q ₁ .

As in the case of the conventional example, the IGFET Q ₇ has an IGFET so that the inverting amplifier composed of the IGFETs Q ₇ and Q ₁₈ operates stably.
Design the W / L of FET Q ₇ to be 3 times the W / L of Q ₁ .

Therefore, in the case of the present embodiment, when the memory cell including the memory cell in which "1" is written is selected when V _CC = 5V, the voltage at the point A is V _A as in the case of the conventional example. (W _I )
When a memory cell including a memory cell in which "0" is written is selected, the voltage at point A is [V
_A (E)].

Further, the current-voltage characteristic of IGFET Q ₁₈ when V _CC = 5V is represented by N in FIG. 8 and the load characteristic of IGFET Q ₇ is represented by P in FIG. 8, and when V _CC = 5V The inverting voltage characteristic of the inverting amplifier composed of IGFETs Q ₇ and Q ₁₈ is represented by Q in FIG. 9 and is no different from the case of the conventional example. The sense amplifier circuit of the present embodiment operates normally when V _CC = 5V, as in the case of the conventional example.

(3) In the present embodiment, the operation of the sense amplifier circuit when V _CC = 5V changes to V _CC = 8V, the curve indicated by R ₁ in FIG. 2 is IG when the power supply voltage changes.
This shows the change in the current flowing through the FET Q ₁₈ . Since the reference voltage generator REF is designed so that the value of the reference voltage V _REF hardly changes even if the power supply voltage rises, the current that flows when V _CC = 8 V becomes I ₁ , and V _CC = There is almost no difference from the current I _ON (min) that flows at 5V. As a comparison, the curve represented by R is IGFET Q ₅₈ in the conventional example.
It shows the change in the current flowing through the.

The curve represented by V ₁ in FIG. 3 is the current-voltage characteristic of the IGFET Q ₁₈ when V _CC = 8V, and the curve represented by U is I when V _CC = 8V.
It shows the load characteristics of GFET Q ₇ . IGFET Q ₁ and Q ₇
Since the W / L is the same as that of the conventional example, the load characteristics of IGFET Q ₇ are exactly the same as those of the conventional example. As can be seen by comparing FIGS. 3 and 12, in the case of this embodiment, V ₁
As shown in, even if V _CC = 8V, the current that flows in IGFET Q ₁₈ becomes I ₁ , and the current I _ON that flows when V _CC = 5V in the design.
Since it is not much different from (min), when V _CC = 8V, the voltage at point H becomes V _H (1) when the memory cell including the memory cell in which "1" is written is selected, Since "H" is output, the voltage at the point H is changed only when the memory cell including the memory cell in which "1" is written is selected when V _CC = 8V as in the conventional example. It becomes V _H (3), and the sense amplifier circuit does not malfunction.

The curve represented by W ₁ in Fig. 4 is the IGFET Q ₇ and Q when V _CC = 8V.
₁₉ shows the inverting voltage characteristic of the inverting amplifier composed of ₁₈ and. V _A (W ₃ ) is the same as V _CC (W ₃ )
= 8V, the voltage at point A when the memory cell including the memory cell in which "1" is written is selected, V _A (E ₂ ) is the same as V _CC (E ₂ ) in the conventional case. = 8V, point A when a memory cell including a memory cell in which "0" is written is selected
It shows the voltage of. As can be seen by comparing FIGS. 4 and 11, in the case of this embodiment, the inverting amplifier composed of IGFETs Q ₇ and Q ₁₈ has a logical threshold value even if V _CC = 8V. It is set between V _A (W ₃ ) and V _A (E ₂ ), and V _H
Since (1) is larger than the logical threshold value V _{I of the} inverting amplifier composed of the IGFETs Q ₉ and Q ₁₀ in the next stage, the sense amplifier circuit of the present embodiment can operate normally even if V _CC = 8V. You can see it works.

As described above, in the sense amplifier circuit of this embodiment, even if the power supply voltage rises to V _CC = 8V, the output voltage is V _CC =
Since the reference voltage generating circuit REF which hardly changes from that at 5V is provided, the sense amplifier circuit of this embodiment operates normally even if V _CC = 8V.

〔The invention's effect〕

As described above, the sense amplifier circuit of the present invention includes the reference voltage generation circuit that outputs a substantially constant voltage even when the power supply voltage changes, so that the read voltage of the memory cell is constant with respect to the power supply voltage. Therefore, it is effective for applications such as EEPROM in which the current flowing in the memory cell is constant with respect to the power supply voltage.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a sense amplifier circuit according to the present invention, and FIG. 2 is a diagram showing the dependency of the current flowing through the IGFET Q ₁₈ on the power supply voltage (curve R ₁ ) in FIG. Conventional example
Figure 3 shows the power supply voltage dependence of the current flowing through IGFET Q ₅₈ (curve R). Figure 3 shows the IGF when V _CC = 8V in Figure 1.
FIG. 4 shows the load characteristics (curve U) of ET Q ₇ and the current-voltage characteristics (curve V ₁ ) of IGFET Q ₁₈ , and FIG.
FIG. 6 is a diagram showing an inversion voltage characteristic (curve W ₁ ) of an inverting amplifier composed of Q ₇ and Q ₁₈ when V _CC = 8V, FIG. 5 is a diagram showing a conventional sense amplifier circuit, and FIG. Is the change in the threshold value of the erased storage cell due to the write-erase repetition cycle (curve K), and the write-erase repetition of the threshold value of the written storage cell. shows changes in threshold due to cycle (curve L), FIG. 7 is, V _CC
= 5V load characteristic of IGFET Q ₁ (curve O), current-voltage characteristic of memory cell in which "1" is written (curve M), and after 100,000 write-erase repeated cycles The figure which shows the current-voltage characteristic (curve N) of the memory cell in which "1" was written,
FIG. 8 shows current-voltage characteristics (curve N) of IGFET Q _{18 in} FIG. 1 and IGFET Q ₅₈ in FIG. 5 when V _CC = 5V, and IGFET Q ₇
9 shows the load characteristic (curve P) of FIG. 5, and FIG. 9 shows the inversion voltage characteristic (curve Q) of the inverting amplifier composed of IGFETs Q ₇ and Q ₅₈ when V _CC = 5V in FIG. Figure, Figure 10
FIG. 5 is a graph showing the power supply voltage dependence (curve R) of the current flowing through the IGFET Q _58, and FIG.
Current-voltage characteristics (curve S) of IGFET Q ₅₈ when V _CC = 8V
And the load characteristics (curve T) of IGFET Q ₇ and FIG. 12 are the load characteristics (curve U) of IGFET Q ₇ and the current of IGFET Q ₅₈ when V _CC = 8V in FIG. FIG. 5 shows the voltage characteristic (curve V), and FIG. 13 shows the inverting voltage characteristic (curve W) of the inverting amplifier composed of IGFETs Q ₇ and Q ₅₈ when V _CC = 8V in FIG. FIG. Q ₁₁ , Q ₁ , Q ₇ , Q ₉ : P Channel type IGFET, Q ₁₂ , Q ₁₃ , Q ₂ , Q ₁₈ , Q ₁₀ : N Channel type IGFET, REF: Reference voltage generator, I ₁ , I ₂ : Inverting amplifier, V _REF : Reference voltage, CC: Power supply.

Claims (2)

[Claims] 1. A first conductive channel type transistor connected between a power supply terminal and a circuit point and having a gate connected to the circuit point, and an input to which a current flowing through the circuit point and a digit line is supplied. A second transistor of the reverse conduction channel type connected to the point, an inverting amplifier having the input point as an input and an output connected to the gate of the second transistor, and connected between the power supply terminal and the output point. A gate is connected between the gate of the first transistor and the third transistor of the first conductive channel type that forms a current mirror together with the first transistor, and is connected between the output point and the reference terminal, and a reference voltage is applied to the gate. In the sense amplifier circuit including the fourth transistor of the reverse conductive channel type that receives the voltage, it is safe against fluctuations in the power supply voltage between the power supply terminal and the reference terminal. A reference voltage circuit that generates a converted voltage and supplies the voltage as the reference voltage to the gate of the fourth transistor, and causes a current flowing by the fourth transistor in response to the reference voltage to change in the power supply voltage. A sense amplifier circuit characterized by being stabilized. 2. A fifth transistor of the first conductive channel type, wherein the reference voltage circuit is connected between the power supply terminal and a reference voltage output terminal and has a gate connected to the reference terminal, and the reference voltage output. A plurality of reverse conduction channel type sixth transistors connected in series between an end and the reference terminal, each gate having a plurality of sixth transistors connected to the drain, The sense amplifier circuit according to claim 1, wherein the ratio of the channel width to the channel length of the fifth transistor is set smaller than that of the sixth transistor.