JPS63223691A - Controller driver circuit for color liquid crystal display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color liquid crystal display device, and more specifically to a color liquid crystal display device that is a color matrix liquid crystal display panel and outputs color image data to the panel. The present invention relates to a controller/driver circuit for a color liquid crystal display when the controller/driver circuit is divided into a controller/driver circuit for a color liquid crystal display.

[Conventional technology]

Conventional liquid crystal display devices use a liquid crystal display controller such as Hitachi's HD63645F to provide image data read from a display memory that stores image data to be displayed to a liquid crystal display means, and the liquid crystal display means displays the given image. Images were displayed by capturing data line by line in the horizontal direction of the screen and outputting it to a liquid crystal panel. However, such conventional liquid crystal display devices are intended for monochrome display, and no consideration has been given to color display.

A conventional liquid crystal display device is illustrated below using FIGS. 2 to 4.
I'll explain it to you.

FIG. 2 is a schematic diagram showing a conventional liquid crystal display device. In the figure, 1 is a liquid crystal controller, 2 is an address generation means, 3 is a memory address, 4 is a data shift clock, 5 is a horizontal clock generated in synchronization with the horizontal scanning period of the screen, and 6 is a line start clock. It's ivy. A memory address 3, a data shift clock 4, a horizontal clock 5, and a line start clock 6 are generated by the address generation means 2. 35 is image storage means (hereinafter also referred to as memory) for storing image information to be displayed; 36 is memory data having a bus width of 8 bits read from the memory 35 at memory address 3; and 37 is data output means. Therefore, memory data 36 with a bus width of 8 bits
data output means 38 receives the input data, converts it into display data having a bus width of 4 bits suitable for liquid crystal display, and outputs the same. This display data 38 has a bus width of 4 bits. 31 is X
(Axis direction) driving means, 30 is 1-line liquid crystal display data,
32 is a Y (axis direction) driving means, 33 is display line data, 34 is a liquid crystal panel, and X driving means 31. Y drive means 32
The display data is displayed on a liquid crystal display.

FIG. 3 is a block diagram showing details of the X drive means 31 in FIG. 2.

In FIG. 3, numeral 39 is data shift means for taking in display data 38 for one line using data shift clock 4, 40 is shift data that is the output of data shift means 39, and 41 is 1 for latching shift data 40 using horizontal clock 5. Line means lunch. XDI to XD640 are one line liquid crystal data 30 when one line on the liquid crystal display screen is 640 dots.

FIG. 4 shows the X drive means 31Y drive means 3 in FIG.
2 is a timing diagram of each signal related to the operation when driving the liquid crystal panel 34. FIG.

In FIG. 4, (A) is a horizontal clock 5, that is, a clock generated in synchronization with each horizontal scanning period (IH period) on the display screen. (b) is a data shift clock 4, that is, a clock having a much higher repetition frequency than the horizontal clock 5, and in FIG.
is a data shift clock used to shift the data in the shift means 39. (c) is display data 38
The timing diagram shows the display data from 1 to 1 as 3 days.
It will be appreciated that up to 160 pieces of display data are shown, each of which is synchronized to the data shift clock 4.

(d) is a timing diagram showing the horizontal clock 5 as well, but the time scale is set smaller than in the case of (a). (E) is 1 line liquid crystal display data XDI~X
This shows that the first line, second line, third line, etc. of D640 are synchronized with the horizontal clock 5. (F) and (G) are display line data 33 outputted by the X driving means 32, respectively. That is, (to) is the display line data YDI to display the first line,
(G) is display line data YD2 that indicates that the second line should be displayed.

Hereinafter, reference will be made to FIG. 2 again to explain the operation.

In FIG. 2, the image information stored in the memory 35 is read out according to the memory address 3 output from the address generating means 2, and becomes memory display data 36 (8-bit width). This 8-bit memory display data 36
is taken into the data output means 37, and is divided into upper 4 bits and lower 4 bits in order to convert it into a 4-bit width data format suitable for the interface on the liquid crystal panel side. The divided 4-bit data becomes liquid crystal display data 38 according to the data shift clock 4 and is outputted from the data output device 37.

The liquid crystal display data 38 is given to the X driving means 31 together with the data shift clock 4 and the horizontal clock 5, and the horizontal clock 5 and the line start clock are given to the X driving means 32, so that the display data 38 is displayed on the liquid crystal panel 34. It will be displayed.

The operations of the X drive means 31 and the X drive means 32 will be explained below with reference to FIGS. 3 and 4.

In FIG. 3, as shown in FIG. 4, after outputting the first horizontal clock 5, the data shift means 39 outputs 160 pieces of display data 38, that is, 640 dots (160 x 4 bits), according to the data shift clock 4. The data for the period is taken into the IH period and output as shift data 40. This shift data 40 is launched by the 1-line launch means 41 at the falling edge of the horizontal clock 5, and becomes 1-line data 30 (XDI to XD640). That is, the X drive means 31 uses the data one line before the line of display data 38 currently taken into the data shift means 39 as one line data 30, and outputs the data to the one line latch means 4 as one line data 30.
1 to the liquid crystal panel 34. 1 line data 30
is the display line data 33 which is the output of the X driving means 32.
((to) in Figure 4.

(See (g)), the lines that are "high" are displayed on the liquid crystal panel 34.

The X driving means 32 sets the first line YDl of the liquid crystal panel 34 to "high" by taking in the line start clock 6 with the horizontal clock 5, and thereafter changes the second line YD2.3 every time the horizontal clock 5 is input. Eye YD3・
Shift "high" in the order of... Therefore, as shown in FIG. 4, when the X driving means 31 is outputting the first line data 30 of the first line, the X driving means 32 sets YDI of the display line data 33 to "high".
and the X driving means 31 receives the first line data 3 of the second line.
When outputting 0, the X driving means 32 sets YD2 of the display line data 33 to "high".

The display data 38 is displayed on the liquid crystal panel 34 by the operations of the X driving means 31 and the X driving means 32 described above.

[Problem that the invention seeks to solve]

In the conventional liquid crystal panel 34 shown in FIG.
By adding (green) and B (blue) color filters, it is possible to display eight colors (a combination of R, G, and H).

FIG. 5 is an explanatory diagram of a liquid crystal panel provided with such a color filter. As shown in FIG. 5, by expressing one line of visible information with three lines on the liquid crystal panel with R2O and B filters, it is possible to display eight colors. However, as shown in Figure 5, such a liquid crystal panel has 200 vertical lines of visible information, but it actually has 3 colors (R, G, B), so it has three times that number, or 600 lines (200X3). line is required. Therefore, in the conventional liquid crystal display device shown in FIG. 2, if an attempt is made to realize a color liquid crystal display device by replacing only the liquid crystal panel 34 with the one for color display shown in FIG. Data access and data transfer to the X driving means 31 requires three times the speed compared to monochrome data because the data is data in the three primary colors of R, G, and B.
A problem arises in that the drive means are both expensive.
- An object of the present invention is to solve the above problems and provide a controller/driver circuit for a color liquid crystal cover that enables color display in a liquid crystal display device without requiring expensive memory or driving means. .

[Means for solving problems]

In order to solve the problem, in the present invention, in a controller/driver circuit for outputting image data to be displayed to a color matrix liquid crystal display panel, data output means, liquid crystal display data latch means for each primary color, and color separation clock are provided. The apparatus includes a generating means and a means for separating liquid crystal display data by primary color.

[Operation] The data output means is inputted with each primary color data read out from the storage means for dividing the image data to be displayed into N types (N is an integer) of primary colors and storing them as primary color data, and displays the data on the liquid crystal display. The data is converted into a standard data format and output as liquid crystal display data. There are N liquid crystal display data latch means, and each of the liquid crystal display data for each primary color from the data output means is latched in the horizontal direction 154 on the display screen.
Store and latch in 7 minute increments. The color separation clock generation means chronologically generates N clocks as color separation clocks for each horizontal scanning period on the display screen.

The primary color separation means for liquid crystal display data sequentially selects each of the N liquid crystal display data latch means within one horizontal scanning period using the color separation clock, and separates the liquid crystal display data stored therein by primary color. It is separated and output to the color matrix liquid crystal display panel in units of one line in the horizontal direction.

As described above, data can be imported into the driver circuit (liquid crystal display data latch means, liquid crystal display data separation means for each primary color) that outputs data to the color matrix liquid crystal display panel in the same way as when importing single color data. (If three sets of primary color data are imported in series, it will be three times faster) and the memory can be accessed at the same speed as for single color data. It becomes possible.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

For convenience of explanation, it is assumed that the color display is eight colors and that the color image data consists of R, G, and B primary color data.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, l is a color liquid crystal controller, 2 is an address generation means, 3 is a memory address, 4 is a data shift clock, 5 is a horizontal clock, 6 is a line start clock, 30 is 1 line liquid crystal display data, 31 32 is a Y driving means for color, 33 is display line data, 34 is a liquid crystal panel for color (see Fig. 5),
It is.

In addition, 7 is an R storage means (hereinafter also referred to as R memory) for storing the R component of color image data as data, 8 is a G storage means (hereinafter also referred to as G memory) for storing the G component of color image data as data, 9 is a B storage means (hereinafter also referred to as B memory) that stores the B component of color image data as data, and 10, 11, and 12 are used to read data from the R memory 7, G memory 8, and B memory 9, respectively, using memory address 3. Output 8-bit wide R memory data, G
Memory data, B memory data. Reference numeral 13 denotes data output means, and 14, 15, and 16 represent outputs of the data output means 13, which are R display data, G display data, and B display data, respectively.

The data output means 13 outputs 8-bit R memory data 10.
．． G memory data 11 and B memory data l2 are respectively input, and they are divided into upper 4 bits and lower 4 bits, and according to data shift clock 4, 4 bits of R display data, 14.4 bits of G display data, 15.4 bits of G memory data are input. It is output as B display data 16.

50 is a color separation clock generation means, and 51 is a color separation clock. The color separation clock generation means 50 includes:
Horizontal clock 5 and data shift clock 4 are input,
As a result, a color separation clock 5 consisting of three clocks located chronologically within one horizontal scanning period of screen scanning is generated.
1 is generated and output.

17, 18, and 19 are shift means for taking in one line of R display data 14, G display data 15, and B display data 16, respectively; 17 is an R shift means, 18 is a G shift means, and 19 is a B shift means. be. 20, 21, and 22 are the outputs of the respective shift means, which are R shift data, G shift data, and B shift data. 23, 24, and 25 are latch means for respectively latching the R shift data 20, G shift data 21, and B shift data 22 by the horizontal clock 5, 23 is the R latch means, 24 is the G latch means, 25 is the B latch means.

26, 27, and 28 are the outputs of each launch means, which are R line data, G line data, and B line data. 29
is a primary color separation means, which receives R line data 26, G line data 27, and B line data 28 as input, and according to the color separation clock 51, depending on the first pulse (first clock) of the clock, R line data 26 is divided into two pulses. eye(
G line data 27 depending on the second clock),
Depending on the third pulse (third clock), the B line data 28 is output as one line of liquid crystal data 30, respectively.

FIG. 6 is a timing diagram showing the relationship between the R display data 14, G display data 15, B display data 16, data shift clock 4, and horizontal clock 5.

It will be appreciated that each display data is synchronized with the data shift clock 4, that one line of data falls between the horizontal clocks 5, and so on.

FIG. 7 is a circuit diagram showing a specific example of the color separation clock generation means 50. In the figure, 42 is a T counter which resets itself by setting its output high after counting T input clocks, and 49 is a count output of the T counter. 43 is a 2 counter which outputs a high level after counting the input clock by 2 after reset, and 48 is a clock mask signal which masks the clock input to the T counter 42 in the AND circuit 46. 45 is an OR circuit, and 44 and 47 are inverters.

FIG. 8 is a timing diagram showing the operation of the color separation clock generation means 50 shown in FIG.

It will be appreciated that three color separation clocks 51 are located within one period (IH period) of the horizontal clock 5.

FIG. 9 is a timing diagram showing the operation of the X drive means 31, particularly the primary color separation means 29, in FIG.

Hereinafter, reference will be made to FIG. 1 again to explain the operation.

In FIG. 1, color image information is R, G.

Each of the B primary color components is divided into an R memory 7 and a G memory 8.
, are stored in the B memory 9. This stored color image information is simultaneously read out by the memory address 3 outputted from the address generating means 2, and R memory data 10, G memory data 11, and B memory data 1 each having a width of 8 bits are read out.
It becomes 2. R memory data 10, G memory data 11,
B memory data 12 is taken into data output means 13 and divided into upper 4 bits and lower 4 bits.

The divided data of 4 bits each are output from the data output means 13 as R display data 14, G display data 15, and B display data 16, respectively, in accordance with the data shift clock 4.

As shown in FIG. 6, the data output means 13 outputs each display data 14, 15,
6, ie, 640 (4×160) dots, are output in synchronization with the data shift clock 4.

As already mentioned, the color separation clock generation means 50 can be realized with the circuit configuration shown in FIG. The operation is shown in Figure 7.
This will be explained with reference to FIG.

In FIG. 7, when the horizontal clock 5 is input, the T counter 42, 2 counter 43 is reset by its output via the inverter 44. Therefore, inverter 47
The clock mask signal 48 which is the output of T
The counter 42 converts the data shift clock 4 into an AND circuit 4.
6, and the counting operation is performed accordingly. As shown in FIG. 8, the T counter 42 counts T data shift clocks 4 and outputs a count output 4.
Repeat the action of setting 9 to “high” twice.

When the count output 49 becomes "high" twice, the second counter 43 that is counting the "high" outputs "high" twice.
In order to make it "high", the clock mask signal 48 outputted via the inverter 47 becomes "low".This closes the AND circuit 46 and stops the counting operation of the T counter 42.

As described above, as shown in FIG. 8, the color separation clock 51 is generated by ORing the outputs of the horizontal lock 5 and the counter 49 and outputting the result, three times during one horizontal scanning period. This is the clock that is generated.

Next, the operation of the X drive means 31 in FIG. 1 will be explained with reference to FIG. 9. Each display data 14, 15, and 16 outputted from the data output means 13 is a data shift clock 4.
At the falling edge of , one line is taken into each of the R shift means 17, G shift means 18, and B shift means 19. When 1947 worth of data is taken into each of the R shift means 17, G shift means 18, and B shift means 19, the outputs thereof, R shift data 20, G shift data 21, and B shift data 22, are output from the horizontal clock 5. A falling edge causes each R latch means 23. .

It is taken into the G latch means 24 and the B latch means 25.

This data is output as R line data 26, G line data 27, and B line data 28 from each latch means for one line period, which is the period of the horizontal clock 5.

Therefore, the shift means takes in data one line after the line data latched by the launch means. The primary color separation means 29 is connected to one of the horizontal clocks 5.
1 of the three color separation clocks 51 in the cycle
R line data 27 by the pulse (first clock)
, G line data 28 is selected by the second pulse (second clock), and B line data 29 is selected by the third pulse (third clock) and output as line liquid crystal data 30.

By using the color separation clock 51 as its shift clock, the Y driving means 32 sets the MDI to "high" when R1 of the first line of visible information is line liquid crystal data 30, as shown in FIG. When 01 on the first line of information is line liquid crystal data 300, YD2 is set to 1 high.

As explained above, the color separation clock generation means 50
, access to the memory storing color image information by the primary color separation means 29, and data transfer to the shift means in the X driving means can be the same as in the case of single color data, and the access, data The transfer speed can be made comparable to that in a conventional monochrome liquid crystal display device.

〔Effect of the invention〕

According to the present invention, access to the memory and data transfer to the shift means in the Since it can be made equivalent to that in the system, the memory and driver can be made inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional liquid crystal display device, FIG. 3 is a block diagram of the X driving means in FIG. A timing diagram showing the operation of the X drive means and Y drive means in the figure, FIG. 5 is a configuration diagram of a color liquid crystal panel, and FIG. 6 shows R and G in FIG. FIG. 7 is a timing diagram showing the relationship between the display data of B, the data shift clock, and the horizontal lock; FIG. 7 is a circuit diagram showing an example of the configuration of the color separation clock generation means in FIG. 1;
This figure is a timing diagram showing the operation of the color separation clock generating means shown in FIG. 7, and FIG. 9 is a timing diagram showing the operation of the X driving means and Y driving means in FIG. 1. Description of symbols 1...Liquid crystal controller, 2...Address generation means, 3...Memory address, 4...Data shift clock, 5...Horizontal clock, 6...Line start clock, 7... ...R storage means, 8...G storage means,
9...B storage means, 10...R memory data, 11
...G memory data, 12...B memory data, 1
3...Data output means, 14...R display data, 1
5...G display data, 16...B display data, 50
...Color separation clock generation means, 51...Color separation clock, 17...R shift means, 18...G
Shift means, 19...B shift means, 20...R shift data, 21...G shift data, 22...B
Shift data, 23...R latch means, 24...G
Latch means, 25...B latch means, 26...R line data, 27...G line data, 28...B
Line data, 29...Primary color separation means, 30...1
Line liquid crystal data, 31...X driving means, 32...
Y driving means, 33...Display line data, 34...
LCD panel, 42...T counter, 43...2 counter, 48...clock mask signal, 49...count output agent patent attorney Akio Namiki Figure 1! ! 21! ! Mugisho Core Draw Part 3! ! ! (G) Y-D2 15 Figure

Claims (1)

[Claims] 1. In a controller/driver circuit for outputting image data to be displayed to a color matrix liquid crystal display panel, the image data to be displayed can be outputted in N ways (N is an integer).
data output means for inputting each primary color data read out from the storage means for storing it as primary color data divided by primary color, converting it into a data format suitable for liquid crystal display and outputting it as liquid crystal display data; A total of N liquid crystal display data latch means for storing and latching the liquid crystal display data for each primary color from the means for one horizontal line on the display screen, and a total of N liquid crystal display data latch means for storing and latching the liquid crystal display data for each primary color on the display screen, and for each horizontal scanning period on the display screen, N clocks are sent to the color display screen. a color separation clock generation means for generating time series as a separation clock; and a color separation clock for sequentially selecting each of the N liquid crystal display data latch means within one horizontal scanning period using the color separation clock and storing the data therein. Separate the LCD display data by primary color and display it in the horizontal direction 1
Separating means for separating liquid crystal display data by primary color to output it to the color matrix liquid crystal display panel in units of lines;
A controller/driver circuit for a color liquid crystal display, characterized by comprising: 2. In the color liquid crystal display controller/driver circuit according to claim 1, the image data is R.
The color separation clock generation means chronologically generates three clocks as color separation clocks for each horizontal scanning period. The primary color separation circuit for liquid crystal display data separates each liquid crystal display data of R (red), G (green), and B (blue) and sequentially outputs the liquid crystal display data to a color matrix liquid crystal display panel. A controller/driver circuit for a color liquid crystal display characterized by comprising a circuit. 3. In the color liquid crystal display controller/driver circuit according to claim 1, the color separation clock generation means is reset when a horizontal clock is input, and when a data shift clock is input and T counts are made, A T-counter that outputs one pulse, an OR circuit that ORs the output of the T-counter and the horizontal clock, and is reset when the horizontal clock is input, and the output of the T-counter is branched and input. and a logic circuit that blocks input of a data shift clock to the T counter when the outputs of the two counters are input. Controller/driver circuit for color LCD display.