JPH03200282A - Image display device - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and reduce the power consumption by writing picture element data which are inputted in picture element units in buffer circuits in order, reading held data out of the buffer circuits in parallel every time picture element data of four picture elements are written in the buffer circuit, and transferring them to latch circuits with a latch clock. CONSTITUTION:The (n)-bit picture element data which are inputted in picture element units are written in the buffer circuits 41a and 41b and every time picture element data of four picture elements are written in the buffer circuits 41a and 41b, their held data are read out in parallel and transferred to the latch circuits 42a and 42b, and 43a and 43b with the latch clock. When picture element data of one line are latched in the latch circuits 42a and 42b, and 43a and 43b, the latched picture element data are read out together to a driving circuit at specific timing to drive signal electrodes for displaying. Consequently, the constitution of the circuit which generates the latch clock is simplified and the frequency of the latch clock is lowered to reduce the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display device that displays gradation on a dot matrix type display panel such as a liquid crystal, and particularly relates to an improvement in a signal electrode drive circuit.

[Prior Art] Conventionally, a signal electrode (segment electrode) drive circuit in an image display device using a dot matrix type liquid crystal display panel is configured as shown in Fig. m3.

That is, for example, 3-bit digital pixel data D1 to D3 sent from an A/D conversion circuit (not shown) is
The signal is input to buffer circuits 11a and 11b consisting of 3-bit D-type flip-flops. The buffer circuit 11a reads the pixel data DI-D3 using the clock pulse C2 and outputs it to the latch circuit 12a.
reads the pixel data DI-D3 using the Ml clock CI and outputs it to the latch circuit 12b. The above clock pulses CI and C2 are shown in FIGS. 4(a) and (b)! = As shown, these are two-phase clock pulses with the same frequency but a 180° difference in phase. The latch circuit 12a transfers the data held in the buffer circuit 11a to two-phase clock pulses CI.
, C2 and input to inverters 14a-14c via NOR circuits 13a-13c. Latch circuit 1
2b reads the data held in the buffer circuit 11b using the clock pulse C2, and the NOR circuits 15a to 15
It is input to inverters 16a to 16c via c. The output signals of the inverters 14a to 14c are 3″
N-stage latch circuit 17 with bit configuration. ~17N,
Odd-numbered latch circuits 171, 173 . ..., 17N
-1, and the output signals of inverters 16a to 16c are input to even-numbered latch circuits 17□, 17. ,...17
It is input to N.

A D-type flip-flop 18 reads a start signal STI given in synchronization with the horizontal synchronization signal using a clock pulse C1, and inputs it to the D-type flip-flop 19. This flip-flop 19 reads the input signal using the clock pulse C2 and inputs it to the shift register 20. This shift register 20 is (N/2-1)
The latch circuits 201 to 2ON/2-1 in the stages are connected in cascade, and the input signal is sequentially shifted by two-phase clock pulses CI and C2, and the signal STO is output from the latch circuit 2ON/2-1 in the final stage. is input to the D-type flip-flop 21. This flip-flop 21 reads the signal STO using the clock pulse C1 and inputs it to the reset terminal R of the RS flip-flop 22. This flip-flop 22 is set by the output signal of the flip-flop 18, and the output signal is inputted to a D-type flip-flop 24 and an AND circuit 26 via an inverter 23. The flip-flop 24 reads the input signal in synchronization with the clock pulse C2, and the D-type flip-flop 25 and the NOR circuits 13a to 13d, 15a to 1
It is human-powered by 5d.

Further, the output signal of the flip-flop 24 is transmitted together with the clock pulse C2 to the clock terminal C of the latch circuits 20+ to 2ON/2-1 via the NOR circuit 27 and the inverter 28.
It is input to Y. The flip-flop 25 reads the input signal using the clock pulse C1, and the AND circuit 2
Enter 6. The output signal of the AND circuit 26 is inputted together with the clock pulse CI to the clock terminal Cx of the latch circuits 201 to 2ON/2-1 via the NOR circuit 29 and the inverter 30. Furthermore, the above inverter 3
The output signal of 0 is input to the NOR circuits 321 to 32N/2. In addition, the NOR circuit 321 includes a flip-flop 19
The output signal of the latch circuit 20. is input to the NOR circuits 322-32N7□. -2ON7□-1 output signals are respectively input. And the above NOR circuits 321 to 32N
The output signals of 7□ are respectively output from odd-numbered latch circuits 17.
1°173, . . . , 17N-1 and even-numbered latch circuits 17□, 174. ..., 17N as a latch clock CK S l =CK S N/□. That is, the NOR circuit 32. The latch clock CKSI~CKSN,□ output from the latch circuit 17.~32N/2. ~17N, the odd number and even number are input as a pair.

FIG. 4 shows the operation timing of the conventional circuit. The operation shown in FIG. 3 will be explained below with reference to FIG. When entering a new field and receiving pixel data Dl-D3 from the A/D conversion circuit, the buffer circuit 11a
, llb, and the odd-numbered data and even-numbered data are converted into parallel data. That is, A/
When the first pixel data DI-D3 shown in FIG. 4(c) is sent from the D conversion circuit, this pixel data DI-D
3, first, the buffer circuit 1 is activated by the clock pulse C2.
It is latched to 1a. Next, when the second +7) pixels 7'-data D1 to D3 are sent, this pixel data is sent to the buffer circuit 11. latched to b. At this time, the first pixel data held in the buffer circuit 11a is latched into the latch circuit 12a by the clock pulse C1. The pixel data latched by the latch circuit 12a is read out from the latch circuit 12a by the clock pulse C2. At this time, the buffer circuit 11
The pixel data held in pixel data b is latched by the latch circuit 12b by the clock pulse C2 and output. Therefore, the latch circuit 12a.

The first pixel data and the second pixel data latched in the pixel 12b are simultaneously output at the timing of the clock pulse C2, as shown in FIGS. 4(f) and 4(g).

On the other hand, when entering the new field mentioned above, Fig. 4(d)
A start timing signal 5TI (low level) shown in is input to the flip-flop 18. The start timing signal STI is latched into the flip-flop 18 by a clock pulse CI, and further by a clock pulse c2.
As a result, it is latched by the flip-flop 19. As a result, the flip-flop 19 outputs a latch clock generating pulse shown in FIG. 4(h), which is sent to the latch circuit 20. Further, the flip-flop 22 is set by the output signal (low level) of the flip-flop 18, its output signal becomes high level, the output of the inverter 23 becomes low level, and the gate of the AND circuit 26 is closed. Further, the output signal of the inverter 23 is latched by the flip-flop 24 by the clock pulse c2, and the output signal falls from high level to low level as shown in FIG. 4(h). The period during which the output signal of the flip-flop 24 is at a low level becomes a data valid period.

As described above, when the output signal of the flip-flop 24 falls to low level, the latch circuits 12a, 12
The latch data of b is the NOR circuit 13a to 13c, 15a to
15c and inverters 14a-14c+16a-16c
The signal is then sent to the latch circuits 17a to 17N via.

Furthermore, since the low level signal output from the flip-flop 24 is latched by the flip-flop 25 by the clock pulse CI, the AND circuit 26 continues to have its gate closed, that is, the output signal is "0". held in state. While the output signal of the AND circuit 26 is held at a low level, the clock pulse C1 is applied to the NOR circuit 29 and the inverter 3 as shown in FIG. 4(j).
0, and the latch circuits 201 to 2ON7□
-1 is input. Further, the clock pulse Ct outputted from the inverter 30 is inputted to the NOR circuits 32+ to 32N/2 via the inverter 31. In a certain field, when the first clock pulse C1 is output from the inverter 31, it coincides with the timing when the latch clock generation pulse shown in FIG. 4(h) is output from the flip-flop 19, and therefore the NOR circuit 32
1 to latch clock CKS shown in FIG. 4(1) are output. When this latch clock CKS is output, the pixel data held in the latch circuit 12a is latched in the latch circuit 171, and the pixel data held in the latch circuit 12b is latched in the latch circuit 17□.

Thereafter, the latch clock generation pulse outputted from the flip-flop 19 is synchronized with the clock pulse outputted from the inverter 30.28, and the latch circuit 20.
It is sequentially shifted to 2ON/□-1. This latch circuit 2
With the shift operation of 0, ~2ON7□-3, NOR circuit 3
From 2□ to 32N7□, latch clocks CKS2 to CKS N and □ are sequentially output as shown in FIGS. 4(m) and (n). Furthermore, during this period, the pixel data DI-D3 sent from the A/D conversion circuit is sequentially sent to the buffer circuit 11a.

It is latched by latch circuits 12a and 12b via 11b. The pixel data latched by the latch circuits 12a and 12b are sent to the latch clocks CKS2 to CKS N/
□ is sequentially latched by latch circuits 173 to 17N. The 3-bit pixel data latched by each of these latch circuits 173 to 17N creates an 8-gradation driving signal, and the segment electrodes of a liquid crystal display panel (not shown) are driven for display.

[Problems to be Solved by the Invention] As described above, in the conventional image display device, the latch circuit 12
The two pixel data held in a and 12b are transferred to the latch circuit 17 by the latch clock CKS, ~CKSN5,2.
1 to 17N are latched sequentially.

That is, two pieces of pixel data are simultaneously transferred to the latch circuit by one latch clock CKS. Therefore, for N outputs, N/2 latch circuits 20, . 20□,・
...and NOR circuits 321, 32□.

... is required and the number of outputs of the drive circuit increases,
There was a problem in that the circuit also increased in proportion (by a factor of 1/2).

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an image display device that can simplify the circuit configuration and reduce the number of circuits even if the number of outputs from the drive circuit increases.

[Means and effects for solving the problem] The present invention sequentially latches pixel data in a plurality of latch circuits provided corresponding to each signal electrode of a dot matrix display panel,
In an image display device that drives the signal electrodes for display based on the latch data, n-bit pixel data input in units of one pixel is sequentially written into a buffer circuit, and pixel data for four pixels is written into this buffer circuit. Each time the pixel data is read out in parallel, the data is read out in parallel and transferred to the latch circuit using the latch clock, and when one line of pixel data is latched into the latch circuit, the latched pixel data is driven all at once at a predetermined timing. The signal is read out to a circuit and the signal electrodes are driven for display.

With the above configuration, pixel data sent pixel by pixel is sequentially written into the buffer circuit, and every time four pixels are written, it is transferred to the latch circuit in synchronization with the latch clock. Therefore, data for four pixels can be set in the latch circuit with one latch clock.

Therefore, the configuration of the circuit that generates the latch clock can be simplified, and the latch clock 1. Power consumption can be reduced by lowering the Ij wave number.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the digital pixel data DI-D3 of multiple bits, for example, 3 bits, sent from the A/D conversion circuit (not shown) at the previous stage is sent to a buffer circuit 41a consisting of a 3-bit D-type flip-flop. , 41b is manually operated. The buffer circuit 41a converts the pixel data D1 to D3 into a clock pulse C sent from a timing generation circuit (not shown).
The buffer circuit 41b reads the pixel data DI-D3 using the reference clock C1 and outputs it to the latch circuit 42H. The above clock pulse CI.

As shown in FIGS. 2(a) and 2(b), C2 is a two-phase tarok pulse having the same frequency and a 180° difference in phase. The latch circuit 42g reads the data held in the buffer circuit 41a using two-phase clock pulses CI and C2, and outputs the data to the latch circuit 43a and NOR circuits 46a to 46a.
Enter in 6c.

The latch circuit 43m latches input data using a latch clock Cl0B sent from a timing signal generation circuit 50, the details of which will be described later, and inputs the input data to the NOR circuits 44a to 44c. Further, the latch circuit 42b is connected to the buffer circuit 4.
The data held in 1b is read by the two-phase clock pulse C2, and the latch circuit 43b and the NOR circuit 47a~
Enter 47c. The latch circuit 43b latches the input data using the latch clock Cl0B and inputs it to the NOR circuits 45a to 45c. And the above NOR circuit 4
4a to 44c, 45a to 45c.

The output signals of 46a to 46c and 47a to 47c are sent to a latch circuit 48. of N stages with each stage having 3 bits via a data bus line. ~48N are sequentially input in units of four stages. This latch circuit 48. The number of constituent stages N of ~48N is
They are provided corresponding to the number of signal electrodes of the display panel, that is, the number of pixels on one horizontal scanning line.

Reference numeral 51 denotes a D-type flip-flop provided in the timing signal generation circuit 50, which reads a start signal STI given in synchronization with the horizontal synchronization signal using a clock pulse C1, and inputs it to the inverter 52. The output signal of the inverter 52 is sent to the D-type flip-flop 54 as a reset signal together with the start signal STI via the NOR circuit 53. This flip-flop 54 is
The input signal is read by the clock pulse C2 and inputted to the NAND circuit 57, and also inputted to its own input terminal I and the NAND circuit 56 via the inverter 55. Also,
A clock pulse CI is input to the NAND circuits 56 and 57. This clock pulse CI is a NAND circuit 56.5
The pulses are taken out as clock pulses CIO and C1l via inverters 58 and 59, and further inverted and taken out as clock pulses CIOB and CIIB.

Further, the signal output from the flip-flop 51 of the timing signal generation circuit 5o is inputted to the RS flip-flop 61. This flip-flop 61 is set by a signal from the flip-flop 51 and reset by a clock pulse Ctt. The output signal of the flip-flop 61 is input to a D-type flip-flop 63 via an inverter 62. This flip-flop 63 reads the input signal using the clock pulse CIOB and inputs it to the shift register 64. This shift register 64 consists of (N/4-1) stages of latch circuits 651 to 65N/4-1 connected in cascade, and converts the signal STO output from the final stage latch circuit 65N/4-1 into a D-type. input to flip-flop 66;

This flip-flop 66 reads the signal STO using the clock pulse C1l and inputs it to the flip-flop 67. This flip-flop 67 latches the human input signal using the clock pulse Cl0B and inputs it to the reset terminal R of the RS flip-flop 69 via the inverter 68. The output signal of the flip-flop 63 is inputted to the set terminal S of the flip-flop 69 via an inverter 70 .

The output signal of the flip-flop 69 is sent to the NOR circuits 71, 72 and the NOR circuits 44a to 44c, 45a to 45c, 46a to 46a as the data r valid interval signal UTI.
46c, 47a to 47c. Further, C1lI3 is manually input to the NOR circuit 71, and a clock pulse CIOB is input to the NOR circuit 72. Then, the output signals of the NOR circuits 71 and 72 are transmitted to the inverters 73 and 7, respectively.
4 to the clock terminal CX of the latch circuits 651 to 65N74-1.

Manpower is provided by CY. A flip-flop 63 and a latch circuit 65. ~65 N, ---1 output signal is
NOR circuit 751 together with the output signal of NOR circuit 71, respectively.
Latch clock CKSI = C via ~75N, -+
KSN74 and latch circuit 48. ~48
N is input in units of four. For example, the NOR circuit 75. The latch clock CKSI output from the latch circuit 4
81-484.

Next, the operation of the above embodiment will be explained with reference to the timing chart of FIG.

When a new field is entered and the start timing signal STI (low level) shown in FIG. 2(C) is sent, the output signal of the NOR circuit 53 becomes high level and the flip-flop 54 is reset. Thereafter, the start timing signal STI is latched in the flip-flop 51 by the clock pulse C2, its output signal is at a low level, and the output signal of the inverter 52 is at a high level.
The output signal of the NOR circuit 53 becomes low level, and the reset state of the flip-flop 54 is released.

The output signal of the NOR circuit 53 is maintained at a low level even after the start timing signal STI returns to a high level, and the flip-flop 54 is maintained in a state in which it can operate. Therefore, after the reset state is released, the flip-flop 54 performs an inverting operation every time the clock pulse C2 is input. For this reason, Fig. 2(e),
As shown in (f), the clock pulse C1 is applied to the NAND circuit 5.
6°57 and are taken out as inverted clock pulses CIO and C1l. These clock pulses cto, ctt are further applied to the inverter 58.5.
9 and extracted as CIOB, C1113.

Further, when the start timing signal STI is latched by the flip-flop 51, the flip-flop 61 is set by the output signal.

As a result, the output signal of the flip-flop 61 becomes high level and the output signal of the inverter 62 becomes low level, which are read into the flip-flop 63 by the clock pulse Cl0B. Therefore, the output signal of the flip-flop 63 is changed to the clock pulse CIOB as shown in FIG. 2(II).
falls in sync with

The output signal of this flip-flop 63 is sent to the shift register 64 as a latch clock generation pulse. The flip-flop 61 then outputs the clock pulse C
1l, its output signal returns to low level, the output signal of inverter 62 returns to high level, and is latched into flip-flop 63 by clock pulse Cl0B.

Furthermore, when the latch clock generation pulse is output from the flip-flop 63, the flip-flop 69 is set via the inverter 70. At this time, the low level signal output from the flip-flop 69 is used as the data valid interval signal UTI by the NOR circuits 44a to 44c, 4
5a-45c.

46a to 46c and 47a to 47c.

The pixel data sent from the A/D conversion circuit is transferred to the latch circuits 481 to 48 by the data valid interval signal UTI.
It becomes possible to transfer the information to N.

Furthermore, when the data valid interval signal UTI is output from the flip-flop 69, the clock pulse CI
IB is a NOR circuit 71. The clock pulse CIOB is extracted via the inverter 73 (FIG. 2(n)) and
is taken out via the NOR circuit 72° inverter 74 (FIG. 2(0)).

The clock pulses C11B and CIOB outputted via the inverters 73 and 74 cause the latch clock generation pulses sent from the flip-flop 63 to the shift register 64 to the latch circuits 651 to 65N/4-.
1 sequentially. As described above, the flip-flop 63 outputs a pulse for creating a latch clock and ν, and this pulse is sequentially shifted to the latch circuits 651 to 65N and 4-1, so that the NOR circuits 75+ to 75N
are sequentially selected, and the signals U, Nochikuro, Tsuku CS K + to C5KN/4 shown in FIGS. 2(p) to (r) are output.

On the other hand, when the new field is entered and pixel data D1 to D3 are sent from the A/D conversion circuit, the buffer circuits 41a, 41b and the NOR circuits 42a, 42b, 4
3a and 43b convert the first to fourth pixel data into parallel data. That is, the first pixel data Dl-1D3 shown in FIG. 2(g) is output from the A/D conversion circuit.
When the pixel data DI-D3 is sent, first, this pixel data DI-D3 is latched by the buffer circuit 41a by the clock pulse C2. Next, when the second pixel data DI-D3 is sent, this pixel data is latched into the buffer circuit 41b by the clock pulse C1. At this time, the first pixel data held in the buffer circuit 41a is latched into the latch circuit 42a by the clock pulse C1. The pixel data latched by the latch circuit 42a is read out from the latch circuit 42a by the clock pulse C2. At this time, the pixel data held in the buffer circuit 41b is transferred to the latch circuit 42 by the clock pulse C2.
It is latched to b and output. Therefore, the latch circuit 42
The first pixel data and the second pixel data latched in a and 42b are simultaneously outputted to the latch circuit 43a by the clock pulse Cl0B output from the timing signal generation circuit 50.

43b.

Further, when the second pixel data latched in the buffer circuit 41a is sent to the buffer circuit 41b, the A/D
The third pixel data sent next from the conversion circuit is latched into the buffer circuit 41a by the clock pulse C2. Next, when the fourth pixel data is sent, this pixel data is latched into the buffer circuit 41b by the clock pulse C1. At this time, pixel data No. 3 and 1 held in the buffer circuit 41a is latched into the latch circuit 42a by the clock pulse CI.

The pixel data latched by the latch circuit 42a is read out from the latch circuit 42a by the clock pulse C2. At this time, the 4th and 11th pixel data held in the buffer circuit 41b is transferred to the latch circuit 42b and output by the clock pulse C2. Therefore, the third pixel data latched in the latch circuits 42a and 42b and the fourth
The pixel data of the numbers are simultaneously output as shown in FIGS. 2(i) and (k). At this time, the latch circuit 43a.

43b holds the first and second pixel data. That is, since the clock pulse CLOB is output at twice the period of the clock pulse C1, at the time when the third and fourth pixel data are latched in the latch circuits 42a and 42b, the first pixel data is outputted in the latch circuits 43a and 43b. pixel data of ``day and 2 and 1'' are held.

In the above state, the latch clock CKSI shown in FIG. 2(p) is output from the NOR circuit 75□, and the latch clock CKSI shown in FIG.
The first and second pixel data held in 3a and 43b are transferred to NOR circuits 44a to 44c and 45a to 45c.
is transferred to the latch circuit 481.48□ through the latch circuit v642a.

The third and fourth pixel data held in 42b are transferred to latch circuits 483 and 484 via NOR circuits 46a to 46c and 47a to 47c.

Thereafter, similarly, pixel data sent from the A/D conversion circuit is transferred four by four to the latch circuits 48° to 48N in synchronization with the latch clocks CICS1 to CKSN and 4. Then, when one line of pixel data is set in the latch circuits 481 to 48N, the pixel data is collectively transferred to the signal electrode drive circuit (
(not shown), and the signal electrodes of the display panel are driven for display.

On the other hand, when the latch clock generation pulse outputted from the flip-flop 63 is sequentially shifted in the shift register 64 and shifted to the final stage latch circuit N4, the output signal 5TO (FIG. 2(d)) is It is sent to flip-flop 66 and latched in synchronization with clock pulse C1l.

As a result, the output of the flip-flop 66 becomes low level, which is latched by the flip-flop 67 by the clock pulse Cl0B, and the flip-flop 69 is reset via the inverter 68 by the latch output. As a result, the data valid period signal UTI output from the flip-flop 69 returns to high level, and the NOR circuit 4
4a-44c, 45a-45c, 46a-46c.

Close the gates 478-47c. Furthermore, when the data valid interval signal UTI reaches level 11, the NOR circuit 7
1. Close the gate of 72, Kurosokunokurusu CIIB
, CIOB is output from NOR circuit 71.72! stop. Thereafter, when the start timing signal STI is sent in the next field, the above-described operation is repeated.

Although the above embodiments have been explained using a liquid crystal display panel as an example, the present invention is not limited thereto, and can be applied to an image display device equipped with a dot matrix type display panel.

[Effects of the Invention] As detailed above, according to the present invention, pixel data is sequentially latched in a plurality of latch circuits provided corresponding to each signal electrode of a dot matrix display panel, and pixel data is latched based on the latched data. In an image display device that drives the signal electrodes for display, pixel data input pixel by pixel is sequentially written into a buffer circuit, and every time pixel data for four pixels is written into this buffer circuit, the retained data is written in parallel. Since the data is read out and transferred to the latch circuit using the latch clock, data for four pixels can be set in the latch circuit with one latch clock. Therefore, the number of elements in the latch clock generation circuit can be reduced to half of the conventional one, and the circuit configuration can be simplified, which can be particularly effective when the number of signal electrodes in the display panel is large.

Furthermore, since the frequency of the latch clock is reduced to half that of the conventional one, it is possible to reduce power consumption and provide a margin for operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment,
FIG. 3 is a block diagram showing the configuration of a conventional liquid crystal drive circuit, and FIG. 4 is a timing chart for explaining the operation of FIG. 3. 41a 41b--buffer circuit, 42a. 42b, 43a, 43b--latch circuit, 50--
Timing signal generation circuit, 481-48 N... Latch circuit, 64... Shift register.

Claims (1)

[Claims] In an image display device, pixel data is sequentially latched in a plurality of latch circuits provided corresponding to signal electrodes of a dot matrix display panel, and the signal electrodes are driven for display based on the latch data. a buffer circuit capable of holding pixel data; a data writing means for sequentially writing n-bit pixel data input in units of one pixel into the buffer circuit to hold four pixels;
reading means for reading out pixel data for four pixels held in the buffer circuit in parallel to a data bus line; and a plurality of latch clocks having different phases sequentially at a cycle in which the pixel data for four pixels is read into the buffer circuit. a multi-stage latch circuit that sequentially latches pixel data for four pixels sent through the data bus line using a latch clock output from the latch clock generation means; An image display device comprising: reading means for reading out pixel data latched in a latch circuit all at once to a drive circuit at a predetermined timing.