JPS632157B2 - - Google Patents

Info

Publication number
JPS632157B2
JPS632157B2 JP56178802A JP17880281A JPS632157B2 JP S632157 B2 JPS632157 B2 JP S632157B2 JP 56178802 A JP56178802 A JP 56178802A JP 17880281 A JP17880281 A JP 17880281A JP S632157 B2 JPS632157 B2 JP S632157B2
Authority
JP
Japan
Prior art keywords
integrated circuit
insulating substrate
motherboard
resistant film
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56178802A
Other languages
Japanese (ja)
Other versions
JPS5879799A (en
Inventor
Yoshio Nakatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17880281A priority Critical patent/JPS5879799A/en
Publication of JPS5879799A publication Critical patent/JPS5879799A/en
Publication of JPS632157B2 publication Critical patent/JPS632157B2/ja
Granted legal-status Critical Current

Links

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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)

Description

【発明の詳細な説明】 本発明は高密度実装が可能で、信頼性、特に耐
湿特性に優れた混成集積回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit that can be mounted at high density and has excellent reliability, especially moisture resistance.

近年の実装技術の発展はめざましく、安価で、
小型化、高信頼性の要求が高くなつているが、一
定絶縁基板にのせられる電子部品の点数には限界
がある。したがつて高密度化するには絶縁基板の
両面に電子部品を搭載する方法がとられている
が、両面の接続に問題があり、価格や信頼性にお
いて好ましくない。
The development of mounting technology in recent years has been remarkable, and it is inexpensive and
Although there are increasing demands for miniaturization and high reliability, there is a limit to the number of electronic components that can be mounted on a given insulating substrate. Therefore, a method of mounting electronic components on both sides of an insulating substrate has been adopted to increase the density, but there is a problem in connecting both sides, which is undesirable in terms of cost and reliability.

本発明は、中央に折り曲げることが可能なスリ
ツトのはいつた絶縁基板に付設されかつパターン
を有する導体を形成した耐熱フイルムに電子部品
を搭載することによつて構成した集積回路を、前
記耐熱フイルムを折り曲げない状態で、樹脂被覆
した後、前記集積回路を前記スリツトから2つ折
りに折り曲げ、この折り曲げた集積回路をマザー
基板の貫通孔に挿入して、この折り曲げた集積回
路が元の折り曲げない状態に戻ろうとする復元力
を利用してこの集積回路の端部をマザー基板に接
続して、良好な接続状態を得るとともに、高密度
化が容易でしかも信頼性特に耐湿性に優れた混成
集積回路を得ようとするものである。
The present invention provides an integrated circuit constructed by mounting electronic components on a heat-resistant film attached to an insulating substrate with a bendable slit in the center and formed with a patterned conductor. After coating the integrated circuit with resin without bending it, the integrated circuit is folded in half from the slit, and this folded integrated circuit is inserted into the through hole of the motherboard, so that the folded integrated circuit returns to its original unfolded state. The ends of this integrated circuit are connected to the motherboard by utilizing the restoring force of the integrated circuit to return to the original state, and a good connection is obtained.The hybrid integrated circuit is easy to increase density and has excellent reliability, especially moisture resistance. It is an attempt to obtain.

(実施例) 以下、本発明の実施例の混合集積回路の製造方
法について図面を参照しながら詳細に説明する。
(Example) Hereinafter, a method for manufacturing a mixed integrated circuit according to an example of the present invention will be described in detail with reference to the drawings.

(実施例 1) 第1図に示すようにスリツト1aのはいつた紙
フエノール基板からなる絶縁基板1とパターンを
有する導体を形成したポリイミドの耐熱フイルム
2を粘着テープを用いて貼り合わせた。次にチツ
プ抵抗、チツプコンデンサ、ミニモールド化され
たトランジスタ、ICなどからなる集積回路3を
前記耐熱フイルム2上に搭載し、マザー基板との
接続端子をマスキングテープでマスキングした
後、キシロール、メチルエチルケトンの混合溶剤
45wt%を含む粘度が70CPSのエポキシ樹脂をス
プレーガンにて塗布し、80℃で30分硬化させ、厚
みが50μmの被覆樹脂層4を形成した後、マスキ
ングテープをはがした。
(Example 1) As shown in FIG. 1, an insulating substrate 1 made of a paper phenol substrate with slits 1a and a polyimide heat-resistant film 2 on which a patterned conductor was formed were bonded together using an adhesive tape. Next, an integrated circuit 3 consisting of a chip resistor, a chip capacitor, a mini-molded transistor, an IC, etc. is mounted on the heat-resistant film 2, and the connection terminals with the motherboard are masked with masking tape. mixed solvent
An epoxy resin containing 45 wt% and having a viscosity of 70 CPS was applied with a spray gun and cured at 80° C. for 30 minutes to form a coating resin layer 4 with a thickness of 50 μm, and then the masking tape was removed.

(実施例 2) 実施例1と同様に、スリツト1aのはいつたガ
ラスエポキシ基板からなる絶縁基板1とパターン
を有する導体を形成したポリイミドの耐熱フイル
ム2を2液性で無溶剤タイプのエポキシ樹脂系接
着剤を用いて貼り合わせた。次に、実施例1と同
一の集積回路3を前記耐熱フイルム2上に搭載
し、マザー基板との接続端子をマスキングテープ
でマスキングした後粘度が480CPSで無溶剤タイ
プのウレタン変性アクリル樹脂をデイツプにて塗
布し、紫外線硬化させ、厚みが250μmの被覆樹脂
層4を形成した後、マスキングテープをはがし
た。
(Example 2) As in Example 1, an insulating substrate 1 made of a glass epoxy substrate with slits 1a and a polyimide heat-resistant film 2 on which a patterned conductor was formed were mixed with a two-component, solvent-free epoxy resin. It was attached using adhesive. Next, the same integrated circuit 3 as in Example 1 was mounted on the heat-resistant film 2, and after masking the connection terminals with the motherboard with masking tape, a solvent-free urethane-modified acrylic resin with a viscosity of 480 CPS was used as a dip. After coating and curing with ultraviolet rays to form a coating resin layer 4 having a thickness of 250 μm, the masking tape was removed.

次に実施例1,2で得られたブロツク化した集
積回路3の載つた絶縁基板1をそのスリツト1a
から折り曲げ、この2つ折りの絶縁基板を第2図
に示すようにマザー基板5の貫通孔に挿入し、ハ
ンダ6にて接続した。これにより高密度化が実現
できるとともに、信頼性、特に耐湿性に優れた混
成集積回路が得られた。
Next, the insulating substrate 1 on which the block integrated circuit 3 obtained in Examples 1 and 2 was mounted was inserted into the slit 1a.
The two-folded insulating substrate was inserted into the through hole of the motherboard 5 as shown in FIG. 2, and connected with solder 6. This made it possible to achieve high density and to obtain a hybrid integrated circuit with excellent reliability, especially moisture resistance.

本発明において使用される絶縁基板は、フエノ
ール基板、紙フエノール基板、ガラスエポキシ基
板、紙ポリエステル基板、アルマイト処理された
アルミ基板など通常絶縁基板として使用されてい
るもので、限定されるものではない。またスリツ
トのはいつた絶縁基板を用いるのは、180度折り
曲げることによつて、接続、絶縁性に優れ、高密
度化が可能な両面電子部品搭載の集積回路が得ら
れる為である。導体はホトレジストまたはエツチ
ングによつて形成し、耐熱フイルムは電子部品と
導体を接続するのに必要なハンダデイツプまたは
ハンダリフローの温度に耐えるポリイミドが望ま
しく、耐熱フイルムと絶縁基板は熱硬化性樹脂ま
たは両面粘着テープを用いて貼り合わせることが
できる。
The insulating substrate used in the present invention is not limited to those commonly used as insulating substrates, such as a phenol substrate, a paper phenol substrate, a glass epoxy substrate, a paper polyester substrate, and an alumite-treated aluminum substrate. Furthermore, the reason why an insulating substrate with slits is used is that by bending it 180 degrees, an integrated circuit with electronic components mounted on both sides, which has excellent connection and insulation properties and can be increased in density, can be obtained. The conductor is formed by photoresist or etching, the heat-resistant film is preferably polyimide that can withstand the solder dip or solder reflow temperatures required to connect the electronic components and the conductor, and the heat-resistant film and insulating substrate are made of thermosetting resin or double-sided adhesive. Can be attached using tape.

ところで搭載する電子部品は、チツプ化された
抵抗、コンデンサ、ミニモールド化されたトラン
ジスタ、ICなどが望ましいが、トランジスタ、
ICなどのミニモールドされた電子部品はリード
とデバイス間のパスが短かく、接着剤で仮止め
し、ハンダデイツプまたはハンダリフローによつ
て、導体との接続を行なつた場合、熱膨張係数が
1桁異なるため熱衝撃によつてリード端子とモー
ルド樹脂の界面の信頼性が低下し、信頼性特に耐
湿性が著しく低下する。また回路定数を一定にす
るために、チツプ抵抗、チツプコンデンサをレー
ザーを用いて機能トリミングを行なつたまま使用
すると、結露した場合には特性値が不安定になる
ので樹脂被覆する必要がある。
By the way, the electronic components to be mounted are preferably chipped resistors, capacitors, mini-molded transistors, ICs, etc.
Mini-molded electronic components such as ICs have a short path between the leads and the device, so if they are temporarily fixed with adhesive and connected to a conductor by solder dip or solder reflow, the coefficient of thermal expansion is 1. Because of the order of magnitude difference, the reliability of the interface between the lead terminal and the molded resin decreases due to thermal shock, and the reliability, particularly the moisture resistance, decreases significantly. Furthermore, if chip resistors and chip capacitors are used with their functions trimmed using a laser in order to keep circuit constants constant, their characteristic values will become unstable if condensation occurs, so they must be coated with resin.

樹脂被覆材料としては、エポキシ樹脂、アクリ
ル樹脂、シリコーン樹脂、ポリブタジエン樹脂な
どがあり、これらを変性した無溶剤タイプのもの
や、必要に応じてトルオール、キシロール、酢酸
ブチル、メチルエチルケトン、ブタノールなどの
溶剤を添加したタイプのものがある。
Resin coating materials include epoxy resins, acrylic resins, silicone resins, and polybutadiene resins, and there are solvent-free types that have been modified from these resins, as well as solvent-free types that have been modified with these resins, as well as solvent-free types that are coated with toluene, xylol, butyl acetate, methyl ethyl ketone, butanol, etc. as necessary. There are some added types.

また、樹脂被覆層の厚みは、絶縁基板にもとの
フラツトな状態にもどろうとする復元力を持たせ
る必要性、耐湿性から10μm以上が望ましいが、
1mm以上になると折り曲げたときにクラツクが生
じるので好ましくない。
In addition, the thickness of the resin coating layer is desirably 10 μm or more due to the need to provide the insulating substrate with a restoring force to return to its original flat state and moisture resistance.
If it exceeds 1 mm, cracks will occur when bending, which is undesirable.

被覆方法としては、集積回路の載つた絶縁基板
を折り曲げない状態で被覆することが重要であ
り、この状態で絶縁基板をマザー基板に挿入接続
した時に、貫通孔と絶縁基板との間に隙間が生じ
て、位置ずれを生じることがあつても、絶縁基板
にもとのフラツトな状態にもどろうとする復元力
があるため、良好な接続が可能である。しかし、
折り曲げた後にデイツプまたは粉体塗装によつて
被覆すると、絶縁基板に復元力がなくなるので、
ハンダ付けを行なつても、第3図のように接続不
良の要因となる。したがつて、被覆方法としては
折り曲げない状態でデイツプやスプレーまたはス
クリーン印刷によつて塗布するのが良い。
As for the coating method, it is important to cover the insulating substrate on which the integrated circuit is mounted without bending it, and when the insulating substrate is inserted and connected to the motherboard in this state, there is no gap between the through hole and the insulating substrate. Even if this occurs, a good connection can be made because the insulating substrate has a restoring force to return to its original flat state. but,
If the insulating substrate is coated with dip or powder coating after bending, the insulating substrate will lose its restoring force.
Even if soldering is performed, it may cause a connection failure as shown in FIG. Therefore, it is preferable to apply the coating without bending it by dip, spray or screen printing.

以上本発明によれば、絶縁基板を折り曲げない
状態で耐熱フイルムを含めて樹脂被覆した後、中
央から2つ折にすることによつて元の状態に戻ろ
うとする絶縁基板の復元力を得ることができ、マ
ザー基板の貫通孔と絶縁基板の端部を密着させる
ことができ、位置ずれも生じないのでマザー基板
との接続が非常に良好になるとともに、混成集積
回路の高密度化が容易となり、しかも信頼性特に
耐湿性に優れた混成集積回路が得られるに至つ
た。
As described above, according to the present invention, it is possible to obtain the restoring force of the insulating substrate to return to its original state by coating the insulating substrate with a resin including a heat-resistant film without bending it, and then folding it in half from the center. This allows the through-hole of the motherboard and the edge of the insulating board to be brought into close contact with each other, and there is no misalignment, resulting in a very good connection with the motherboard and making it easier to increase the density of hybrid integrated circuits. Moreover, a hybrid integrated circuit with excellent reliability, particularly moisture resistance, has been obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本発明の実施例を示す断
面図、第3図は折り曲げ後に被覆した時の接続不
良を示す断面図である。 1…絶縁基板、1a…スリツト、2…耐熱フイ
ルム、3…集積回路、4…被覆樹脂層、5…マザ
ー基板、6…ハンダ。
FIGS. 1 and 2 are cross-sectional views showing an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing a connection failure when covering after bending. DESCRIPTION OF SYMBOLS 1...Insulating substrate, 1a...Slit, 2...Heat-resistant film, 3...Integrated circuit, 4...Coating resin layer, 5...Mother board, 6...Solder.

Claims (1)

【特許請求の範囲】[Claims] 1 中央に折り曲げることが可能なスリツトのは
いつた絶縁基板に付設されかつパターン有する導
体を形成した耐熱フイルムに電子部品を搭載する
ことによつて構成した集積回路を、前記耐熱フイ
ルムを折り曲げない状態で、樹脂被覆した後、前
記集積回路を前記スリツトから2つ折りに折り曲
げ、この折り曲げた集積回路をマザー基板の貫通
孔に挿入してこの折り曲げた集積回路が元の折り
曲げない状態に戻ろうとする復元力を利用してこ
の集積回路の端部を前記マザー基板に接続する混
成集積回路の製造方法。
1. An integrated circuit constructed by mounting electronic components on a heat-resistant film that is attached to an insulating substrate with a bendable slit in the center and formed with a patterned conductor, with the heat-resistant film not being bent. After coating with resin, the integrated circuit is folded in half through the slit, and the folded integrated circuit is inserted into a through hole of the motherboard, and the folded integrated circuit is restored to its original unbent state. A method of manufacturing a hybrid integrated circuit in which an end of the integrated circuit is connected to the motherboard using force.
JP17880281A 1981-11-06 1981-11-06 Method of producing hybrid integrated circuit Granted JPS5879799A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17880281A JPS5879799A (en) 1981-11-06 1981-11-06 Method of producing hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17880281A JPS5879799A (en) 1981-11-06 1981-11-06 Method of producing hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS5879799A JPS5879799A (en) 1983-05-13
JPS632157B2 true JPS632157B2 (en) 1988-01-18

Family

ID=16054898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17880281A Granted JPS5879799A (en) 1981-11-06 1981-11-06 Method of producing hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5879799A (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4812556B1 (en) * 1969-05-27 1973-04-21
JPS4819148B1 (en) * 1970-10-12 1973-06-11
JPS4822154B1 (en) * 1970-09-07 1973-07-04
JPS4822747B1 (en) * 1970-12-10 1973-07-09
JPS5225264A (en) * 1975-08-21 1977-02-25 Matsushita Electric Ind Co Ltd Hybrid miniature parts
JPS5426671B2 (en) * 1976-02-26 1979-09-05
JPS57193094A (en) * 1981-05-18 1982-11-27 Matsushita Electric Ind Co Ltd Electronic circuit part and method of mounting same
JPS6011809A (en) * 1983-06-30 1985-01-22 Ricoh Co Ltd Auto focusing method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4812556U (en) * 1971-06-21 1973-02-12
JPS4819148U (en) * 1971-07-13 1973-03-03
JPS4822154U (en) * 1971-07-21 1973-03-13
JPS5124520Y2 (en) * 1971-07-23 1976-06-23
JPS5228067U (en) * 1975-08-20 1977-02-26
JPS5279565U (en) * 1975-12-12 1977-06-14
JPS5426671U (en) * 1977-07-26 1979-02-21
JPS5833708Y2 (en) * 1978-10-02 1983-07-28 松下電器産業株式会社 flexible printed circuit board
JPS5565890U (en) * 1978-10-30 1980-05-07
JPS5834770Y2 (en) * 1978-12-25 1983-08-04 松下電器産業株式会社 printed circuit board equipment

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4812556B1 (en) * 1969-05-27 1973-04-21
JPS4822154B1 (en) * 1970-09-07 1973-07-04
JPS4819148B1 (en) * 1970-10-12 1973-06-11
JPS4822747B1 (en) * 1970-12-10 1973-07-09
JPS5225264A (en) * 1975-08-21 1977-02-25 Matsushita Electric Ind Co Ltd Hybrid miniature parts
JPS5426671B2 (en) * 1976-02-26 1979-09-05
JPS57193094A (en) * 1981-05-18 1982-11-27 Matsushita Electric Ind Co Ltd Electronic circuit part and method of mounting same
JPS6011809A (en) * 1983-06-30 1985-01-22 Ricoh Co Ltd Auto focusing method

Also Published As

Publication number Publication date
JPS5879799A (en) 1983-05-13

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