JPS63215265A - Horizontal synchronizing pll circuit - Google Patents

Abstract

PURPOSE:To improve the stability of a horizontal synchronizing PLL circuit using a gate circuit type phase comparator by detecting a code from a frequency divider in the PLL circuit for a prescribed period before and after a low frequency signal period such as a vertical synchronizing signal or the like so as to generate a pseudo horizontal synchronizing signal thereby compensating a composite synchronizing signal. CONSTITUTION:The pseudo horizontal synchronizing signal generator 105 detects a code from a frequency divider 102 to generate a pseudo horizontal synchronizing signal. A signal selector 108 selects a pseudo horizontal synchronizing signal E when the level of an output signal G of a (T1+T2) detector 109 is at logical 1 and selects a composite synchronizing separator signal F when the signal G is at logical 0. The output signal B is inputted to a phase comparator 103 and subjected to phase comparison with a frequency division signal A. Thus, the rate of levels 0, 1 in the output of a phase comparator 103 is made stable even during the low frequency signal period such as a vertical synchronizing signal and then the output D of the low pass filter 104 is stable. Then the disturbance of the picture is decreased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a horizontal synchronization PLL used in television image equipment, etc.
Regarding circuits.

[Conventional technology]

As portable televisions become more popular, various horizontally synchronized PLL circuit techniques have been disclosed to ensure image stabilization.

Among them, the following are the phase comparators.

That is, the horizontal synchronization signal frequency (hereinafter abbreviated as r1. f
The oscillation signal of the voltage controlled oscillator, which oscillates at N times of ++ = l 5750 HZ), is divided into 1/N and the PLL
In the lock tooth, a frequency divider is used to generate a frequency-divided signal A having the same frequency as f++, and a gate circuit is used as a phase comparator to gate the passage of the frequency-divided signal A using a composite synchronous separation signal B. It is something to do.

Examples of the same gate circuit are shown in Figure 2 (2) and Figure 2 (b).
The following are possible. In FIG. 2(a), 201 C-
The frequency-divided signal A is gated by the composite synchronous separation signal B using an analog switch having a MOS-FET configuration. In FIG. 2(b), 202 NΔAND and NOR gates provide
Gating the frequency divided signal with the composite synchronization signal 13,
3 C-MOS-FETf7) pair ON/OFF F
-11-ru. In the tt gate circuit as well, when the composite synchronizing signal B is "1", the logic level corresponding to the frequency division signal appears at the output C, and when it is "0", it becomes a high impedance state.

JP-A-87475 discloses a gate circuit type phase comparator using an analog switch, as shown in FIG. 2(a), and explains its usefulness. In other words, the conventional synchronous 1'LL circuits used in portable televisions, for example, have been made monolithic due to the demand for smaller products and lower power consumption, and moreover, the 011MO5 configuration has been designed, and the phase comparator used there As a device, a digital phase comparator (consisting of a plurality of RS radii) as disclosed in Utility Model Application Laid-Open No. 61-07235 is generally used. However, since the in-phase comparator responds to the edges of the signal, its noise resistance is extremely poor. On the other hand, the gate circuit type phase comparator does not respond to the edges of the signal, but takes in the pulse width of the signal as phase comparison information, and therefore has relatively good noise resistance.

[Problem that the invention seeks to solve]

However, the gate circuit type phase comparator of the prior art has the following problems. This will be explained based on FIG.

In FIG. 3, B is a composite synchronization separation signal, and A is a division signal from a frequency divider, the duty of which is 50%.

C is the output signal of the gate circuit type phase comparator, which is shown as a solid line in the figure. D is a signal obtained by filtering C with a low-pass filter, and is indicated by a broken line in the figure. As the voltage controlled oscillator, for example, one shown at 101 in FIG. 1 can be considered. The phase comparison signal, which is limited to a low frequency by the low-pass filter 104 and converted into a DC signal, is applied to the varicap diode Cv, and the oscillation frequency of the voltage-controlled oscillator 101 is adjusted by rJy4. As the applied voltage increases, the capacitance of the varicap diode Cv decreases, so the oscillation frequency increases as will be described later. Therefore, in the stable state of the PLL, the composite synchronous separation signal 3 has a phase relationship such that it gates the falling edge trigger of the frequency divided signal A in the phase comparator. In FIG. 3, a normal horizontal synchronizing signal 1111 (during the period in which images are superimposed)
Between, the pulse width of the composite synchronization signal B is stable, and the phase comparison output C of the frequency-divided signal A gated thereby
The ratio between rlJ and "0" is also constant, and therefore the low-pass filter output is also stable as shown at 302. However, between the vertical pulses 1111, the pulse width of the composite synchronizing signal B becomes wider than normal, so the ratio of rlJ, "0" in the phase comparator output C is disturbed. In this example "0"
is dominant, so the low-pass filter output has a voltage level lower than normal as shown in 303, and therefore the frequency-divided signal A is out of phase with the original signal (shown by the broken line). This causes the low-pass filter output to vary accordingly. This tendency does not recover even during the equivalent pulse period after the end of the vertical pulse, and may extend to the beginning period of the image.

In this case, when displaying an image, the upper part of the screen becomes distorted, and a normal image cannot be provided.

Also, even in the normal horizontal synchronization signal period, like 301,
Even if a pulse with a wider pulse width than the original synchronizing pulse shown by the broken line is mixed in as noise, it will be gated by that signal and the signal C output from the phase comparator will be "0" or "1". '' is disturbed, the low-pass filter output fluctuates as shown in 305, and as a result, the frequency-divided signal A has a phase shift. (Originally the position of the broken line) In this case, image disturbance occurs in the corresponding part of the image.

The present invention has been made in view of the problems of the prior art as mentioned above, and its purpose is to provide a horizontal period PLL circuit using a gate circuit type phase comparator.
An object of the present invention is to provide a horizontally open 1υl PLL circuit capable of suppressing image disturbances caused by instability of a phase comparator output when vertical pulses or wide pulses are mixed.

[Means for solving problems]

In order to achieve the above object, the present invention (11a)
a voltage controlled oscillator that oscillates at N times the horizontal synchronizing signal frequency; b) dividing the oscillation signal of the voltage controlled oscillator into l/N;
C) a frequency divider that generates the divided signal A; C) a pseudo-horizontal synchronization signal generator that detects the code of the frequency divider and generates a pseudo-horizontal synchronization signal E near the original time position; and d) composite. C) an integrator that integrates the synchronization separation signal F to detect a low frequency period; and C) the low frequency period T and the periods T before and after it;
a signal selector that selects the pseudo-horizontal synchronization signal E, selects the composite synchronization separation signal F in periods other than T1 and T, and generates a composite signal B; A horizontal synchronization PLL circuit is constituted by a phase comparator consisting of a gate circuit for gating the passage of A, and g) a low-pass filter for converting the output of the position comparator into a current.

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of a horizontal synchronous PLL circuit according to the present invention. 101 is a voltage controlled oscillator, which has a high resistance R for feedback.
1 inverter 11O, inductance L1 capacitor C
l % ct, cs, and varicap diode C
Consists of v. The oscillator is of the Kolpibutsu type, and its oscillation frequency is fvc. It is given in free. The varicap diode Cv is supplied with a phase comparison voltage converted into a direct current by a low-pass filter 104 via a high resistance R1. As the applied voltage increases, Cv decreases and therefore the oscillation frequency rvco increases.

102 is a frequency divider. This is an 8-bit counter that counts the oscillation signal fvco of the voltage controlled oscillator 101. 113 is a decoder, and the counter 111
160" code is detected. 114 is an SR latch, and when the decoder 113 detects the r160J code, the fvc.

generates a reset pulse with a width determined by
Reset 11. In other words, the counter 111 is 160
It is a forward counter. 112 is toggle 1”/I” (1”/
F=flip-flop), S R latch 114
The reset signal generated from the above is frequency-divided by l/2 to create a frequency-divided signal with a duty of 50%. Therefore, l) When L is in the locked state, the frequency of the divided signal A is "6".
Since it matches I+, r v co = 160 X
2XrA=320Xru=320X15750=:5,04 (MIIZ).

103 is a gate circuit type phase comparator, and frequency divider 1
A phase comparison signal C is generated by comparing the phases of the frequency-divided signal A from 02 and a composite synchronous separation signal B selected by a signal selection circuit to be described later. The configuration of the phase comparator 103 may be of the type shown in FIG.

104 is a low-pass filter that converts the phase comparison signal C into a direct current and generates a phase comparison voltage for controlling the oscillation frequency of the voltage controlled oscillator 101.

105 is a pseudo-horizontal synchronizing signal generator, and frequency divider 10
2 code is detected and a pseudo horizontal synchronization signal is generated. A detailed example of the circuit configuration is shown in FIG. 4, and the operation will be explained with reference to the time chart of FIG.

First, in the frequency divider 102, the frequency divided signal A falls within the pulse width of the composite synchronous separation signal F when the PLL is in the locked state as described above. In this embodiment, by appropriately selecting the values of the eight elements and inductance that make up the voltage controlled oscillator 101, the falling edge of the divided signal A is placed in the middle of the pulse of the composite synchronous separation signal F, as shown in FIG. It is assumed that the steady phase error of the PLL has been adjusted. Therefore, Kara/ri1
As shown in FIG. 6, two reset pulses from the SR latch 114 are generated during the horizontal synchronization period.
One of them is in the middle of the pulses of the composite synchronous signal nt times the signal. Further, the counter 111 periodically repeats the code "0" to r150J every time the reset pulse 114 is input. In the stable state of the PLL, the composite synchronous separation signal F
The horizontal period pulse width T ++ in the middle is T ++ = 4, 76 μS = 24 X 1 /
f v c.

Therefore, from the code r148J of the counter 111,
If a pulse is generated during the rllJ period (however, during the period in which the falling edge of the frequency divided signal is interposed), a signal pseudo-equivalent to the horizontal synchronizing signal can be obtained.

Now, in FIG. 4, 401 is a decoder that detects the hood "11" of the counter 111, and 402 is a code r14.
This is a decoder that detects 7J.

403 is a composite gate, which selects "V..." and generates a clock pulse when the code of the counter 21 becomes rlLJ, r147J. 404 is a toggle F/F, which outputs the output signal of SR Labuti 114. The clock is set by the output signal of the gate 403.The Q output of the toggle F:/F404 has A=r as shown in FIG.
In lJ, the code of Kahn ivy 111 is from r148J to A
= "0" and the code of the counter 111 generates a pseudo periodic signal E having a pulse width up to "11". 10G is C,・R
This is an integrator consisting of a comparator consisting of two time constant circuits of 3 and R1 and R4, and two imparks of 115. As shown in FIG. 7, only the vertical signal portion of the composite synchronous separation signal F is frequency separated and outputted from the integrator 106.

109 detects the low frequency period T (output pulse width of the integrator 106) and the period T before and after it (T, +Tt)
It is a detector. A detailed example of the circuit configuration is shown in FIG.

FIG. 7 is the time chart. In Figure 5, 5
01 is a differentiator for differentiating the integrator output 106, and generates, at the leading edge of the signal 106, a differential pulse having a width of 172 cycles to the frequency-divided signal. 502 is a 9-bit counter,
The frequency-divided signal A is counted as a clock signal, and is reset by the previous differential pulse 501. Since the digital signal 501 generates the period of the vertical periodic signal, the color/digital signal 502 operates as a 262-base or 263-base counter in each field of the television. The time chart in FIG. 7 is for operation in 263 base. 503 is a decoder that detects code "8" of counter 502, 504 is code r2
This is a decoder that detects 58J. Decoder 503.5
The output of 04 and the frequency-divided signal A are ANDed at a composite gate 605 to generate a clock pulse. 506 and toggle F/['', the clock pulse 505 is used as a toggle signal, and the signal 501 is used as a set signal.As a result, the Q output of toggle F/F 50G has T+ +T,
A signal G with a time width of is output.

108 is a signal selector, (T, +Tt) detector 109
When the output signal G is "1", the pseudo horizontal synchronization signal E is selected, and when it is "0", the composite synchronization separation signal I? Select. The output signal is B, which is input to the phase comparator 103,
The phase is compared with the frequency divided signal A.

Fig. 8 does not show the time chart of Fig. 1. Signal selector 1
The output signal B of 08 is a pseudo-horizontal periodic signal E during the (T+ +Tt) period, and is a composite synchronous signal 111 during other periods.
1 (consisting of the signal F, even during a low frequency signal period such as a vertical synchronization signal, r at the output of the phase comparator 103
The ratio between OJ and rlJ is stable, and therefore the output of the low-pass filter 104 is also stable. Therefore, image distortion is reduced.

(Effects of the Invention) According to the present invention, during a period of a low frequency signal such as a vertical synchronization signal, a code in a frequency divider in a PLL circuit is detected during a certain period including a period before and after the period of a low frequency signal such as a vertical synchronization signal, and a pseudo horizontal By generating a synchronization signal and compensating for the composite synchronization signal, it is possible to improve the stability of the horizontal synchronization PLL circuit using a gate circuit type phase comparator.As a result, image equipment such as televisions with reduced image disturbance can be improved. Furthermore, as explained above, since signal processing is done digitally, it is easy to make the circuit monolithic.

[Brief explanation of the drawing]

Figure 1...Horizontal synchronization according to the present invention 1) LL circuit configuration diagram Second nut...(a), (b)...Gate circuit type phase comparator circuit diagram Figure 3...・Time chart diagram of conventional horizontal synchronization PLL circuit Figure 4...Configuration diagram of pseudo horizontal synchronization signal generator Figure 5・
...Configuration diagram of (TI +Tt) detector Fig. 6...Time chart in Fig. 4 Fig. 7...Time chart in Fig. 6 Fig. 8...Time chart in Fig. 1 101
102 is a voltage controlled oscillator, 102 is a frequency divider, 103 is a phase comparator, 104 is a low-pass filter, 105 is a pseudo horizontal synchronization signal generator, 106 is an integrator, 108 is a signal selector, 100
is (T, 10T!) detector. that's all

Claims (1)

[Claims] (1) a) a voltage controlled oscillator that oscillates at N times the horizontal synchronizing signal frequency; and b) dividing the oscillation signal of the voltage controlled oscillator to 1/N;
c) a frequency divider that generates a divided signal A; c) a pseudo-horizontal synchronization signal generator that detects the code of the frequency divider and generates a pseudo-horizontal synchronization signal E near the original time position; and d) a composite an integrator that integrates the synchronization separation signal F to detect a low frequency period;
f) a signal selector that selects the composite synchronous separation signal F and generates a composite signal B during other periods; and f) a phase comparator comprising a gate circuit that gates passage of the frequency-divided signal A using the composite signal B. and g) a horizontally synchronized PLL circuit comprising a low-pass filter that converts the output of the phase comparator into direct current.