JPS63215079A - Eprom semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To extend the freedom in circuit design of EPROM device by means of providing floating gates at both sidewall parts opposing to a control gate. CONSTITUTION:A control gate 5 is formed on a substrate 1 in an element region encircled by a field oxide film 2 through the intermediary of a gate insulating film comprising a double layer structure of an oxide film 3 and a nitride film 4 while the sidewall parts and upper surface of this control gate 5 are covered with another oxide film 6 and another nitride film 7. Furthermore, floating gates 8' comprising polycrystalline silicon are formed on the sidewall parts of control gate 5. Besides, source drain regions in LDD structure comprising shallow N<->regions 9 as well as deep n<+>regions 10 are formed outside the floating gate 8' in the substrate. Through these procedures, the source and drain regions are not decided in principle but to be selected freely subject to the design requirements.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to electrically rewritable read-only memory (EPROM).
ogramableRead only Memory
) The present invention relates to a semiconductor device and its manufacturing method.

[Conventional technology]

EPROM, which is an electrically rewritable ROM, is widely used in various electronic devices because of the advantage that written contents can be changed freely.

EFROM injects hot electrons (thermoelectrons) generated by the avalanche effect into a floating gate adjacent to a control gate, and controls the output voltage by the floating gate potential generated by these hot electrons.An example of this is Nikkei Micro Device. 1
It is described on page 100 of the January 1986 issue. The structure of this is shown in FIG. 2, in which the side wall of the control gate 21 is flooded with a floating gate 22h%.

To explain the operation in this configuration, during writing, the side where the floating gate 22 is provided and the n region 232 provided on the opposite side are grounded, and a write gate voltage of 10 Vgp is applied to the control gate 21 to collect electrons. Inject into the floating gate 22 (Fig. 2(a)
). Further, during reading, the potential appearing across the floating gate 22 is different, and the memory operates as a memory.

[Problem that the invention seeks to solve]

However, in such conventional EPROM devices,
The floating gate is only provided on one side of the control gate, and the source and train during readout are automatically determined depending on which side of the control gate the floating gate is placed on, so there is little freedom in circuit design. There was a problem.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an EPROM semiconductor device and its manufacturing method that prevents the source and train from being automatically determined when a floating gate is provided, increasing the degree of freedom in circuit design. do.

[Means for solving problems]

To achieve the above object, the EPROM semiconductor device according to the present invention includes floating gates provided on opposite side walls of a control gate with an insulating film interposed therebetween.

Further, according to the method for manufacturing an EPROM semiconductor device according to the present invention, a control gate is formed after forming a gate insulating film in a predetermined region on a substrate, and a film with high etching resistance is formed on the surface and side surfaces of the control gate. A gate electrode material is roughly deposited over the entire surface and patterned so that it remains only on the sidewalls of the control gate to form a floating gate, and a source and a source are deposited in the substrate outside the floating gate.
A drain region is formed.

[For production]

According to the EPROM semiconductor device according to the present invention, since floating gates are provided on both side walls of the control gate, it is possible to freely select whether the high impurity concentration diffusion region formed in the substrate is to be used as a source or a train. be able to. Therefore, the degree of freedom in circuit design increases. Further, according to the method of manufacturing an EPROM semiconductor device according to the present invention, after forming the control gate, electrode material for forming the floating gate is deposited, and this is etched by anisotropic etching to form floating gates on both sides of the control gate. The above configuration can be easily obtained.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1(f) is a cross-sectional view showing the completed state of the EPROM device according to the present invention, in which two layers of an oxide film 3 and a nitride film 4 are formed on the substrate 1 in the element region surrounded by the field oxide film 2.
A control gate 5 is formed through a gate insulating film having a layered structure, and the sidewalls and top surface of the control gate 5 are covered with an oxide film 6 and a nitride film 7. A floating gate 8' made of polycrystalline silicon is formed. In the substrate outside the floating gate 8', there is an LDD (Lightly Doped Dra) consisting of a shallow N- region 9 and a deep N++ region 10 outside of this.
A source train region having an in ) structure is formed.

FIG. 1(a> to FIG. 1(f>) are cross-sectional views of elements by step, showing a method of manufacturing an EPROM device to obtain such a configuration.

First, a LOCO is applied to the periphery of the element formation region of the semiconductor substrate 1.
A thick field oxide film 2 is formed by method 3 (selective oxidation method), a silicon oxide film 3 which will become a gate oxide film is formed on the substrate surface by, for example, thermal oxidation, and a silicon nitride film 4 is roughly formed thereon.

Roughly, polysilicon is deposited on this by CVD method, and patterned to form the desired gate electrode shape.
A gate electrode 5 is obtained (FIG. 1(a)).

Next, oxidation is performed to form an oxide film 6 on the side walls and top surface of the gate electrode 5 (FIG. 1(C-)). Subsequently, a nitride film 7 is grown on the entire surface (FIG. 1(C)), and polysilicon 8 is deposited by CVD (FIG. 1(d)).
).

Next, when etching is performed using anisotropic etching such as reactive ion etching (RIE) so that the surface of the nitride film 7 on the control gate 5 is exposed, a fan-shaped cross section is formed only on the side wall of the control gate 5. A floating gate 8' is formed. Using the control gate 5 and floating gate 8' as ion implantation masks, an N-type impurity such as phosphorus is implanted at a relatively small dose and diffused.
A region 9 is formed (FIG. 1(e)).

Next, for example, an NSG film 11 is deposited as an intermediate insulating film,
Using this as an ion implantation mask, N-type impurities such as phosphorus are implanted and diffused with high energy. As a result, since the thickness of the NSG film 11 in the height direction is thick in the side parts of the floating gate 8', ions are hardly implanted into the substrate 1, and the ions are implanted into the substrate below the part where the NSG film surface is horizontal. A deep N++ region 10 with high ion concentration is formed within the region 1, and this region becomes a source train region.

In this way, an EPROM device including an LDD structure having a shallow drain layer near the gate electrode is completed (
Figure 1(f)〉.

FIG. 3 is an explanatory diagram showing the operation of the EPROM device according to the present invention. 3(a) and (b) show the write operation. First, +Vdp is applied to the N+ diffusion layer 101 on the left side, the N region 102 on the right side is grounded, and a gate voltage lower than Vdp is applied to the control gate 5. ■g
When p is applied, electrons are injected into the floating gate 8'1 on the left side of the control gate 5.

When the ground potential is applied to the N++ region 101 and the vcip potential is applied to the control gate 5, the right floating gate 8'
Electrons are injected into 2.

When electrons are injected into the two floating gates on both side walls of the control gate 5, the left N+ region is grounded and the read gate potential vc+r is applied to the control gate 5. Like N++ area 10
The read potential ■dr is obtained from 2. In this case, the N+ region 02 may be grounded and the read potential may be taken out from the N++ region 101. In other words, the source and drain can be freely selected, allowing reading from both directions.

In the above embodiment, an insulating oxide film and a nitride film as an etch stopper are formed on the control gate electrode, but the etching rate with the floating gate material (polysilicon in the embodiment) is high. Any material other than the nitride film can be used.

Further, in the embodiment, an LDD structure is adopted as the source/drain region, but the present invention is not limited to this.

〔Effect of the invention〕

As described above, in the EPROM device according to the present invention, floating gates are provided on opposite side walls of the control gate, so the source and train are not uniquely determined and can be freely selected depending on the design conditions. The degree of freedom in circuit design increases.

Further, the manufacturing method according to the present invention allows such an EPROM device to be easily manufactured.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an EPROM device according to the present invention and a step-by-step element sectional view for explaining the manufacturing method thereof, and FIG. 2 is a cross-sectional view of a conventional EPR
A sectional view showing the configuration of the OM device, FIG. 3 is an EPR of the present invention.
FIG. 3 is an explanatory diagram showing the operation of the OM device. 1...Substrate, 2...Field oxide film, 3, 6...
・Oxide film, 4, 7... Nitride film, 5... Control gate,
8... Polysilicon film, 8'... Floating gate, 9... N- region, 10... N region, 11.
...NSG film. -Example 1 4: S/V+1Il (NSOl 1!IL! Hosen Conventional/) EPROM Tea 2nd (J) (C) Implementation? In@Sakucha 3 z

Claims (1)

[Claims] 1. An EPROM semiconductor device having a control gate and floating elements disposed on both side walls of the control gate with an insulating film interposed therebetween. 2. The EPROM semiconductor device according to claim 1, wherein the control gate and the floating gate are each formed of polysilicon. 3. Insulating film is silicon oxide film and silicon nitride film 2.
E of claim 1, characterized in that it consists of a layer.
PROM semiconductor device. 4. Forming a gate insulating film in the element formation region on the substrate; Forming a control gate electrode using a first gate electrode material on the gate insulating film; a step of forming a film with high etchability; a step of depositing a second gate electrode material on the entire surface and etching it by anisotropic etching to form a floating gate electrode on a side wall portion of the control gate electrode; EPR comprising a step of implanting ions into the substrate using a gate electrode and a floating gate electrode as an ion implantation mask to form a source/drain region.
A method for manufacturing an OM semiconductor device. 5. The method of manufacturing an EPROM semiconductor device according to claim 4, wherein the first and second gate electrode materials are polysilicon and are deposited by CVD. 6. EPRO according to claim 4, wherein the anisotropic etching is reactive ion etching
M method for manufacturing semiconductor device. 7. EPRO according to claim 4, wherein the film having high etching resistance is a silicon nitride film.
M method for manufacturing semiconductor device.