JPS6243180A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To localize a floating gate electrode only on a channel between source and drain regions, by forming element isolating grooves by a self-aligning manner together with the floating gate electrode, and forming the floating gate electrode by a self-aligning manner together with a control gate electrode. CONSTITUTION:On a P-type silicon substrate 1, a floating gate electrode 3 comprising polycrystalline silicon is formed through source and drain diffusing regions 10 and a first gate silicon oxide film 2. On said floating gate 3, a control gate electrode 9 comprising polycrystalline silicon is formed through a second gate silicon oxide film. In the P-type silicon substrate 1, grooves 5, in which PSG films 7 are embedded, are provided. The floating gate electrode 3 is formed in a self-aligning manner together with the control gate electrode 9 at the end parts of the source and drain diffusing regions 10. The electrode 3 is formed in self-aligning manner by the grooves 5 at the side end part of a channel region between the source and drain diffusing regions 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and particularly to a nonvolatile semiconductor memory device having a floating gate electrode.

[Conventional technology]

A floating gate nonvolatile semiconductor memory device has a floating gate electrically insulated from the outside through a source/drain diffusion region on a semiconductor substrate and a gate insulating film on a channel region between the source/drain diffusion regions. Generally used is a device comprising an electrode and a control gate electrode on the floating gate electrode with an insulating film interposed therebetween.

As a means to miniaturize such a floating gate type non-volatile semiconductor memory device with a two-layer gate structure, for example, ``Semiconductor device and manufacturing method thereof'' is disclosed in Japanese Patent Application Laid-open No. 54-137982.
There is a device described as

This allows the dimensions of the device in the direction perpendicular to the channel to be reduced by preventing the floating gate electrode from overlapping the field insulating film for isolation between elements.

In addition, as a means of realizing such a structure, ``a first semiconductor layer, which becomes a first floating gate, is formed on the surface of a semiconductor substrate via a first insulating film, and a first semiconductor layer, which becomes a mask for selective oxidation, is formed on this semiconductor layer. 2 insulating film is formed, the first semiconductor layer extending over the second insulating film on the field region other than the surface for forming the source/drain/channel region is removed, and the substrate is oxidized using the remaining second insulating film as a mask. A manufacturing method has been proposed in which a thick field insulating film is formed in the field region.

[Problems that the invention helps solve]

In the above-mentioned nine conventional floating gate nonvolatile semiconductor memory devices, element isolation is achieved by selective oxidation, so even if the floating gate is designed not to overlap on the field region, it is actually a selective oxidation method. During oxidation, a thick oxide film is formed that sinks into the channel region under the floating gate electrode (commonly called a bird's beak), and the effective channel width of the device is reduced by the size of this bird's beak. For this purpose, conventional non-volatile semiconductors 8[In second-generation devices, the desired effective channel width? Even though it is secured, do you increase the channel width in consideration of the size of the bird's beak in the design? This has the disadvantage that it is not suitable for downsizing the device.

The object of the invention is to eliminate the above-mentioned drawbacks of the conventional device, and to provide a structure in which the floating gate electrode does not overlap the insulating film.
An object of the present invention is to provide a nonvolatile semiconductor memory device with a structure suitable for miniaturization.

〔problem? Means to solve]

A nonvolatile semiconductor memory device of the present invention has a floating gate electrode formed on a north fist drain region formed on a semiconductor substrate and a channel region above the source/drain region with a first gate insulating film interposed therebetween. and a second layer on the floating gate electrode.
a control gate electrode formed through a gate insulating film;
A nonvolatile semiconductor memory device having a groove for isolation between elements formed on the surface of a semiconductor substrate and filled with an insulator, in which the floating gel pole is self-aligned with the control gate electrode at the end of the source/drain region. It is formed in a self-aligned manner with the groove for isolation between elements at the side end portions of the channel region.

As described above, in the present invention, a groove is dug in the semiconductor substrate and the inside is filled with an insulator to isolate the elements, and the floating gate electrode is entirely formed in self-alignment with the groove. Since the floating gate electrode does not extend over the field region at all, and bird's beaks do not occur unlike the selective oxidation method, the effective channel width does not decrease.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

The first part is a plan view of an embodiment of the present invention, and the second and third sections are cross-sectional views taken along lines A-A' and B-B' of the center &+ example of the first section.

In factors 1 to 3, a floating gate electrode 3 made of polycrystalline 7 silicon is placed on a P-type silicon substrate 1 via a source/drain diffusion region 1o and two first gate silicon oxide films.
is formed on this floating gate electrode 3.
A control gate electrode 9 made of polycrystalline silicon is formed via a gate silicon oxide film. Further, on the P type/recon substrate 1, there is provided a groove 5 for isolation between elements, in which an I)SG film 7 is embedded.

The floating gate electrode 3 is formed in a self-aligned manner with the control electrode 9 at the end of the north-drain diffusion region 10, and is also formed on the side of the channel region between the north-drain diffusion region 10. The end portions are formed in a self-aligning manner by the hooks 5. Reference numeral 11 is a contact hole for connecting the source/drain diffusion region 10 to the A/wiring 12.

In this embodiment configured in this manner, the isolation between the elements F-1 is achieved by the trench 5 in which the PSO film 7 is embedded, so that the element isolation region does not overlap with the floating gate electrode 3. .

Next, the manufacturing method of the above embodiment will be explained using nine pages.

FIGS. 4(3) to 4(ei) are cross-sectional views of the semiconductor chip shown in step ':p for explaining the manufacturing method of the Dotenjin flow example.

First, as shown in FIG.
A first polycrystalline silicon film, which will become the floating gate'wL pole 3 in the future, is grown to a thickness of about 200 OA by a normal vapor phase growth method, and is doped with N-type conductivity type impurities. Add some phosphorus.

Next, a silicon nitride film 4 is grown to a thickness of about 300 OA.

Next, as shown in FIG. 4(b), photoresist
As a mask, the silicon nitride film 4, polycrystalline silicon film 3A, and silicon oxide film 2 on the area that will become the isolation region in the future are sequentially etched away using anisotropic adhesive active ion etching technology, and the exposed silicon substrate is removed. The surface of the substrate 1 was excavated to a depth of about 1.5 μm using an anisotropic glue active ion etching method to form a 5 ft groove for isolation between elements, and the photoresist was removed. Floating gate electrode 3 is formed in this groove 5 in a self-aligned manner.

This FIG. 4 tb+ is a cross-sectional view corresponding to the line AA' in FIG. 1, and hereinafter, FIG.
FIG.

Next, as shown in FIG. 4(C), a groove 5 is formed by thermal oxidation.
Approximately 30O on the sides and bottom of the floating gate electrode 3
A silicon oxide film 6 is formed, and then 7 silicon oxide film 1 is formed.
A P8G film 7 is formed on the entire surface to a thickness of about 3 μm by a normal vapor phase growth method.

The PSG film grown on the entire surface here is to facilitate surface flattening by heat treatment in the next step, and instead of the PSG film, a boron phosphorus silica glass film containing boron and phosphorus or the like can be used. Here, a PSG film with a phosphorus concentration of 10 mo1% was used.

Next, as shown in Figure 4 (td), when heat treatment is performed in an oxidizing atmosphere at 1000''C, the PSG film 7 becomes fluid 9 and the surface becomes approximately flat due to surface tension. As described above, in this embodiment, the PSG film was deposited by vapor phase growth to fill the grooves 5 for isolation between elements, but the grooves 5 may be filled by other methods. For example, it is also possible to deposit a silicon oxide film using a sputtering method, or to deposit an organic insulating film using a spin-on method.

Next, as shown in step 4d (el), a wet or dry etching method capable of selectively etching the PSG film, such as an HF-based wet etching method or a CF4-based plasma etching method, is used until the silicon nitride film 4 is exposed. The PSG film 7 is etched.Then, when the silicon nitride film 4 is removed using hot phosphoric acid, P is formed only in the groove 5.
The SG film 7 is left behind. During this etching step, the silicon nitride film 4 is used to prevent the surface of the PSG film from being lower than the surface of the floating gate II pole 3 and to prevent the surface flatness from being impaired due to over-etching.

That is, over-etching is allowed during etching by the thickness of the silicon nitride film 4, and the process margin is widened.

Through the above steps, the surface of the PSG film 7 in the isolation trench 5 and the surface of the floating gate electrode 3 are flattened to almost the same height, and the isolation trench 5 and the floating gate electrode 3 are self-aligned. A precisely formed shape is obtained.

Next, as shown in FIG. 2, a second gate silicon oxide film 8 of about 30 OA is formed on the floating gate electrode 3 by thermal oxidation.
A second gate electrode 9 is formed on top of the second gate electrode 9 to a thickness of
The polycrystalline silicon film is approximately soo.

Grow to thickness A.

The subsequent steps will be explained with reference to FIG. 3, which is a sectional view taken along the line BB' of the embodiment shown in FIG. 1.

As a photoresist mask (not shown), the second polycrystalline silicon film, the second gate silicon oxide film 8, and the first polycrystalline silicon film 3Ak are sequentially etched by anisotropic plasma etching to form a desired gate. The electrode shape is formed of gold, and then N is deposited on the silicon substrate 1 using this multilayer film as a mask.
Arsenic, which is a type impurity, is ion-implanted at a dose of 5×1 O/car to form source/drain diffusion regions 10.

The shapes of the floating gate [&3 and the control gate pole 9 formed in this manner are determined in a self-aligned manner at the end of the source/drain region of the channel.

Thereafter, through steps such as forming an interlayer insulating film, forming contact holes, and forming A/wirings, the nonvolatile semiconductor memory device shown in FIGS. 1 to 3 is completed.

〔Effect of the invention〕

As explained in detail above, the present invention forms a groove for isolation between elements in a self-aligned manner with a floating gate electrode, and forms a floating gate electrode in a self-aligned manner with a control gate electrode. can be localized only on the channel between the source and drain regions. Therefore, inconveniences caused by bird's beaks when device isolation is achieved by selective oxidation are also eliminated. According to the present invention, a floating gate type nonvolatile semiconductor memory device with a two-layer gate structure having the smallest area in plan view can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, FIGS. 2 and 3 are sectional views taken along lines AA' and BB' of the embodiment of FIG.
FIG. 4 (al to tel are process cross-sectional views for explaining the manufacturing method of an embodiment of the present invention. 1... P-type silicon substrate, 2... first gate silicon oxide film, 3 floating gate Electrode, 4 Silicon nitride film, 5 Groove, 6 Silicon oxide film, 7...
・psog,s 2nd gate silicon oxide film, 9
・Control gate electrode, 10 Source/drain diffusion region, 11. ・Contact hole, 12...A/wiring. Agent Patent attorney Shingyu Uchihara Figure 5 Hou 2 Figure 4: J Rico, 1→1 ■ Rabbit

Claims (1)

[Claims] A source/drain region formed on a semiconductor substrate, a floating gate electrode formed on the surface of the semiconductor substrate between the source/drain regions via a first gate insulating film, and a second gate electrode formed on the floating gate electrode. In a nonvolatile semiconductor memory device having a control gate electrode formed through a gate insulating film, and a groove for isolation between elements formed on the surface of the semiconductor substrate and filled with an insulating material, the floating gate The electrode is formed in self-alignment with the control gate electrode at the end of the source/drain region, and in self-alignment with the element isolation groove at the end of the channel region between the source/drain regions. Characteristic non-volatile semiconductor memory device.