JPS63215062A - Design method for semiconductor integrated circuit mask - Google Patents

Abstract

PURPOSE:To improve the efficiency of area utilization of a semiconductor integrated circuit mask by a method wherein the source part of the mask is provided on the outer circumferential part of the mask, and the source parts of the adjoining masks are arranged common when the masks are arranged automatically. CONSTITUTION:The source parts 30 and 32 of the P-channel transistor part of a two-input NAND logical gate semiconductor integrated circuit mask and the source part 36 of an N-channel transistor part are provided on the outer circumferential part of the mask. Then, utilizing the fact that each mask has the same potential, the marginal measurements of the adjoining masks and the width of the source are reduced by making the source parts 32 and 34 common, the width in lateral direction of the automatically arranged masks can be reduced, and the efficiency of area utilization can also be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit mask with efficient use of area.

2. Description of the Related Art Conventional 1 For example, when automatically arranging a two-man-powered NAND logic gate semiconductor integrated circuit mask shown in FIG. 2(a) and a two-man-powered NOR logic gate semiconductor integrated circuit mask shown in FIG. 2 (tb) adjacently. , it was done as follows.

Hereinafter, a semiconductor integrated circuit mask is defined as a general term for multiple level masks such as aluminum level masks and contact level masks that are required when actually manufacturing semiconductor integrated circuits.

First, in the two-man NAND logic gate semiconductor integrated circuit mask, the source part 40,42 of the P channel transistor
and adjacent semiconductor integrated circuit mask margin portions 41 and 43 corresponding thereto are provided. A source portion 44 of an N-channel transistor and a margin portion 45 for masking an adjacent semiconductor integrated circuit are provided.

In the case of a two-man NAND logic gate semiconductor integrated circuit mask, the width generated by the source portion 40° 42 of the P-channel transistor plus the width of the adjacent semiconductor integrated circuit mask margin 41.43.

Define the horizontal width of the entire mask.

On the other hand, in the two-man NOR logic gate semiconductor integrated circuit mask, a source portion 62 of a P-channel transistor and a margin portion 63 for the adjacent semiconductor integrated circuit mask are provided.

Source portions 54 and 56 of N-channel transistors and corresponding margin portions 55 and 57 for masking adjacent semiconductor integrated circuits are provided.

In the case of two-person NOR logic gate semiconductor integrated circuit mask,
The width generated by the source portion 64.degree. 56 of the N-channel transistor plus the width of adjacent semiconductor integrated circuit mask margins 66 and 67 defines the lateral width of the entire mask.

FIG. 2C shows the automatic arrangement of the two types of semiconductor integrated circuit masks described above. The lateral width of this semiconductor integrated circuit mask is equal to the sum of the lateral widths of the individual semiconductor integrated circuit masks described above. Further, the distance 61 between the source portion e2 and the source portion 640 of the P-channel transistor is equal to the sum of margins 43.53 for adjacent semiconductor integrated circuit masks provided in each semiconductor integrated circuit mask.

Source portion 66 and source portion 68 of N-channel transistor
The interval 67 is the adjacent semiconductor integrated circuit mask margin 4.
Equal to the sum of 5.55.

Problems to be Solved by the Invention In the conventional method of designing semiconductor integrated circuit masks, a problem similar to that of the poet arises in which masks are arranged horizontally one after another through automatic placement.

In FIG. 2(c), paying attention to the fact that the source portions 60, 62.84 of the P-channel transistor are at the same potential, the margin 61 is unnecessary, and the source portion 62.84 is not necessary.
It can be seen that 84 can be shared.

Source part 66.6B of N-channel transistor.

Noting that To is at the same potential, it can be seen that the margin 67 is unnecessary and that the source parts 66 and 68 can be shared.

That is, there is a problem in that the lateral dimension of the semiconductor integrated circuit mask shown in FIG. 2C includes an unnecessary margin dimension and a source width dimension.

In view of the above, the present invention provides a semiconductor integrated circuit mask with a source portion on the outer periphery, and when automatically arranging the masks, the source portions of adjacent masks are placed in common, and the semiconductor integrated circuit mask has high area utilization efficiency. The purpose of this invention is to provide a mask design method for obtaining a mask.

Means for Solving the Problems The present invention provides a semiconductor integrated circuit in which the source portion of a single semiconductor integrated circuit mask is provided on the outer periphery, and when the mask is automatically placed, the source portions of adjacent masks are placed in common. This is a method of designing a circuit mask.

Still further, the present invention provides a method for designing a semiconductor integrated circuit mask, characterized in that when automatically arranging the mask, an enable flag is set in the source portion, and the source portion is placed in common according to the data of the flag. be.

The source portion of the working semiconductor integrated circuit mask is provided on the outer periphery, and each source portion has enable flag data indicating whether or not it can be shared with the source portion of an adjacent semiconductor integrated circuit mask.

When the semiconductor integrated circuit masks created in this way are arranged horizontally one after another by automatic placement, the source parts of adjacent masks that can be shared are shared based on the enable flag data of the source part of each mask. It will be placed automatically.

In this way, unnecessary margin dimensions between adjacent masks and source width dimensions can be greatly reduced1.
A semiconductor integrated circuit mask with high area utilization efficiency can be obtained.

Embodiment FIG. 1(a) shows a two-man NA in the first embodiment of the present invention.
This is an ND logic gate semiconductor integrated circuit mask, and the source portion 10.12 of the P channel trough 22 is provided on the outer periphery of the mask. The source portion 14 of the N-channel transistor portion is also provided on the outer periphery of the mask.

There is no margin portion corresponding to the adjacent mask margin portions 41, 43, 4.5 as shown in FIG. 2(a).

FIG. 1(b) shows a two-person NO. in the first embodiment of the present invention.
This is an R logic gate semiconductor circuit mask, and the source portion 20 of the P channel trough 932 portion is provided at the outer periphery of the mask. Source portion 24 of N-channel transistor section
．． 26 is also provided on the outer periphery of the Maasuf.

There is no margin portion corresponding to the adjacent mask margin portions 53, 55, 57 as shown in FIG. 2(b).

Both the source portion 12.14 in FIG. 1(a) and the source portion 20.24 in FIG. 1(b) are provided with enable flag data indicating that they are source portions that can be shared.

When the two types of semiconductor integrated circuit masks described above are automatically arranged, the mask shown in FIG. 1(c) is obtained. That is, the common source portion 32 is the source portion 12 and the source portion 20 of each mask made common, and the common source portion 3
4 is a mask in which the source portion 14 and the source portion 24 of each mask are made common.

As described above, according to this embodiment, the margin dimension for adjacent masks and the dimension of the source width can be reduced, and the width in the horizontal direction of the mask in FIG. It is smaller than the width in the lateral direction of the automatically placed mask shown in FIG.

Note that in the first embodiment, the semiconductor integrated circuit mask is C
Although the MO3 structure is used, an NMO3 structure may also be used.

FIG. 3 shows a second embodiment of the present invention. Figure 3(a),
FIG. 3(b) shows the source part of the semiconductor integrated circuit mask,
Only the drain part is described.

In the semiconductor integrated rotation mask shown in FIG. 3CB, there are three source portions S10. S12. S14 and one drain portion d10 are provided.

The source portions 810 and 312 can be made common by an enable flag.

In the semiconductor integrated circuit mask shown in FIG.
Source portions 820, 822, 324 and one drain portion d20 are provided.

The source parts 820 and 322 can be made common by an enable flag.

The two semiconductor integrated circuit masks mentioned above are shown in FIG. 3(a) (
7) For the mask, automatically arrange it in the direction shown in Figure 3 + c), and for the mask in Figure 3 (b),
FIG. 3(d) [By automatically arranging the source portion S10 and the source portion S20 in mirror-inverted directions as shown, the source portion S10 and the source portion S20. Since the source portion S12 and the source portion S22 can be shared, a semiconductor integrated circuit mask with high area utilization efficiency can be obtained.

5. As described in detail of the invention, according to the present invention, when semiconductor integrated circuit masks are automatically placed, the source portions of the same potential are shared and automatically placed, so the margin size for adjacent masks can be reduced compared to the conventional method. Since the source width can be reduced, a semiconductor integrated circuit mask can be designed with high area utilization efficiency, and its practical effects are enormous.

[Brief explanation of the drawing]

FIG. 1(a) shows a two-man powered NAN according to the first embodiment of the present invention.
D mask diagram, FIG. 1(b) is a two-man NOR mask diagram showing the first embodiment of the present invention, and FIG. 1(c) is a mask diagram as a result of automatic placement showing the first embodiment of the present invention. Fig. 2(a) is a diagram of a two-man NAND mask showing a conventional example;
FIG. 2 cb) is a two-man powered NOR mask diagram showing a conventional example. FIG. 2(c) is a mask diagram as a result of automatic placement showing a conventional example, FIG. 3(b) is a schematic diagram of a mask showing a second embodiment of the present invention, FIG. ), FIG. 3(d) is a plan view showing the direction of mask arrangement. 10.12, 14, 20, 24, 28, 30° 36...
...Source part, 32.34...Common source part. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure 1 Figure 1 m1 (C): M Jintsu sauce evil portion Figure 2 Figure 2 cause (C) Figure 3 (C) fO 5ro, S12. S/4-source part Sho Sn,
524 - source part molecule ho, dυ - train part < d)

Claims (2)

[Claims] (1) Design of a semiconductor integrated circuit mask characterized in that the source portion of a single semiconductor integrated circuit mask is provided on the outer periphery, and when the mask is automatically placed, the source portions of adjacent masks are placed in common. Method. (2) When automatically arranging the semiconductor integrated circuit mask, an enable flag is set in the source portion, and the source portion is placed in common according to the data of the flag. Design method for semiconductor integrated circuit masks.