JPS63213966A - Manufacture of thin-film transistor integrated circuit - Google Patents

Abstract

PURPOSE:To manufacture an integrated circuit having excellent thin-film transistor characteristics by evaporating and forming a semiconductor thin-film immediately after a gate insulating film is shaped and simultaneously conducting the removal of a semiconductor thin-film unnecessary section and the exposure of the side surface of a photo-resist for lifting off the gate insulating film for forming a contact hole through a dry etching process. CONSTITUTION:Cadmium selenide (CdSe) in approximately 500Angstrom as a semiconductor for a thin-film transistor is evaporated onto the whole upper surface of a gate insulating film 15 immediately after the gate insulating film 15 is formed, thus shaping the so-called CdSe thin-film 16. A resist 17 for protecting the so-called CdSe thin-film for protecting a section required for manufacturing the thin-film transistor is deposited and formed onto the upper surface of the CdSe thin-film 16. The whole sample is introduced into a sputtering device, and an unnecessary section in the CdSe thin-film 16 is removed through a dry etching process under a plasma-changed argon gas atmosphere at 1X10<-2>Torr. The CdSe thin-film 16 coating the side surface of a resist 14 for lifting off the gate insulating film and one part of the gate insulating film 15 are gotten rid of at the same time, and the side surface of the resist 14 for the lift-off is exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a thin film transistor integrated circuit comprising a gate electrode below a gate insulating film and a source electrode and a drain electrode above the gate insulating film.

2. Description of the Related Art A conventional method for manufacturing a thin film transistor integrated circuit of this type will be described below with reference to FIGS. 2 and 3.

First, as shown in FIG. 2, a gate electrode 2 and a wiring 3 are formed on a glass substrate 1 by a conventionally known photolithography technique after evaporating 500A of aluminum. Note that the gate electrode and wiring 3 are provided under a gate insulating film 5, which will be described later.

Next, in order to form a small hole (hereinafter referred to as a contact hole) for electrically connecting the wiring provided on the upper part of the gate insulating film 5 and the wiring 3 under the gate insulating film 5, which will be described later. Apply photoresist for gate insulating film lift-off to the area where the contact pole will be formed (approx.
, am) 4 is deposited.

Next, aluminum oxide (approximately 300%
0A) by sputtering to form a gate insulating film 5.
Then, in order to protect the gate insulating film 5 from the subsequent ion beam etching process, a resist 6 for protecting the gate insulating film is deposited on the upper surface of the gate insulating film 5 other than where the contact hole is to be formed.

Next, the gate insulating film 5 deposited on the side surface of the photoresist 4 for lift-off is removed by irradiating the argon ion beam 7 obliquely from above, and the photoresist 4 is exposed (ion beam etching step). .

Next, the photoresist 4 and the gate insulating film protection resist 6 are removed using a stripping solution.

In this step, the gate insulating film 5 on the photoresist 4
is lifted off to form a contact hole.

Next, the process moves on to forming a cadmium selenide (CdSe) thin film as a semiconductor thin film for a thin film transistor. The formation process will be explained with reference to FIG.

First, a CdSe thin film lift-off photoresist 8 is deposited on the upper surface of the gate insulating film 5 at a contact hole formation position and in the vicinity thereof. Next, a CdSe thin film (approximately 50 OA) 9 is deposited on the entire surface including the resist 8 by a vapor deposition method.

Next, the photoresist 8 is removed using a resist stripping solution. In this step, unnecessary portions of the CdSe thin film 9 are also removed.

Here, a state in which the CdSe thin film (semiconductor thin film for thin film transistor) 9 is patterned is shown in FIG. In the figure, numeral 10 is a so-called whisker peculiar to lift-off that occurs at the end of the CdSe thin film 9, and A is a contact hole.

Problems to be Solved by the Invention However, such conventional manufacturing methods have the following drawbacks.

(1) The process is complicated. Three photolithography steps are required to form the contact hole and to form the CdSe thin film.

(2) The interface between the gate insulating film and the CdSe thin film becomes dirty during the photolithography process.

(3) In the CdSe thin film paste lift-off process, CdS
e So-called whiskers are formed at the edges of the thin film. This whisker causes a break in the aluminum thin film when source and drain electrodes are formed on the CdSe thin film by aluminum vapor deposition in a subsequent step.

The reason why the above problem occurs is as follows. That is, firstly, the CdSe thin film is patterned by lift-off. Source for this.

So-called whiskers occur which cause step breaks when forming the drain electrode.

Second, the CdSe thin film is formed after the contact hole is formed. The surface of the gate insulating film for forming contact holes is contaminated with photoresist. A thin film transistor is particularly required to have a clean interface between a gate insulating film and a semiconductor thin film (CdSe thin film). If this interface becomes dirty, the characteristics of the thin film transistor will change significantly over time.

Third, lift-off and C for contact hole formation
This is because lift-off for dSe thin film patterning is performed separately. This makes the process complicated.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to perform dry etching of the semiconductor thin film instead of lift-off without contaminating the interface between the gate insulating film and the semiconductor thin film. Provides a method for manufacturing a thin film transistor integrated circuit in which the formation of contact holes and semiconductor thin film patterning are performed in the same process, thereby simplifying the entire process. It's about doing.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention, after forming a gate insulating film lift-off resist, deposits a semiconductor thin film for a thin film transistor following the deposition of a gate insulating film, and then performs semiconductor thin film patterning. In this method, a resist for etching is formed, and then the unnecessary portions of the semiconductor thin film are etched and the lift-off resist for forming contact holes is simultaneously exposed in a dry etching process.

action The effects of the above technical means are as follows.

That is, after forming a gate insulating film for forming a contact hole, a semiconductor thin film is immediately deposited without contaminating the surface of the gate insulating film with organic matter due to a photolithography process, so the interface between the gate insulating film and the semiconductor thin film is contaminated. This reduces the number of interface states caused by impurities. Therefore, the thin film transistor manufactured according to the present invention exhibits good characteristics. In particular, changes in thin film transistors over time due to electron capture in interface states are significantly improved.

Furthermore, according to the technical means of the present invention, the process of forming a contact hole and the process of patterning a semiconductor thin film are performed by a single dry etching process, so that the entire process is significantly simplified compared to the conventional method.

EXAMPLE Hereinafter, an example of a method for manufacturing a thin film transistor integrated circuit according to the present invention will be described with reference to FIG.

First, a gate electrode 12 of a thin film transistor and a wiring under a gate insulating film 13 are formed using a metal thin film on a glass substrate 11 . Next, a so-called gate insulating lift-off resist 14 is formed at the location where the contact hole is to be formed, and then aluminum oxide (approximately 300O
A gate insulating film 15 made of A) is deposited by sputtering. The steps up to this point are exactly the same as the conventional method detailed in FIG.

Next, immediately after forming the gate insulating film 15, cadmium selenide (Cd) is used as a semiconductor for thin film transistors.
Approximately 50 OA of Se) is deposited over the entire upper surface of the gate insulating film 15 to form a so-called CdSe thin film (semiconductor thin film for thin film transistors) 16.

Next, a so-called CdSe thin film protection (for semiconductor thin film patterning) resist 17 is deposited on the upper surface of the CdSe thin film 16 to protect the portions necessary for manufacturing the thin film transistor. Thereafter, the entire sample is placed in a sputtering apparatus, and unnecessary portions of the CdSe thin film 16 and gate insulating film 15 are simultaneously removed by dry etching in an argon gas atmosphere turned into plasma at 1X10 Torr.

That is, in this dry etching step, unnecessary parts of the CdSe thin film 16 are removed, and a part of the CdSe thin film 16 and gate insulating film 15 covering the side surfaces of the gate insulating film lift-off resist 14 (the side surfaces of the lift-off resist 14 are removed). (the portion where the lift-off resist 14 is located) is removed, and the side surface of the lift-off resist 14 is exposed.

Next, the lift-off resist 14 and the CdSe thin film protection resist 17 are removed using a resist stripping solution. In this process, the patterning of the CdSe thin film 16, that is, the formation of the shape of the semiconductor thin film necessary for manufacturing the thin film transistor, and the formation of the contact hole are completed at the same time. According to this embodiment, the formation of the gate insulating film 15 is completed simultaneously. Since the CdSe thin film (semiconductor thin film) 16 is formed immediately thereafter, a good semiconductor thin film-gate insulating film interface can be obtained.

Note that if the formation of the gate insulating film and the formation of the CdSe thin film are performed consecutively in the same vacuum chamber without exposing it to the atmosphere,
An even better interface can be obtained.

Furthermore, since the CdSe thin film is patterned by dry etching, so-called whiskers do not occur in the semiconductor thin film portion, which is characteristic of lift-off as shown in the conventional technique shown in FIG.

Furthermore, in the conventional process, contact hole formation and Cd
Although three times of photolithography was required to remove the unnecessary parts of the Se thin film, in the process of this embodiment, only two times were required, and the entire process is significantly simplified compared to the conventional method.

Effects of the Invention As is clear from the above explanation, according to the present invention, a semiconductor thin film is formed by vapor deposition immediately after the gate insulating film is formed.
Next, a dry etching process is used to simultaneously remove unnecessary parts of the semiconductor thin film and expose the sides of the gate insulating film lift-off photoresist for forming contact holes, so that the interface between the gate insulating film and the semiconductor thin film is not removed as before. This has the advantage that it is possible to manufacture an integrated circuit with good thin film transistor characteristics without being contaminated by photolithography or the like.

Further, according to the present invention, since unnecessary portions of the semiconductor thin film are removed by a dry etching process, it is possible to avoid the occurrence of so-called whiskers at the ends of the semiconductor thin film, which are characteristic of lift-off.

Furthermore, according to the present invention, removing unnecessary portions of the semiconductor thin film;
Since the side surface exposure of the lift-off resist for forming the contact hole is performed simultaneously in the dry etching process, the entire process is significantly simplified compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram illustrating a manufacturing process of a thin film transistor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a schematic diagram illustrating a manufacturing process of a thin film transistor integrated circuit based on a conventional method. FIG. 3 is a schematic diagram for explaining the process of removing an unnecessary portion of a semiconductor thin film using a conventional method, and FIG. 4 is a schematic diagram showing a state in which a semiconductor thin film for a thin film transistor is patterned using a conventional method. 11...Glass substrate, 12...Gate electrode, 13.
... Wiring under gate insulating film, ]4... Resist for gate insulating film lift-off, 15... Gate insulating film, 16...
・CdSe thin film (semiconductor thin film for thin film transistors), 1
7... Resist for protecting CdSe thin film (resist for semiconductor thin film patterning). Name of agent: Patent attorney Toshio Nakao and one other person
1 Figure//-71'Last Base Ignition/2 Day Senju Seven Exchanges/3 Buu Kamidamitsuhaku Underworld Trap Freeze/4 Wow")l!, look at 4 Sirikutofuwa WL Ji'
St/S Buta 1 Ascendant gland/A CtDoSe し3-1ζ)Ke;#ltOney
s'VM Ibookine Fu'$1,)/7- Ctt5υ
=s *Korea's last 2nd (Kijiteri 1ri-H) and Tani] L Jis)) /7 /ro, 2 1 1 t/ y3 Figure 2?・ ＼ l 3 Figure 3 (′ ＼ 2 1J

Claims (1)

[Claims] After forming the gate electrode of the thin film transistor and the interconnection under the gate insulating film using a metal thin film on the glass substrate, forming a first resist for lift-off of the gate insulating film at the location where the contact hole is to be formed, and then forming a gate insulating film on the entire surface. Immediately, a semiconductor thin film for a thin film transistor is formed on the entire surface, and a second semiconductor thin film patterning layer is formed on the semiconductor thin film.
After forming a resist, and then dry etching to simultaneously remove unnecessary portions of the semiconductor thin film and the semiconductor thin film and gate insulating film covering the side surfaces of the first resist to expose the side surfaces of the first resist. , the first
A method for manufacturing a thin film transistor integrated circuit, characterized in that forming a contact hole and patterning a semiconductor thin film are performed simultaneously by removing a resist and the second resist using a resist stripping solution.