JPS632135B2 - - Google Patents
Info
- Publication number
- JPS632135B2 JPS632135B2 JP56000323A JP32381A JPS632135B2 JP S632135 B2 JPS632135 B2 JP S632135B2 JP 56000323 A JP56000323 A JP 56000323A JP 32381 A JP32381 A JP 32381A JP S632135 B2 JPS632135 B2 JP S632135B2
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- layer
- alloying
- substrate
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 22
- 238000005275 alloying Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 3
- 229910052751 metal Inorganic materials 0.000 description 23
- 239000002184 metal Substances 0.000 description 23
- 239000004065 semiconductor Substances 0.000 description 12
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- -1 that is Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は、半導体基板との合金形オーム性接触
において平滑で均一なオーム性接触を得る方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for obtaining smooth and uniform ohmic contact in alloyed ohmic contact with a semiconductor substrate.
従来、GaAs等の半導体基板と金属層とのオー
ム性接触を得るには、半導体基板上に金属層を真
空蒸着し、次に熱処理を行ない金属層を合金化す
ることによつて行なわれていた。金属層として
は、Au／Au・Ge，Pt／Au・Ge，Ni／Au・
Ge，Mo／Au・Ge等の組成が用いられてきた。
Au・Geは、半導体基板とのオーム性接触を得る
ためであり、その上部金属つまりAu，Pt，Ni，
Mo等は、合金化時のAu・Geの凝集を妨げ、か
つ金属層表面での抵抗を下げるために被着されて
いる。 Conventionally, ohmic contact between a semiconductor substrate such as GaAs and a metal layer was achieved by vacuum-depositing the metal layer on the semiconductor substrate and then performing heat treatment to alloy the metal layer. . The metal layer is Au/Au・Ge, Pt/Au・Ge, Ni/Au・
Compositions such as Ge, Mo/Au/Ge, etc. have been used.
Au/Ge is used to obtain ohmic contact with the semiconductor substrate, and the upper metal, that is, Au, Pt, Ni,
Mo and the like are deposited to prevent agglomeration of Au and Ge during alloying and to lower resistance on the surface of the metal layer.
ここで、金属として微細パタンを得るには、通
常ホトレジストによるリフトオフ法が広く用いら
れている。その理由は、上記Au系の合金の化合
物半導体に対する充分な選択性をもつた微細パタ
ンを形成し得るエツチング法がないためである。
リフトオフ法では、金属層を真空蒸着する前に半
導体基板上にホトレジストの微細パタンを形成し
ておき、この微細パタンの上に金属層を真空蒸着
する。次に、大気中に取り出してからホトレジス
トを除去し、金属層のリフトオフパタンを得る。 Here, to obtain a fine metal pattern, a lift-off method using photoresist is commonly used. The reason for this is that there is no etching method that can form a fine pattern with sufficient selectivity to the compound semiconductor of the Au-based alloy.
In the lift-off method, a fine pattern of photoresist is formed on a semiconductor substrate before a metal layer is vacuum-deposited, and a metal layer is vacuum-deposited on this fine pattern. Next, after taking it out into the atmosphere, the photoresist is removed to obtain a lift-off pattern of the metal layer.
微細パタンのリフトオフに用いられるホトレジ
ストは解像度の良いポジ型レジストであるが、こ
のレジストの熱変形は120℃以上で生じる。従つ
て、金属層蒸着時の基板温度は、120℃以上にす
ることはできない。 The photoresist used for lift-off of fine patterns is a positive resist with good resolution, but thermal deformation of this resist occurs at temperatures above 120°C. Therefore, the substrate temperature during metal layer deposition cannot be higher than 120°C.
上記のリフトオフ工程の後、金属層は高温に上
げられ合金化処理される。従来の合金化時の温度
プログラムを第１図に示す。図中ａは合金化温度
までの昇温部、ｂは合金化部分、ｃは降温部であ
る。これは、室温から、合金化温度TAまで300〜
500℃／分程度の昇温速度で単調に昇温し、合金
化温度TA＝400〜500℃をtA＝０〜10分間保つて、
降温するという方法である。また、合金化時の雰
囲気は、H2，N2，Ar等のガスが流れている。 After the above lift-off process, the metal layer is raised to a high temperature and alloyed. A conventional temperature program during alloying is shown in FIG. In the figure, a is a temperature rising part up to the alloying temperature, b is an alloying part, and c is a temperature cooling part. This ranges from room temperature to alloying temperature T A of 300~
Monotonically raise the temperature at a heating rate of about 500°C/min, maintain the alloying temperature T A = 400 to 500°C for t A = 0 to 10 minutes,
This method involves lowering the temperature. Further, gases such as H 2 , N 2 , Ar, etc. are flowing in the atmosphere during alloying.
上述した合金化方法では、しばしば、金属層が
ほぼ半球状に膨れ上り、所謂、ボール・アツプ２
１となる（第２図参照）。第２図において、２１
はボール・アツプ、２２はオーム性電極、２３は
半導体基板、２４はボール・アツプ部空隙を示
す。前記のボール・アツプは、半径rB＝0.5〜
10μm程度にも達し、金属層表面も0.5〜10μm程
度の凸部を有する。 In the alloying method described above, the metal layer often swells into an almost hemispherical shape, resulting in a so-called ball up2.
1 (see Figure 2). In Figure 2, 21
22 is an ohmic electrode, 23 is a semiconductor substrate, and 24 is a ball-up gap. The above ball up has a radius r B = 0.5 ~
The metal layer surface also has convex portions of about 0.5 to 10 μm.
このボール・アツプは、図に示した如く、内部
が空隙２４となつている。これは、昇温過程での
合金化が金属層表面から進行するために、主とし
て半導体表面の吸着分子と、オーム性金属層中の
吸着分子等とが、かかる昇温過程中にガス化する
際、外部への逃げ場を失ない集合，膨脹すること
により、金属層を持ち上げボール・アツプとなる
ことによる。 As shown in the figure, this ball up has a cavity 24 inside. This is because alloying progresses from the surface of the metal layer during the heating process, so when adsorbed molecules on the semiconductor surface and adsorbed molecules in the ohmic metal layer gasify during the heating process. , by gathering and expanding without losing any escape to the outside, the metal layer lifts up and becomes a ball-up.
このようなボール・アツプ現象は、上述のよう
なリフトオフ工程を用いる場合以外でも、金属層
の真空蒸着が金属層の合金化温度以下の基板温度
で行われ、これがパターニングなどの処理のため
に大気中に晒されてから合金化熱処理が行なわれ
るような場合においても顕著に発生する。 This ball-up phenomenon is caused even when the lift-off process described above is not used, and the metal layer is vacuum-deposited at a substrate temperature below the alloying temperature of the metal layer, which is exposed to the atmosphere for processing such as patterning. It also occurs noticeably in cases where alloying heat treatment is performed after being exposed to heat.
半導体素子が集積化されるに従い、オーム性電
極も微細化されており、このようなボール・アツ
プが存在すると、電気特性が劣化するばかりか、
ホト工程の不均一化、上部配線金属との短絡等の
問題が生じる。 As semiconductor devices become more integrated, ohmic electrodes are also becoming finer, and the presence of such ball ups not only deteriorates electrical characteristics, but also
Problems such as non-uniformity of the photo process and short circuit with the upper wiring metal occur.
本発明は、半導体基板とオーム性接触を得る金
属層とを合金化する前に、半導体基板上の吸着分
子と、オーム性接触を得る合金層中の吸着分子と
を除去することにより、オーム性合金層のボー
ル・アツプを防ぐことができることに基づくもの
であり、本発明により、平滑で均一なオーム性電
極が形成することができる。 The present invention achieves ohmic contact by removing adsorbed molecules on the semiconductor substrate and adsorbed molecules in the alloy layer that makes ohmic contact before alloying the semiconductor substrate and a metal layer that makes ohmic contact. This is based on the fact that ball-up of the alloy layer can be prevented, and a smooth and uniform ohmic electrode can be formed according to the present invention.
次に本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.
第３図は本発明の実施例で、合金化温度プログ
ラムを示している。合金化の前には以下の如く試
料が準備される。清浄化されたGaAs等の半導体
基板上に、オーム性接触となる金属層、例えば
Pt／Au・Ge，Ni／Au・Ge，Au／Au・Ge，
Mo／Au・Ge等を、蒸着，スパツタ等により被
着する。Au・Ge層はGaAsとのオーム性接触を
得るため0.01〜1.0μm程度の厚さとし、Au・Ge
層の上には上述Pt，Ni，Au，Mo等の金属を0.01
〜1.0μm程度の厚さに被着する。次に、当該オー
ム性接触となる金属層を所望の形状にパタニング
する。これで、試料が準備できる。この試料を、
合金化炉に入れ、第３図に示す温度プログラム
で、合金化しオーム性接触を得る。 FIG. 3 is an embodiment of the present invention, showing an alloying temperature program. Before alloying, the sample is prepared as follows. A metal layer for ohmic contact, e.g., is placed on a cleaned semiconductor substrate such as GaAs.
Pt/Au・Ge, Ni/Au・Ge, Au/Au・Ge,
Deposit Mo/Au, Ge, etc. by vapor deposition, sputtering, etc. The Au/Ge layer has a thickness of approximately 0.01 to 1.0 μm to obtain ohmic contact with GaAs.
On top of the layer, the metals such as Pt, Ni, Au, Mo, etc.
Deposit to a thickness of ~1.0μm. Next, the metal layer that will form the ohmic contact is patterned into a desired shape. The sample is now ready. This sample
It is placed in an alloying furnace and alloyed with the temperature program shown in FIG. 3 to obtain ohmic contact.
第３図において、縦軸は試料温度、横軸は時間
を示す。まず、試料温度を昇温Ａし、温度をTP In FIG. 3, the vertical axis shows sample temperature and the horizontal axis shows time. First, raise the sample temperature A, then lower the temperature to T P
Claims (1)
と前記GaAs基板が合金化する温度以下の基板温
度で蒸着する工程と、前記基板を大気中で処理す
る工程と、前記Au・Ge層と前記GaAs基板が合
金化する以下の温度下及び大気圧以下の減圧下に
前記基板を保持する工程と、熱処理により前記
Au・Ge層と前記GaAs基板とを合金化する工程
を含むことを特徴とするオーム性電極の製造方
法。 ２ 前記のGaAs基板とAu・Ge層とを合金化す
る温度以下の温度に昇温し、ついで一定温度に保
つた後、合金化温度まで昇温し、前記Au・Ge層
と前記GaAs基板とを合金化することを特徴とす
る特許請求の範囲第１項記載のオーム性電極の製
造方法。 ３ 前記のGaAs基板とAu・Ge層とが合金化温
度に達するまで昇温速度を１〜100℃／分とする
ことを特徴とする特許請求の範囲第１項記載のオ
ーム性電極の製造方法。[Claims] 1. A step of depositing an Au/Ge layer on a GaAs substrate at a substrate temperature below the temperature at which the Au/Ge layer and the GaAs substrate are alloyed, and a step of treating the substrate in the atmosphere. and a step of holding the substrate at a temperature below which the Au/Ge layer and the GaAs substrate become alloyed and under a reduced pressure below atmospheric pressure, and a step of holding the substrate under a reduced pressure below atmospheric pressure, and heat treatment to
A method for manufacturing an ohmic electrode, comprising the step of alloying an Au/Ge layer and the GaAs substrate. 2 The temperature is raised to a temperature below the temperature at which the GaAs substrate and the Au/Ge layer are alloyed, and then the temperature is maintained at a constant temperature, and then the temperature is raised to the alloying temperature, and the Au/Ge layer and the GaAs substrate are heated. 2. The method for manufacturing an ohmic electrode according to claim 1, wherein the ohmic electrode is alloyed with: 3. The method of manufacturing an ohmic electrode according to claim 1, characterized in that the temperature increase rate is 1 to 100° C./min until the GaAs substrate and the Au/Ge layer reach an alloying temperature. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32381A JPS57114229A (en) | 1981-01-07 | 1981-01-07 | Manufacture of ohmic electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32381A JPS57114229A (en) | 1981-01-07 | 1981-01-07 | Manufacture of ohmic electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57114229A JPS57114229A (en) | 1982-07-16 |
| JPS632135B2 true JPS632135B2 (en) | 1988-01-18 |
Family
ID=11470689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32381A Granted JPS57114229A (en) | 1981-01-07 | 1981-01-07 | Manufacture of ohmic electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57114229A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5194765A (en) * | 1975-02-19 | 1976-08-19 | Kagobutsuhandotaino oomuseidenkyoku | |
| JPS54152483A (en) * | 1978-05-23 | 1979-11-30 | Toshiba Corp | Forming method for electrode of compound semiconductor light-emitting element |
| JPS55145366A (en) * | 1979-04-27 | 1980-11-12 | Mitsubishi Electric Corp | Ohmic electrode of n-type semiconductor of groups 3-5 metals in periodic table and forming method of the same |
-
1981
- 1981-01-07 JP JP32381A patent/JPS57114229A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5194765A (en) * | 1975-02-19 | 1976-08-19 | Kagobutsuhandotaino oomuseidenkyoku | |
| JPS54152483A (en) * | 1978-05-23 | 1979-11-30 | Toshiba Corp | Forming method for electrode of compound semiconductor light-emitting element |
| JPS55145366A (en) * | 1979-04-27 | 1980-11-12 | Mitsubishi Electric Corp | Ohmic electrode of n-type semiconductor of groups 3-5 metals in periodic table and forming method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57114229A (en) | 1982-07-16 |
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