JPS6321207B2 - - Google Patents

Info

Publication number
JPS6321207B2
JPS6321207B2 JP54138997A JP13899779A JPS6321207B2 JP S6321207 B2 JPS6321207 B2 JP S6321207B2 JP 54138997 A JP54138997 A JP 54138997A JP 13899779 A JP13899779 A JP 13899779A JP S6321207 B2 JPS6321207 B2 JP S6321207B2
Authority
JP
Japan
Prior art keywords
reactive power
multiplier
current
component
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54138997A
Other languages
Japanese (ja)
Other versions
JPS5663622A (en
Inventor
Atsushi Nishidai
Shinichiro Nishimura
Takashi Masuda
Makoto Azuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissin Electric Co Ltd
Original Assignee
Nissin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissin Electric Co Ltd filed Critical Nissin Electric Co Ltd
Priority to JP13899779A priority Critical patent/JPS5663622A/en
Publication of JPS5663622A publication Critical patent/JPS5663622A/en
Priority to JP62014417A priority patent/JPH0621968B2/en
Publication of JPS6321207B2 publication Critical patent/JPS6321207B2/ja
Granted legal-status Critical Current

Links

Classifications

    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02BINTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B75/00Other engines
    • F02B75/02Engines characterised by their cycles, e.g. six-stroke
    • F02B2075/022Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
    • F02B2075/027Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle four

Landscapes

  • Control Of Electrical Variables (AREA)
  • Supply And Distribution Of Alternating Current (AREA)

Description

【発明の詳細な説明】 例えば、アーク炉の運転により生ずるようなフ
リツカを抑制するには、その無効電力変動の補償
をする必要があり、このような目的に副うものと
してサイリスタ形無効電力補償装置の適用が考え
られる。第1図はサイリスタ形無効電力補償装置
の構成を説明するための概略図である。系統に変
圧器T1,T2を介してアーク炉F1,F2が接続さ
れ、これと並列に変圧器T3を介してリアクトル
Reと双方向に通電可能のようにサイリスタThを
逆並列に接続した通電制御素子とを直列とした遅
相無効電力調整回路とコンデンサCおよびインダ
クタンスLよりなる進相コンデンサ兼フイルタ回
路が接続される。そしてアーク炉F1,F2の電流
を検出する変流器CT1,CT2と電圧変成器PTと
より、無効電力検出器DDにおいて、時々刻々の
無効電力成分が計算され、変動する無効電力は基
準値と比較され、基準値より正又は負の大きさに
従つてサイリスタの点弧制御端子に加えられるパ
ルス位相を制御するような制御パルス発生装置
PGに加えられ、この制御パルス発生装置PGの出
力端はサイリスタの点弧制御端子に接続され、無
効電力の制御が行われる。パルスがある位相から
遅らされれば、リアクトルReを流れる電流は減
少し、系統電圧は上昇する。
Detailed Description of the Invention For example, in order to suppress flicker caused by the operation of an arc furnace, it is necessary to compensate for the fluctuations in reactive power. The application of the device is considered. FIG. 1 is a schematic diagram for explaining the configuration of a thyristor type reactive power compensator. Arc furnaces F 1 and F 2 are connected to the grid via transformers T 1 and T 2 , and a reactor is connected in parallel to this via transformer T 3 .
A phase-advancing capacitor/filter circuit consisting of a capacitor C and an inductance L is connected to a lagging reactive power adjustment circuit in which Re is connected in series with a energization control element in which a thyristor Th is connected in antiparallel so that current can be passed in both directions. . Then, the reactive power detector DD calculates the reactive power component from time to time by the current transformers CT 1 and CT 2 and the voltage transformer PT that detect the currents of the arc furnaces F 1 and F 2 , and the reactive power component is calculated from time to time. is compared with a reference value, and the pulse phase applied to the firing control terminal of the thyristor is controlled according to the positive or negative magnitude of the reference value.
The output terminal of the control pulse generator PG is connected to the ignition control terminal of the thyristor to control the reactive power. If the pulse is delayed from a certain phase, the current flowing through the reactor Re decreases and the grid voltage increases.

上述の無効電力を検出するのに、電圧の90度遅
相波形と電流の乗算を行い、乗算により生ずる第
2高調波分を低域ろ波器(以下LPFという)に
よつて除去するような構成のものが知られている
が、このような構成のものではLPFの性質上急
速な無効電力Qの変化に追随できず、そのため、
フリツカ対策のような速い変動を検出し、この変
動を直ちに系統制御に反映させる必要があるよう
なものに対しては適切でない。
In order to detect the above-mentioned reactive power, the 90 degree phase-lag waveform of the voltage is multiplied by the current, and the second harmonic component generated by the multiplication is removed by a low-pass filter (hereinafter referred to as LPF). Although some configurations are known, such configurations cannot follow rapid changes in reactive power Q due to the nature of the LPF, and therefore,
It is not suitable for things such as anti-flicker measures, where rapid fluctuations need to be detected and these fluctuations immediately reflected in system control.

本発明は前述のようにLPF使用による検出の
遅延を解消し、制御の際、誤制御の要因となるよ
うな制御信号の発生を未然に防止する無効電力検
出回路を備えた無効電力補償装置にある。
As described above, the present invention provides a reactive power compensator equipped with a reactive power detection circuit that eliminates the detection delay caused by the use of an LPF and prevents the generation of control signals that may cause erroneous control during control. be.

以下第2図に示す実施例および第3図の波形説
明図に基づいて本発明を説明する。第2図におい
て母線に電圧変成器PTおよび変動負荷Lvおよび
リアクトルReと双方向に通電する逆並列接続の
サイリスタThの直列回路および進相兼フイルタ
ー用のコンデンサCが並列に接続される。なお
L1は電源線路のインダクタンスを示している。
The present invention will be described below based on the embodiment shown in FIG. 2 and the waveform explanatory diagram in FIG. In FIG. 2, a series circuit of a voltage transformer PT, a variable load Lv, a reactor Re, an antiparallel-connected thyristor Th that conducts current in both directions, and a phase advance/filter capacitor C are connected in parallel to the bus bar. In addition
L 1 indicates the inductance of the power line.

電圧変成器PTの2次側は90度位相器PSに接続
され、90度位相器PSの出力側は乗算器X1に接続
され、一方、変動負荷Lvの電流Iを検出する変
流器CTが変動負荷Lvに結合され、その2次側は
乗算器X1に接続される。
The secondary side of the voltage transformer PT is connected to a 90 degree phase shifter PS, and the output side of the 90 degree phase shifter PS is connected to a multiplier X 1 , while the current transformer CT detects the current I of the variable load Lv. is coupled to a variable load Lv, and its secondary side is connected to a multiplier X1 .

乗算器X1に90度遅相波形の系統電圧V90と負荷
電流Iとを入れれば、無効電力が算出されるが、
両者の積をとることによつて先に述べたように直
流分中に2倍周波数の交流分が残る。この交流分
を除去、平滑化するため乗算器X1よりの出力は、
T1=1/4f、つまり1/4サイリスタに相当する時間 遅延を与える遅延回路TCに入力され、この遅延
回路TCを通した遅延無効電力信号Qとこの遅延
回路を経由しない直接無効電力信号Qとは加算器
A1において加算され、第3図に示すように2Q
がその出力側に現われる。この際前記系統電圧V
と負荷電流Iの乗算により生じた双方の無効電力
信号Qの第2高調波分は互に打消されてリツプル
は消去される。
If the system voltage V 90 with a 90-degree phase-lag waveform and the load current I are input into the multiplier X 1 , the reactive power can be calculated.
By taking the product of the two, an alternating current component of twice the frequency remains in the direct current component, as described above. To remove and smooth this alternating current component, the output from multiplier X1 is
T 1 = 1/4f, that is, input to a delay circuit TC that provides a time delay equivalent to a 1/4 thyristor, and a delayed reactive power signal Q that passes through this delay circuit TC and a direct reactive power signal Q that does not go through this delay circuit. is an adder
A 1 is added and 2Q is added as shown in Figure 3.
appears on its output side. At this time, the system voltage V
The second harmonic components of both reactive power signals Q generated by multiplying by the load current I and the load current I cancel each other out, and the ripple is eliminated.

このように加算器A1の出力に第2高調波分は
殆んど含まれず、負荷無効電力変動に即応した誤
差の極めてすくない無効電力信号Qを発生する、
この信号Qは無効電力位相変換回路QPSを経て、
制御パルス発生装置PGに入力し、その出力によ
りリアクトルReに接続されたサイリスタThの点
弧制御により補償無効電力を制御する。
In this way, the output of the adder A1 contains almost no second harmonic component, and generates a reactive power signal Q with extremely small errors that quickly responds to load reactive power fluctuations.
This signal Q passes through the reactive power phase conversion circuit QPS,
It is input to the control pulse generator PG, and its output controls the compensation reactive power by controlling the firing of the thyristor Th connected to the reactor Re.

次に第4図に示す実施例について説明する。第
2図と同一部分は同一符号で示す。
Next, the embodiment shown in FIG. 4 will be described. The same parts as in FIG. 2 are indicated by the same reference numerals.

第2図の実施例により説明したように、無効電
力瞬時値を加算器A1において出力することがで
きるが、乗算器X1に入力する負荷電流のうち、
有効電力成分に相当する電流を差引けば、この乗
算器X1に入力される電流の振幅を小ならしめる
ことができ、乗算器X1出力(無効電力出力)に
含有される第2高調波リツプルを小ならしめるこ
とができる。
As explained in the embodiment of FIG. 2, the instantaneous value of reactive power can be output at the adder A1 , but of the load current input to the multiplier X1 ,
By subtracting the current corresponding to the active power component, the amplitude of the current input to this multiplier X1 can be reduced, and the second harmonic contained in the multiplier X1 output (reactive power output) can be reduced. Ripple can be reduced.

第4図の実施例においては、第2図の実施例の
回路に、有効電力成分に該当する電流成分を発生
し、これを負荷電流Iより差引いて乗算器X1
入力させる回路が設けられている。
In the embodiment of FIG. 4, a circuit is added to the circuit of the embodiment of FIG. 2 to generate a current component corresponding to the active power component, subtract it from the load current I, and input it to the multiplier X1 . ing.

図示のように系統電圧Vと負荷電流Iが乗算器
X2に入力し、乗算器X2の出力は低域ろ波器LPF1
を通り、乗算器X3に入力し、乗算器X3には系統
電圧Vが入力する。
As shown in the figure, the system voltage V and load current I are multipliers.
X 2 and the output of multiplier X 2 is the low pass filter LPF 1
, and is input to the multiplier X 3 , and the system voltage V is input to the multiplier X 3 .

系統電圧Vと負荷電流Iとの乗算により、有効
電力成分が発生するが、これには第2高調波が含
有されるので、LPF1で除去、平滑化する。電圧
波形と同相で有効電力Pに比例した波形が目的と
する有効電力成分に該当する電流成分であるの
で、これを乗算器X3によつて発生させる。この
電流成分をIpとすれば、Ip sinωt∝P×V
sinωtで表わされる。
An active power component is generated by multiplying the system voltage V and the load current I, but since this contains a second harmonic, it is removed and smoothed by LPF 1 . Since a waveform in phase with the voltage waveform and proportional to the active power P is a current component corresponding to the target active power component, this is generated by the multiplier X3 . If this current component is Ip, Ip sinωt∝P×V
It is expressed as sinωt.

有効電力成分は上述のようにLPF1を通される
ので、有効電力成分に変化があつても、Ipはなだ
らかな変化を有するIpavとして現われる。この
Ipavは第2高調波リツプルの小さいものであり、
Ipを減算器Sで負荷電流Iより差引いて乗算器
X1に入力する。これにより、負荷電流I中の有
効電流成分を除去して乗算器X1に入力している
ので、乗算器X1よりの出力に含まれる第2高調
波分を減少させることができる。以下は第2図に
示した実施例と同様に動作する。
Since the active power component is passed through LPF 1 as described above, even if there is a change in the active power component, Ip appears as Ipav with a gentle change. this
Ipav has a small second harmonic ripple,
Ip is subtracted from the load current I by subtractor S and multiplier
Enter X1 . As a result, the effective current component in the load current I is removed and input to the multiplier X1 , so it is possible to reduce the second harmonic component included in the output from the multiplier X1 . The following operation is similar to the embodiment shown in FIG.

次に第5図に示す実施例について説明する。第
2図と同一部分は同一符号で示す。
Next, the embodiment shown in FIG. 5 will be described. The same parts as in FIG. 2 are indicated by the same reference numerals.

乗算器X1で乗算される無効電力成分中には、
装置運転中に、発生する無効電力のうち、比較的
長い時間変動に関与しない準定常分が含まれてお
り、上記乗算器X1による演算によれば、比較的
ながい時間変動に関与しない無効電流成分も含有
された演算が行われ、従つて演算によつて生じる
第2高調波分も大きくなる。この実施例は、第2
図の実施例の回路に無効電力の準定常分に相当す
る電流を負荷電流Iより差引いて乗算器X1に入
力させる回路を設け、これによつて第2高調波リ
ツプルを小さならしめたものである。
During the reactive power component multiplied by multiplier X 1 ,
Of the reactive power generated during equipment operation, a quasi-stationary component that is not involved in relatively long time fluctuations is included, and according to the calculation by the multiplier The computation that also includes the component is performed, and therefore the second harmonic component generated by the computation also becomes large. In this example, the second
The circuit of the embodiment shown in the figure is provided with a circuit that subtracts the current corresponding to the quasi-steady portion of the reactive power from the load current I and inputs it to the multiplier X1 , thereby reducing the second harmonic ripple. It is.

図示のように、系統電圧Vを90度遅相波形と負
荷電流Iを乗算器X4に入力して、無効電力を演
算し、前記無効電力出力を低域ろ波器LPF2によ
つて除去、平滑化する。この場合、LPF2の特性
を数秒程度の長い時定数を有するものに選ぶこと
によつて無効電力の変動成分は平均化されて現わ
れず、準定常的な無効電力を得ることができる。
As shown in the figure, the reactive power is calculated by inputting the 90-degree delayed phase waveform of the grid voltage V and the load current I to a multiplier X4 , and the reactive power output is removed by a low-pass filter LPF2. , smooth. In this case, by selecting the characteristics of the LPF 2 to have a long time constant of about several seconds, the fluctuating components of the reactive power are averaged out and do not appear, and quasi-steady reactive power can be obtained.

電圧波形から90度遅相し且つ振巾が上記準定常
無効電力値Qに比例する波形が目的とする無効電
力準定常成分に該当する電流成分であるので、こ
れを電圧波形の90度遅相電圧と前記準定常無効電
力とを乗算器X5に入れると、平均的な無効電流
成分Iqavを得ることができる。Iqav sinωt∝Q
×V sin(ωt−90゜で表わされる。このIqavは第
2高調波リツプルの小さいものであり、Iqavを
減算器Sで負荷電流Iより差引いて乗算器X1
入力する。これにより、負荷電流I中の準定常無
効電流成分を除去して乗算器X1に入力している
ので、乗算器X1よりの出力に含まれる第2高調
波分を減少させることができる。以下は第2図に
示した実施例と同様に動作する。
The waveform that is 90 degrees behind the voltage waveform and whose amplitude is proportional to the quasi-steady reactive power value Q is the current component that corresponds to the target quasi-steady reactive power component, so this is the current component that is 90 degrees behind the voltage waveform. By inputting the voltage and the quasi-stationary reactive power into a multiplier X5 , an average reactive current component Iqav can be obtained. Iqav sinωt∝Q
×V sin (expressed as ωt−90°. This Iqav has a small second harmonic ripple, and Iqav is subtracted from the load current I by a subtracter S and input to the multiplier Since the quasi-stationary reactive current component in the current I is removed and input to the multiplier X1 , it is possible to reduce the second harmonic component included in the output from the multiplier X1 . It operates similarly to the embodiment shown in the figure.

第6図は第4図、第5図の実施例において、負
荷電流中の有効電流成分と準定常無効電流成分を
差引き、更に乗算器X1への入力を変動分のみに
減少させたものである。
Figure 6 shows the embodiment of Figures 4 and 5 in which the active current component and the quasi-steady reactive current component in the load current are subtracted, and the input to multiplier X1 is further reduced to only the variation. It is.

前記の有効電流成分Ipavおよび準定常無効電
流成分Iqavはそれぞれ第2高調波リツプルのす
くないものであり、これを加算器A2で加算すれ
ば、有効電流成分Ipavは系統電圧と同相にあり、
Iqavは90度遅れた電圧相にあり、これらの電流
成分の合成によつて負荷電流Iの大きさおよび位
相に近い電流を発生させることができる。減算器
Sにおいて負荷電流Iより有効電流成分、無効電
流成分が差引かれ、I−(Ipav+Iqav)が乗算器
X1に入力され、一方90度遅相の電圧が入力され
る。すでに説明したように乗算器X1の出力は1/4 サイクルに相当する時間の遅延を与える遅延回路
TCに入力されその出力側は加算器A1と接続さ
れ、加算器A1は乗算器X1の出力端とも接続され
ているので、無効電力Δqの2倍に相当する出力
が加算器A1の出力端に現われる。Δqは当然正又
負である。無効電力に瞬発的な変動を生じた場
合、前述のように無効電力に該当する無効電流を
発生させる回路には特定数の大きいLPF2が用い
られており、このような急激な変動は平滑化さ
れ、従つて平均等な無効電流成分Iqavにはなだ
らかな変動としてのみしか現われない。負荷電流
I中より無効電流成分Iqavおよび又は有効電流
成分Ipavが差引かれると、I―(Ipav+Iqav)
によつて発生する無効電力値Δqは殆んど急激な
変動に基づいて生ずるものとすることができる。
この無効電力値Δqを無効電力位相変換回路QPS
を経て制御パルス発生装置PGに入力させその出
力によりリアクトルReに接続されたサイリスタ
Thの点弧位相の制御により無効電力を制御する。
The active current component Ipav and the quasi-steady reactive current component Iqav each have little second harmonic ripple, and if they are added by adder A2 , the active current component Ipav is in phase with the grid voltage,
Iqav is in a voltage phase delayed by 90 degrees, and by combining these current components, it is possible to generate a current close to the magnitude and phase of the load current I. The active current component and the reactive current component are subtracted from the load current I in the subtracter S, and I-(Ipav+Iqav) is added to the multiplier.
The voltage is input to X 1 , while the voltage with a phase lag of 90 degrees is input. As already explained, the output of multiplier X1 is a delay circuit that provides a time delay corresponding to 1/4 cycle.
It is input to TC and its output side is connected to adder A 1 , and adder A 1 is also connected to the output end of multiplier X 1 , so the output corresponding to twice the reactive power Δq is output from adder A 1. appears at the output end of Δq is naturally positive or negative. When instantaneous fluctuations occur in reactive power, as mentioned above, a large LPF 2 with a specific number is used in the circuit that generates the reactive current corresponding to reactive power, and such sudden fluctuations are smoothed out. Therefore, it appears only as a gentle fluctuation in the average reactive current component Iqav. When reactive current component Iqav and/or active current component Ipav are subtracted from load current I, I-(Ipav+Iqav)
It can be assumed that the reactive power value Δq generated by .
This reactive power value Δq is converted to the reactive power phase conversion circuit QPS.
The thyristor is input to the control pulse generator PG via the
Reactive power is controlled by controlling the firing phase of Th.

なお以上の説明においては説明を簡単にするた
め回路を構成する各要素の係数、定数が説明され
ていないが、当業者において理解されるところで
あるので省略した。
In the above description, in order to simplify the explanation, the coefficients and constants of each element constituting the circuit are not explained, but they are omitted because they would be understood by those skilled in the art.

以上述べたように、本発明においては検出値に
第2高調波リツプルが含まれることが極めて少な
く、且つLPFを用いてリツプルを除去した時の
ような動作の遅れがないため、高速度の無効電力
制御を要求されるようなフリツカ対策等に用いら
れる無効電力補償装置に極めて好適なものという
ことができる。
As described above, in the present invention, second harmonic ripple is extremely unlikely to be included in the detected value, and there is no delay in operation unlike when ripples are removed using an LPF, so high-speed invalidation is possible. It can be said that it is extremely suitable for a reactive power compensator used for flicker countermeasures that require power control.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はサイリスタ形無効電力補償装置の1例
を示し、第2図、第4図、第5図、第6図はそれ
ぞれ本発明の実施例の無効電力補償装置を示し、
第3図は本発明の一部説明のための図面である。 PT…電圧変成器、CT,CT1,CT2…変流器、
T1,T2,T3…変圧器、C…コンデンサ、L,L1
…インダクタンス、Th…サイリスタ、X1,X2
X3,X4,X5…乗算器、A1,A2…加算器、S…減
算器、LPF1,LPF2…低域ろ波器、TC…遅延回
路、PS移相器、PG…制御パルス発生装置、F1
F2…アーク炉、Lv…変動負荷、QPS…無効電力
位相変換回路。
FIG. 1 shows an example of a thyristor-type reactive power compensator, and FIGS. 2, 4, 5, and 6 each show a reactive power compensator according to an embodiment of the present invention,
FIG. 3 is a drawing for partially explaining the present invention. PT...Voltage transformer, CT, CT 1 , CT 2 ...Current transformer,
T1 , T2 , T3 ...Transformer, C...Capacitor, L, L1
...Inductance, Th...Thyristor, X 1 , X 2 ,
X 3 , _ _ _ _ Control pulse generator, F 1 ,
F 2 ...Arc furnace, Lv...Variable load, QPS...Reactive power phase conversion circuit.

Claims (1)

【特許請求の範囲】 1 90度遅相の電圧と負荷電流とを乗算する乗算
器とこの乗算による無効電力成分に1/4サイクル
に相当する時間遅延を与える遅延回路とこの遅延
回路の出力側に加算器を接続するとともに、この
加算器は前記乗算器の出力とも接続され、該加算
器において、前記遅延回路を介入して入力される
遅延無効電力信号と前記乗算器より直接入力され
る直接無効電力信号とを加算せしめて前記乗算に
より生じた第2高調波分を打消し、この加算器出
力には第2高調波分を殆んど含まない無効電力成
分を発生させ、この無効電力成分に従つて、リア
クトルの通電制御を行うことを特徴とする無効電
力補償装置。 2 入力される負荷電流中、有効電力に相当する
電流成分を除去して乗算器への入力電流値を小な
らしめたことを特徴とする特許請求の範囲第1項
記載の無効電力補償装置。 3 入力される負荷電流中準定常的な無効電力に
相当する電流成分を除去して前記乗算器への入力
電流値を小ならしめたことを特徴とする特許請求
の範囲第1項記載の無効電力補償装置。 4 入力される負荷電流中、有効電力に相当する
電流成分と準定常的な無効電力に相当する電流成
分を除去して乗算器への入力電流値を小ならしめ
たことを特徴とする特許請求の範囲第1項記載の
無効電力補償装置。
[Claims] 1. A multiplier that multiplies a 90-degree phase-lag voltage and a load current, a delay circuit that provides a time delay corresponding to 1/4 cycle to the reactive power component resulting from this multiplication, and the output side of this delay circuit. An adder is connected to the multiplier, and the adder is also connected to the output of the multiplier. The second harmonic component generated by the multiplication is canceled by adding the reactive power signal to the reactive power signal, and the output of this adder generates a reactive power component that hardly contains the second harmonic component. A reactive power compensator characterized in that it controls energization of a reactor according to the following. 2. The reactive power compensator according to claim 1, wherein a current component corresponding to active power is removed from the input load current to reduce the input current value to the multiplier. 3. The invalidity according to claim 1, characterized in that the input current value to the multiplier is reduced by removing a current component corresponding to quasi-steady reactive power from the input load current. Power compensator. 4. A patent claim characterized in that a current component corresponding to active power and a current component corresponding to quasi-steady reactive power are removed from the input load current to reduce the input current value to the multiplier. The reactive power compensator according to item 1.
JP13899779A 1979-10-27 1979-10-27 Compensating device for reactive electric power Granted JPS5663622A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP13899779A JPS5663622A (en) 1979-10-27 1979-10-27 Compensating device for reactive electric power
JP62014417A JPH0621968B2 (en) 1979-10-27 1987-01-23 Control circuit of reactive power compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13899779A JPS5663622A (en) 1979-10-27 1979-10-27 Compensating device for reactive electric power

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP62014417A Division JPH0621968B2 (en) 1979-10-27 1987-01-23 Control circuit of reactive power compensator

Publications (2)

Publication Number Publication Date
JPS5663622A JPS5663622A (en) 1981-05-30
JPS6321207B2 true JPS6321207B2 (en) 1988-05-06

Family

ID=15235058

Family Applications (2)

Application Number Title Priority Date Filing Date
JP13899779A Granted JPS5663622A (en) 1979-10-27 1979-10-27 Compensating device for reactive electric power
JP62014417A Expired - Lifetime JPH0621968B2 (en) 1979-10-27 1987-01-23 Control circuit of reactive power compensator

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP62014417A Expired - Lifetime JPH0621968B2 (en) 1979-10-27 1987-01-23 Control circuit of reactive power compensator

Country Status (1)

Country Link
JP (2) JPS5663622A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49121128A (en) * 1973-03-27 1974-11-19
JPS5123648A (en) * 1974-08-22 1976-02-25 Fuji Electric Co Ltd

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525452A (en) * 1975-07-01 1977-01-17 Fuji Electric Co Ltd Control process of reactive power readjusting system
JPS5366550A (en) * 1976-11-26 1978-06-14 Mitsubishi Electric Corp Control circuit for reactive power compensator
JPS547978A (en) * 1977-06-20 1979-01-20 Torio Kk Audio wattmeter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49121128A (en) * 1973-03-27 1974-11-19
JPS5123648A (en) * 1974-08-22 1976-02-25 Fuji Electric Co Ltd

Also Published As

Publication number Publication date
JPH0621968B2 (en) 1994-03-23
JPS5663622A (en) 1981-05-30
JPS62241015A (en) 1987-10-21

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