JPH07236230A - Controller for voltage fluctuation suppresser - Google Patents

Abstract

PURPOSE:To efficiently compensate for the instantaneous voltage fluctuation of each phase and three-phase imbalance voltage fluctuation caused by the three-phase imbalance voltage of receiving power and the fluctuation in reactive power consumption of a load. CONSTITUTION:In the DELTAV detection control for a thyristor control reactor(TCR) where a bias voltage having a waiting operation point at about half of the maximum output of the TCR is added to the voltage fluctuation DELTAV of a system detected for each phase, the bias voltage is shifted by the imbalance component of each phase detected by comparing each phase voltage VU, VV, VW detected as a DC voltage with a three-phase average voltage V3 represented as a DC voltage thus suppressing the three-phase imbalance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a reactive power compensator (hereinafter referred to as SVC) arranged for the purpose of suppressing voltage fluctuations in a three-phase power system, and particularly, at the same time as suppressing voltage fluctuations in each phase. An object of the present invention is to provide a control device that suppresses three-phase unbalanced voltage fluctuations.

[0002]

2. Description of the Related Art SVC is a voltage fluctuation ΔV (≈X _S · ΔQ due to a reactive power fluctuation ΔQ _L of a load such as a power converter installed in a power system by compensating an increase / decrease of reactive power ΔQ _SVC.
L ) is suppressed (however, X _S is the impedance on the power supply side).

This SVC is used not only for suppressing the above-mentioned voltage fluctuation for each phase, but also for suppressing three-phase unbalance of the system voltage.

This prior art example is Japanese Patent Laid-Open No. 59-18512.
The voltage fluctuation suppressing device disclosed in Japanese Patent No. 4 compares the voltage detected for each phase with a fixed reference value V _ref and compares the voltage fluctuation ΔV for each phase.
Is detected, and the SVC is directly converted into a fluctuation component of the line voltage to be compensated, and then the SVC is controlled.

In the above-mentioned conventional method, the detected phase voltage is compared with a common fixed reference value V _ref, and compensation is performed so that the difference becomes 0. Therefore, the voltage fluctuation of each phase is suppressed and the three-phase voltage is not applied. Equilibrium will also be suppressed.

[0006]

[Problems to be Solved by the Invention] Installed capacity Q of SVC
_{The SVC} is set to a size capable of compensating for a predetermined range of the voltage fluctuation ΔV (for example, 10% of the rated voltage of the system) for economic reasons. Then, the voltage fluctuation is suppressed by the increase / decrease control in which the output is narrowed down with respect to the voltage decrease and the output is increased with respect to the voltage increase around the predetermined standby operation point. Therefore, it is preferable to adjust the standby operation point to about ½Q _SVC so that the compensation operation can be performed uniformly in either the increase or decrease direction in order to effectively use the equipment and improve the performance.

However, in the above-mentioned conventional method, the detected system voltage is compared with a fixed reference value V _ref, and SV is determined by the difference between them.
Since the output of C is determined, there is a problem that the standby operating point varies depending on the state of the system and becomes unclear. For example,
If the long-cycle component of the system voltage fluctuates due to fluctuations in the tap position of the power receiving transformer and the power receiving voltage, the standby operating point of the SVC may move to the upper or lower limit. In this case, the output is increased or decreased according to ΔV. Not only the original compensation operation of the SVC cannot be performed, but also the three-phase unbalanced voltage fluctuation is further increased.

Considering the performance required of the voltage fluctuation suppressing device, for example, in the case of compensating for voltage fluctuations due to load operation of a heavy particle accelerating power source, ΔV≈, including the three-phase imbalance. It is necessary to suppress the 10% fluctuation to about ΔVε≈1%. Here, the three-phase unbalance is the result of a slight increase in the three-phase unbalanced voltage of the power source due to the constant current control of the three-phase load, and ΔV ₃ ≈ several% unbalance is expected,
It is necessary to compensate for this by ΔV ₃ ε≈0.

In order to obtain such compensation performance, it is necessary to compensate for voltage fluctuations in each phase and three-phase voltage imbalance as instantaneously as possible to reduce the control error due to response delay.

Therefore, the present invention provides a control system of SVC capable of suppressing the instantaneous voltage fluctuation of each phase with a high response speed while eliminating the three-phase imbalance while optimizing the standby operating point. To aim.

[0011]

The present invention proposes the following two systems as a voltage fluctuation suppressing device for suppressing voltage fluctuations in a three-phase power system by compensating the increase / decrease of reactive power by a thyristor control reactor.

The first control method is to detect the system voltage and
It controls VC, and voltage fluctuation ΔV detected for each phase
To the control signal generating circuit for adding a bias voltage having about 1/2 of the maximum output of the thyristor control reactor as a standby operation point to generate a control signal V _C for each phase of the thyristor control reactor, and converting it to a direct current for detection. Voltage V _{U of} each phase
An imbalance suppression circuit that compares V _V and V _W with a DC-converted three-phase average voltage V ₃ and shifts the bias voltage of each phase so as to eliminate the three-phase voltage imbalance by the difference. It is characterized by having done.

[0013] The second control method is for controlling the SVC detects the reactive power Q _L of the load, the reactive power fluctuation ΔQ of the load detected for each phase, a bias voltage that determines the standby operating point A control signal generation circuit that adds up the control signal V _C of each phase of the thyristor control reactor and the reactive power Q _LU , Q _LV , and _QL W of the load of each phase detected by converting it to DC,
An imbalance suppression circuit that compares the reactive power Q _{3 of the} averaged three-phase DC and shifts the bias voltage of each phase so as to eliminate the reactive power imbalance of the three phases by the difference. Characterize.

[0014]

In the first control method, the SVC output is controlled to increase or decrease from a predetermined standby operation point by the voltage fluctuation ΔV detected for each phase in the control signal generating circuit to suppress the instantaneous voltage transformation.

This voltage fluctuation ΔV can be detected at high speed by removing the long-cycle component of its output by negative feedback while proportionally integrating (PI) the DC-converted phase voltages.
In addition, the unbalance suppression circuit reduces the DC voltage of each phase to 3
The unbalanced voltage of each phase is detected by comparing with the phase average voltage V ₃ .
From the half of the maximum output of SVC, the standby operating point
By shifting by this unbalanced voltage, the voltage unbalance is suppressed. The three-phase average voltage used for detecting the unbalanced voltage can be obtained by instantaneously adding the squared voltages of the respective phases with an analog adder, thereby eliminating the response delay and accurately controlling the unbalanced voltage.

The second control method controls the SVC by detecting the reactive power of the load that causes the voltage fluctuation. In principle, it is the same as the first control method except that the detection target is different. Is. The second control method is feed-forward control, a faster response is obtained compared to the first method, and improvement in compensation performance can be expected.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first control system of the present invention for detecting system voltages V _U , V _V and V _W to control SVC.

[0018] In 3-phase power system of Figure 1, 1 denotes a system bus, connected to the substation power E _S through the power side impedance X _S are powering the three-phase load 2 such as the power converter. An SVC that suppresses voltage fluctuations is installed on the system bus 1.

The SVC is a system in which a thyristor control reactor (hereinafter referred to as TCR) and a filter (hereinafter referred to as FL) are connected in parallel to a system bus 1. In the TCR, a high impedance transformer 3 and an antiparallel connection thyristor 4 are connected in series. Connected and configured. In addition, this high impedance transformer 3
May consist of a conventional transformer and reactor. The TCR and FL are installed for each phase.

The SVC control device 5 includes a DC conversion circuit 6 for DC-detecting the voltage of each phase, an average voltage detector 7 for calculating a three-phase average voltage, and an SVC control signal V _C for each phase. The control signal generation circuits 8 _U , 8 _V , and 8 _W to be created, and the unbalanced control circuit 9 that detects the unbalanced voltage of each phase and shifts the bias voltage of the control signal V _C accordingly, and the control signal V.
_It is composed of phase control circuits 10 _U , 10 _V and 10 _W for generating a gate pulse of TCR according to _C. These circuits have the same configuration for each phase except the shared average voltage detector 7.

First, the DC conversion circuit 6 will be described. 11
Is a square-law detector, which squares the voltages V _U , V _V , and V _W of each phase extracted by the voltage transformer PT to convert the voltage into DC. Reference numeral 12 is a band reject filter (hereinafter referred to as BRF).
The ripple component generated by the multiplication operation is removed.

The square wave detector 1 in the DC conversion circuit 6
The principle of DC voltage detection of the phase voltage using 1 and BRF 12 will be described.

[Equation 1] Becomes

Normally, the system voltage V _S is the third harmonic and the fifth harmonic.
Since waveform distortion occurs due to harmonics, etc., the actual equation (1) contains harmonic components as follows. ^{_{V 2 S = V 2 L (}} cos2ωt + 1) + V L · V N · {cos (ω N + ω) t + cos (ω N -ω) t} + V 2 N · cos (2ωnt + 1) ......... (2) V L> since in> V _N, a (2) wherein the right side third term ≒ 0.

Therefore, it suffices to consider the removal of the ripple components of the first and second terms.

[Equation 2] The TwinT circuit (BRF) 12 of is used.

This BRF depends on the hard circuit constant.

[Equation 3] Can be approximated.

That is, with respect to the first term on the right side of the equation (2),
BRF of ω _N = 2π · f _N is ω _N = 4 for 2 terms.
The BRF of π · f _N is cascade-connected to the square wave detector 11 to individually remove each component.

As a result, V ² _L is obtained, and the DC component V _L of the system voltage V _S can be taken out by performing square root calculation. However, in the increase / decrease compensation performed by detecting only the ΔV change amount, the linearity of the detected value is small, and therefore the square root breaker is omitted in the illustrated example.

Next, the average voltage detector 7 will be described.
The average voltage detector 7 includes an adder 13 that collectively adds the squared values of the phase voltages created by the square detector 11 in three phases,
And a low pass filter (LPF) 14 for multiplying a predetermined coefficient and removing a ripple component,
The operating principle is as follows.

[0029]

[Equation 4]

When the squared values for these three phases are collectively added by the three-phase adder 13, the sum of the second term represented by the trigonometric function becomes 0, and the added value (V _TA ) ² becomes

[Equation 5] Therefore, if the addition gain is set to ⅓ and the switch is used for square root extraction, the three-phase average voltage V _L3 is obtained as a DC signal.

However, since the ripple is expected to occur due to the unbalance of the received voltage and the error of the detection system, the LPF 20
To remove this.

For example, as a problem to be solved by the present invention,
The concrete numerical example mentioned above [6 times ripple of about 10%,
Target to reduce to 1/100]. Commercial frequency
Number f _a= 50H_ZThen, f_r= 50 × 6 = 300H_Z,
Ripple rate ≈ 10% [2 sin (θ + π / 3)]
It

This ripple rate ≈ 10% is 1/100 (-
40 _C ), the LPC f _C is f _C = 300H
_{From Z} / 100 = 3H _Z , T ₃ = 1 / (2πf _C ) ≈50 m
Let s. Since the addition gain needs to be reduced to 1/3, the transfer function of the LPF is [-1 / 3 / (1 + S
T ₃ )]. The square root calculation described above is omitted because it corresponds to the processing of the DC circuit 6 in the illustrated example.

Next, the control signal generating circuits 8 _U , 8 _V and 8 _W will be described. The control signal generation circuits 8 _U , 8 _V , and 8 _W are a voltage fluctuation detector 18 composed of a proportional integration circuit 15, an integration circuit 16, and a subtractor 17, and an SVC standby operating point at the output of the detector 18. It is composed of an adder 19 and an aggregator 20 that add a bias voltage that determines

The output of the voltage fluctuation detector 18 is a proportional integral (PI) output obtained by passing the direct current signal through a proportional integral circuit 15 represented by a transfer function K ₂ / (1 + ST ₂ ). By the integration circuit 16 represented by the transfer function (−1 / ST ₃ )
By performing negative feedback in the subtractor 17, a complete integrator configuration is obtained, and only the fluctuation component ΔV of the DC signal is subjected to the steady deviation 0.
Therefore, it can be taken out at high speed.

Next, the unbalanced control circuit 9 for detecting the unbalanced voltage of each phase and shifting the bias voltage of the control signal V _C according to the detected unbalanced voltage will be described. The circuit 9 includes an adder 21, a proportional integration circuit 22, a reference voltage generator 23, an adder 24, and a coefficient unit 25.

The adder 21 adds the voltage detection values V _U , V _V and V _W of the DC conversion circuit 6 of its own phase and the output V ₃ (the inverted output of −) of the average voltage detector 18, The unbalanced voltage ΔV ₃ of each phase is detected.

The proportional-integral circuit 22 represented by the transfer function K ₄ / (1 + ST ₄ ) matches the detection response speed of the unbalanced voltage ΔV _{3 with} the detection response speed of the voltage fluctuation ΔV of each phase [ST ₄ = with the ST _2], to adjust the sensitivity of the unbalanced suppressed by factor K _4.

The adder 24 outputs the maximum output Q of the SVC output from the reference voltage generator 23 to the output of the proportional-plus-integral circuit 22.
Add the reference voltage corresponding to _SVC .

The coefficient unit 25 halves the output of the adder 24.
By doubling, the bias voltage for each phase is set to a value shifted from the voltage corresponding to about 1/2 of the maximum output of the SVC, which is the reference, by a value that eliminates the unbalanced component of each phase, and the control signal generation circuit 8 Output to the adder 19 for _U , 8 _V , and 8 _W.

The phase control circuits 10 _U , 10 _V and 10 _W are compared with the control signal V _C and the sawtooth wave power supply cycle signal V _PLL generated by the power supply synchronizing circuit 26, and are compared for each half-wave period of the commercial frequency. , TCR gate pulse is generated at the crossing timing. The control signal V _C , the firing angle β, and the TCR current I _TCR have the relationship shown in the lower right part of FIG. When the control signal V _C is 0V which is the minimum, the ignition angle β is the minimum, and the ignition is started in the earliest one control cycle,
The TCR current I _TCR is maximized, that is, the reactive power Q _TCR supplied to each phase is maximized, the firing angle β is delayed and the reactive power Q _TCR is decreased as the control signal V _C increases.

This compensation operation cancels the instantaneous voltage fluctuation ΔV of the system voltage V _L by the output change ΔQ _SVC of the reactive power from the standby operation point 1 / 2Q _SVC (ΔV-
X _S · ΔQ _TCR ≈ 0).

That is, since ΔV ₃ = 0 at the time of _three -phase equilibrium, the standby operation point of each phase of the SVC is 1 / 2ΔQ _SVC , and the output of the SVC is controlled to increase or decrease around this position, and the instantaneous value of each phase is increased. The voltage fluctuation ΔV is suppressed.

When three-phase unbalance occurs, the standby operating point of each phase becomes 1/2 due to the unbalance voltage ΔV ₃ detected for each phase.
It is automatically shifted to (ΔSVC ± ΔV ₃ ), and by compensating the reactive power ΔQ ₃ by this shift amount, unbalance is suppressed and the instantaneous voltage fluctuation is also suppressed while making the system voltage three-phase balanced.

Next, the suppression response time of voltage fluctuation will be examined. In the above-mentioned embodiment, Δ that suppresses the instantaneous voltage fluctuation ΔV
The performance of V detection control depends on how quickly and accurately the voltage fluctuation (AC) of the system is converted into an SVC control signal (DC signal without ripple). The delay element of the DC conversion circuit 6 that performs this is 2ωt in the output of the square-law detector 11.
BRF12, which removes components, has a response time of 5
It can be about ms, which is sufficient for practical use.

When this DC conversion circuit 6 is adopted, the automatic control loop constant of the control signal generating circuits 8 _U , 8 _V and 8 _W is 5
In 0H _Z basis, can the following values.

Loop gain G _L ( _W ) = ΔV · K ₂ …… 1 time Loop time constant τ _L ≈ST ₂ …… (half cycle / 10 ms) Reference time constant τ _ref ≈ST ₃ …… (several cycles /
50 ms).

Further, since the average voltage detector 7 instantaneously adds the squared detection outputs by alternating current, the detection response time becomes 0 in principle. However, in the actual system, it is necessary to consider the three-phase unbalance at the power receiving point and the voltage detection system error of each phase, and the LPF1 that removes the 6 times ripple (about 10%) of the commercial power supply
4 is added. The response time of this LPF14 is about 50
ms, which is sufficiently fast as the detection response time of the unbalanced voltage.

Next, the reactive powers Q _LU , Q _LV of the loads of each phase,
_QLW is detected and the Q control controls the instantaneous voltage fluctuation ΔV of each phase.
A second control method of the present invention for suppressing the unbalanced voltage ΔV ₃ will be described.

A configuration example in this case is as shown in FIG. In this circuit, instead of detecting the system voltage V _L , the system voltages V _U , V _V , and V _{W of} each phase detected by the voltage transformer PT and the load currents I _{LU of} each phase detected by the current transformer CT, I _LV , I
From _LW, by reactive power detector 27, the reactive power Q _LU of each phase of the load, and calculates the Q _LV, Q _LW, now detects the instantaneous reactive power fluctuation Delta] Q _L and reactive power imbalance Delta] Q ₃ of each phase . The instantaneous load fluctuations ΔQ _LU , ΔQ _LV , and ΔQ _LW of each phase are B
It is obtained by extracting the long-period component of the DC detection value of the reactive power obtained by removing the ripple component at RF12 by the integrating circuit 28 and subtracting it by the subtracter 29. The 3-phase unbalanced ΔV ₃ of the system voltage is the result of the slight 3-phase unbalanced voltage of the power receiving source being increased by the constant current control of the 3-phase load, so the unbalanced component ΔQ ₃ of the reactive power should be detected. This makes it possible to suppress the three-phase unbalance ΔV ₃ of the system voltage. In FIG. 2, the other parts denoted by the same reference numerals as those in FIG. 1 represent the use of equivalent products.

In the configuration of FIG. 2, the suppression of the instantaneous voltage fluctuation ΔV and the suppression of the three-phase imbalance are feedforward-controlled by detecting the instantaneous reactive power fluctuation ΔQ of the load and the reactive power imbalance ΔQ ₃ which cause the suppression. Therefore, there is no response delay as in the ΔV detection control, and improvement in performance can be expected. To suppress the three-phase imbalance, it is possible to determine the shift amount of the bias voltage only from the system voltage V _L using the DC detector 6 and the average voltage detector 7 shown in FIG.

[0052]

According to the first aspect of the present invention, the standby operation point of each SVC phase is made to follow the three-phase unbalanced voltage, and the voltage fluctuation detector 18 for detecting the ΔV compensation amount of each phase is completely provided. Because of the integrator configuration, the SVC can efficiently perform ΔV compensation within the control operation region even if there is a long-cycle fluctuation of the power receiving power source and a three-phase imbalance. According to this method, a response of 1 cycle or less for each phase ΔV fluctuation and a response of several cycles for 3-phase unbalance compensation can be realized.

The second invention of the present invention directly detects the reactive power of the load which causes the ΔV fluctuation of each phase and the three-phase imbalance,
Since the compensation is performed by the open loop control, there is no response delay of the ΔV control, and the compensation performance can be further improved.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a control device for a voltage fluctuation suppressing device of the first invention, which detects a system voltage and performs ΔV control.

FIG. 2 is a circuit block diagram showing an embodiment of the control device of the voltage fluctuation suppressing device of the second invention, which detects the reactive power of the load and performs Q control.

[Explanation of symbols]

5 SVC control device 6 DC conversion circuit 7 Average voltage detector 8 _U , 8 _V , 8 _W control signal generation circuit 9 Unbalance suppression circuit 10 _U , 10 _V , 10 _W phase control circuit SVC reactive power compensator TCR thyristor control Reactor

Claims (2)

[Claims] 1. A voltage fluctuation suppressing device for suppressing voltage fluctuations of a three-phase power system by compensating reactive power increase / decrease by a thyristor control reactor, wherein the voltage fluctuation ΔV detected for each phase corresponds to the maximum output of the thyristor control reactor. A control signal generation circuit for adding a bias voltage having a standby operation point of about 1/2 to generate a control signal V _C for each phase of the thyristor control reactor, and a voltage V _U , V for each phase detected by converting to DC _V and V _W are compared with the DC-converted three-phase average voltage V _3, and the difference between
An unbalance suppression circuit that shifts the bias voltage of each phase so as to eliminate a three-phase voltage imbalance. 2. A voltage fluctuation suppressing device for suppressing voltage fluctuations of a three-phase power system by increasing and decreasing compensation of reactive power by a thyristor control reactor, wherein a reactive power fluctuation ΔQ of a load detected for each phase corresponds to a thyristor control reactor. A control signal generation circuit that adds a bias voltage with about 1/2 of the maximum output as a standby operation point to create a control signal V _C of each phase of the thyristor control reactor, and a load of each phase detected by converting to DC Reactive power Q _LU , Q _LV ,
The Q _LW, compared to the reactive power Q ₃ of 3-phase average which is direct current,
An unbalance suppression circuit that shifts the bias voltage of each phase so as to eliminate the reactive power imbalance of the three phases by the difference, and a control device of the voltage fluctuation suppressing device.