JPH0615115U - Control system of reactive power compensator - Google Patents

Abstract

(57) [Abstract] [Purpose] An open loop control system was adopted for the control of the thyristor control reactor (TCR) of the reactive power compensator (SVC) for the purpose of flicker countermeasures for highly variable loads such as arc furnaces. If, in the cause of disturbance in the waveform of the system voltage V _S and the load current I _L, when an error is included in the reactive power Q _L of the detected load, caused control error in TCR, and the voltage variation ΔV remains. The present invention aims to correct this control error while ensuring high-speed control, and improve the compensation performance. [Structure] By combining open loop control, which is the main control, with slave control, which detects the total reactive power Q _T of the grid and performs feedback control, the voltage fluctuation ΔV of the grid that remains as the former control error is corrected. .

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a reactive power compensator (hereinafter referred to as SVC) that compensates for load fluctuations so that the reactive power of the entire system bus is constant and suppresses voltage fluctuations.

[0002]

[Prior art]

 The SVC increases or decreases the reactive power generated by a thyristor-controlled reactor (TCR [Thyristor Controled Reactor]) connected to the system bus, and increases or decreases it according to the load fluctuation, and the power from a substation or the like supplies it to the system bus. Make the power constant. As a result, the impedance drop in the power supply side circuit of the system is made constant and the fluctuation of the bus voltage is suppressed.

The fluctuating load targeted for voltage fluctuation suppression is, for example, an arc furnace. The electric current of the arc furnace shows a strong fluctuation every half cycle and randomly. In order to suppress such voltage fluctuation, it is necessary to control the TCR within the cycle in which the current changes. Therefore, the feedback control, which makes the detection delay due to the time constant of the feedback circuit fatal, cannot be adopted.The open loop control that enables high-speed control is adopted, and the reactive power of the detected load is detected every half cycle of the commercial frequency. in Q _L, the reactive power Q _TCR generated in TCR, and are determined and controlled.

Next, a circuit example of the conventional SVC will be described with reference to FIG. In the figure, 1 is a power supply, 2 is impedance of a power supply and a power supply system, 3 is a bus bar to which a load and SVC are connected, and 4 is a fluctuating load which is a source of flicker.

Reference numeral 5 denotes an SVC reactor, and recently, a high impedance transformer having a large leakage impedance of the transformer is often used. Reference numeral 6 is a thyristor device for SVC, and 5 and 6 constitute a TCR. Numeral 7 is a phase-advancing capacitor equipment, which has a filter structure that absorbs harmonics generated by TCR and load. 8 slow circuit CT, 9 is PT, 10 for bus voltage detection delaying 90 ° the voltage of PT for load current detection, Q _L detection circuit for detecting the load of the reactive power of (Q _L) in a high speed 11 Is. 12 shows the pulse generation circuit which determines the ignition pulse phase of the thyristor according to the reactive power signal Q _L to the output of the Q _L detection circuitry 11, which generates a phase control pulse TCR.

[0006] The above arrangement, in the phase control of the TCR to be performed every half cycle of the commercial frequency, determine the reactive power Q _L of the load from the bus voltage V _S and the load current I _L, the reactive power Q _TCR of TCR, intended to reduce only the size of Q _L from a predetermined offset value, the reactive power Q _L + Q _TCR with the power source side, to suppress a voltage variation and a constant reduction.

[0007] The calculation of the reactive power Q _L of the load in the Q _L detection circuit 11, using a multiplier and an active filter has for example shown, it has been made by the following method. The multiplier multiplies the bus voltage V _S ′ delayed by 90 ° in the delay circuit 10 by the instantaneous value of the load current I _L. This output is expressed by the following equation.

[Equation 1]

As shown in FIG. 3, this is a component in which the reactive power (V _S · I _L · sin θ) which is a DC component is overlapped with a component having a double period of the commercial frequency.

Therefore, the double cycle component is removed by an active filter, and the reactive power is output without delay in detection.

[0010]

[Problems to be solved by the device]

 As described above, in the control of the SVC for a load that fluctuates significantly, the fluctuation must be detected at high speed and the TCR must be controlled within the cycle in which the current has changed, so open-loop control is adopted.

[0011] However, this open-loop control, reactive power Q _TCR to be generated in the TCR, since it is directly determined by the calculated value of the reactive power Q _L of the load by harmonic generation and system voltage V _S load current I _L When the calculated Q _L includes an error due to the disturbance of the waveform of, etc., an error occurs in the compensation amount of TCR. Further, there is a drawback that the voltage fluctuation due to the fluctuating load cannot be completely suppressed and the voltage fluctuation ΔV remains on the bus bar 3.

In principle, the remaining voltage fluctuation ΔV cannot be removed by the open loop control in which the control result is not fed back to the control side.

Therefore, an object of the present invention is to provide a control method capable of removing the residual voltage fluctuation ΔV while performing the open loop control capable of high-speed control.

[0014]

[Means for Solving the Problems]

 The control system of the reactive power compensator provided by this device detects the reactive power of the fluctuating load connected to the bus and increases or decreases the reactive power supplied to the bus by the thyristor control reactor so as to cancel it. In a reactive power compensation device that suppresses voltage fluctuations on the system bus,

[0015] Apart from the main control signal detected reactive power Q _L of the load, a synthetic reactive power Q _T of the entire system (the compensation reactive power Q _SVC generated by the reactive power Q _L and reactive power compensator of the load) It is detected and passed through a first-order lag element and extracted as a slave control signal for control error correction, and the phase control of the thyristor control reactor is performed by the added value of the master control signal and slave control signal. It is characterized by

[0016]

[Action]

Reactive power Q _L of the operation-detected variable load as a main control signal is used to phase control Oh Punrupu in TCR, and every half-cycle of the commercial frequency provides fast control corresponding to the load current I _L, abruptly It suppresses voltage fluctuations corresponding to various load fluctuations.

Aside from this, the reactive power of the entire system (combined reactive power Q _T of the reactive power of the load and the SVC) detected separately represents the error amount of this main control. By adding this to the main control signal to control the phase of the TCR, the residual voltage fluctuation can be removed.

However, since this combined reactive power Q _T includes the reactive power Q _TCR generated by the TCR that is the control target, direct feedback of this results in hunting. Therefore, it is added to the main control signal as a slave control signal through a first-order delay element.

As a result, the remaining voltage fluctuation is removed with a predetermined sensitivity and responsiveness determined by the amplification factor of the first-order lag element and the time constant, and the accuracy of voltage fluctuation suppression is improved.

[0020]

【Example】

 This invention will be described with reference to an embodiment shown in FIG. In FIG. 1, the parts designated by the same reference numerals as those in FIG. 2 indicate the equivalent parts, and the added parts will be described below.

Reference numeral 13 is a CT that detects a combined current I of the load 4 and SVC, and 14 is a Q _T detection circuit that detects a reactive power (Q _T ) of the combination of the load 4 and the SVC. is the same as the method for calculating the reactive power Q _L in Q _L detection circuit 11 that.

Reference numeral 15 is an average value detection circuit composed of a first-order lag element, which outputs the average value of the output signal (Q _T ) of the Q _T detection circuit 14 as a slave control signal. The detection speed (responsiveness) and sensitivity (gain) of this average value are determined by T and K of the transfer function K / (1 + ST), and the control state is optimized by these adjustments. 16 is a summing circuit, for adding as a main control signal Q _L detection circuit 11 output signal (Q _L), the output signal of the average value detecting circuit 15 is a slave control signal (Q _T).

Reference numeral 17 denotes a bias circuit, which adds the bias voltage V _B to the adder circuit 16 with a polarity to be subtracted. This is for cutting the phase-advancing component branched to the system bus 3 from the control signal. That is, the residual current flowing in the power supply includes the current of the phase-advancing capacitor connected to the SVC and the load 4, and the reactive power due to this current has a polarity opposite to that of the reactive power of the load 4 and the TCR and a certain reactive It flows as power, appear as the same function as the biased Ding degree Q _T, since it is unnecessary signal for Q _T detected, and cancel the signal corresponding to the phase advancing reactive power.

The pulse generating circuit 12 generates a trigger pulse for the thyristor circuit 6 based on the output signal of the adding circuit 16. Thus the TCR, Q _L signal which is a main control signal which has been conventionally used, is to be controlled by the synthesis signal Q _T signals and bias voltage V _B that is added in this invention.

[0025] In the above structure, the load current I _L is detected by the CT8, reactive power Q _L of the load calculated QL detection circuit 11 from the slow circuit 10 at 90 ° the output voltage V _S of PT9 that delayed 'is , Is supplied to the pulse generation circuit 12 as a main control signal and controls the TCR in an open loop as in the conventional case. The main control route is faster because computation delay of Q _L detection circuit 11 is negligibly small.

When the control is performed only by this main control route, the TCR cannot completely compensate the load current, and the residual voltage ΔV of the bus 3 caused by the residual current of the load current flowing in the power source 1 is the residual voltage of the power source. The average value of the electric power Q _T is canceled by the slave control route which gives the pulse generating circuit 12. That is, the combined current I of the load current I _L and the SVC current I _SVC is detected by the CT 13, and the combined current I and the output voltage V _S ′ of the PT 9 delayed by 90 ° in the phase delay circuit 10 are changed to the Q _T detection circuit 14. The average value of the reactive power Q _T of the load calculated by the average value detection circuit 15 is given to the pulse generation circuit 12, and the residual voltage ΔV of the bus bar 3 is removed with a predetermined response and sensitivity.

Here, the average value detection circuit 15 of the secondary control route for feedback control has a first-order lag element, and the Q _T detection signal which is a feedback signal includes the TCR current I _{TCR which} is a direct control target. Prevents hunting due to the presence of

By controlling the TCR with the above-described configuration, it is possible to reduce the reactive power that remains uncompensated in the past and reduce the control accuracy.

[0029]

[Effect of device]

 According to this invention, the error that occurs in the open loop control that is adopted as the main control to secure the response speed can be corrected by the feedback control that is the sub control, and the compensation performance, that is, the voltage fluctuation suppressing effect can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a control circuit for explaining an embodiment of the present invention.

FIG. 2 is a diagram showing a control circuit for explaining a conventional control method.

FIG. 3 is a waveform diagram illustrating the principle of reactive power calculation.

[Explanation of symbols]

1 power supply 2 power supply side Inpi - Dance 3 busbar 4 variable load 5 SVC reactor 6 SVC thyristor device 10 slow circuit 11 Q _L detection circuit 12 pulse generator 14 Q _T detector 15 the average value detecting circuit (primary delay element ) 16 adder circuit Q _L main control signal and becomes load reactive power Q _T従制reactive power of the entire system at the control signal

Claims (1)

[Scope of utility model registration request] 1. A reactive power Q of a fluctuating load connected to a bus bar.
Detecting _L, and the a size corresponding thereto, by increasing or decreasing the reactive power Q _TCR thyristor controlled reactor is supplied to the bus, the reactive power compensator for suppressing a voltage fluctuation of the system bus, invalid load power Q _L In addition to the main control signal that detected, the combined reactive power Q _T of the entire system was detected, and the one that passed through the primary delay element was taken out as a slave control signal for correcting the control error. A control system for a reactive power compensator, characterized in that the phase of the thyristor control reactor is controlled by the added value of signals.