JPS63211678A - Manufacture of insulated-gate field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent the generation of a parasitic capacity which is caused by the parts of the source and drain which creep under the thin gate insulating film by forming a channel forming region in self alignment with the section in which a gate is to be formed, or the section on which the thin part of the insulating layer is deposited. CONSTITUTION:On a preformed low impurity concentration region 12, an insulating layer 13 is formed which has a thin part 13A in a part in which a channel is to be finally formed, or a position in which a gate section is to be formed, and the remaining of which is made to be 13B, and with this as a mask an impurity doping is performed. Accordingly, a region in which the channel is to be formed is formed in alignment with the position where the thin part 13A is to be formed, or the position where a gate insulating film 16 is to be formed, and the respective opposed edges 17S, 17d of a source region 18S and a drain region 18d are constructed by the low impurity concentration region 12. With this, these regions are prevented from being opposed through the thin gate insulating film 16 to a gate electrode 15, so that the generation of a parasitic capacity is drastically reduced between the source and drain add the gate.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to insulated gate field effect transistors (MIS-F) in single semiconductor devices or semiconductor integrated circuits.
Related to the manufacturing method of ET).

[Summary of the invention]

The present invention forms a low impurity concentration region of the first conductivity type on the surface of a semiconductor substrate, forms an insulating layer having a thin part and a thick part on the top of the region, and uses this insulating layer as a mask to form a low impurity concentration region. By doping impurities through the thin portion to cancel the conductivity type of the first conductivity type low impurity concentration region and changing it to the second conductivity type, a channel formation region of the second conductivity type is formed by self-alignment, and the insulating layer The parasitic capacitance between the gate and the source and between the gate and the drain is eliminated by using the thin part of the gate as a gate insulating film or by eliminating this thin part and forming a gate electrode on the newly formed gate insulating film, Furthermore, it is possible to avoid the generation of an electric field concentration area at the edge of the drain side, that is, a hot carrier generation source directly under the gate insulating film, and to avoid instability of characteristics due to hot carriers entering the gate insulating film.

[Conventional technology]

Mi in single semiconductor devices or semiconductor integrated circuits, etc.
As a method of obtaining an s-FET, for example, as shown in FIG. A gate electrode (3) is formed, and using this as a mask, the substrate (1) is doped with an impurity, such as by implanting impurity ions, and annealing is performed to activate the impurity, thereby forming the source and drain regions (4) and ( 5)
A method is used in which the gate electrode is formed by self-aligning with the gate portion. In this case, the source and drain regions (4) and (5)
) and the gate part, that is, the arrangement part of the gate electrode (3), are self-aligned (self-aligned) as described above, but the diffusion of impurities in the double-headed regions (4) and (5) is caused by the diffusion of impurities under the gate electrode (3). By entering the source and drain regions (4) and (5) with widths Ls and Ld, respectively, through the thin gate insulating film (2), the gate electrode (
3), there is a problem in that parasitic capacitances, that is, capacitance between the gate and the source and capacitance between the gate and the drain are generated.

In addition, if the channel of the old 5-FET is made particularly short in the channel forming region (6) between the source and drain regions (4) and (5) under the gate electrode (3), the drain region ( 5) The strong electric field strength area at the edge becomes a hot carrier generation source, which causes SiO□
There is a problem that the gate insulating film is troubled, leading to instability in FET operation.

[Problem that the invention seeks to solve]

The present invention eliminates the above-mentioned problems, such as the generation of parasitic capacitance due to the overlapping of the source and drain regions via the gate electrode and thin insulating film, and the instability of characteristics due to the influence of hot carriers. This is what we are trying to solve.

[Means for solving problems]

In the present invention, a method is adopted in which the channel forming region is self-aligned with the gate portion.

That is, in the present invention, as shown in FIG. The insulating layer ( 13), and as shown in FIG. 1B, the thin part (13^) is
) to convert a part of the low impurity concentration region (12) into a channel forming region (14) of the second conductivity type. and insulation N
(13) The upper thin part (13^) itself is covered with the gate insulating film (1
6) or, for example, the image part (13A) and (1
The thin part (13A) is once removed by etching the entire surface using the difference in thickness of 3B), and a gate insulating film (16) is formed thereon again by thermal oxidation, etc., and becomes a gate electrode on this. For example, metal gate electrode (15)
be coated with.

[For production]

MIS-F[!] obtained by the above-described production method of the present invention. According to T, there is a thin part (13A) at the part where the channel will finally be formed, that is, the gate part, on the pre-formed low impurity concentration region (12), and the other part is the thick part (13B).
An insulating layer (13) is formed, and impurity doping is performed using this as a mask.
Since the channel formation region (14) is formed in alignment with the formation position of the gate insulating film (16), each opposing edge of the source region and the drain region is formed by the low impurity concentration region (12). Since these regions are prevented from facing the gate electrode (15) through the thin gate insulating film (16), the generation of parasitic capacitance between the source and drain and the gate is avoided. drastically decrease.

Further, each opposing edge of the source and drain is formed by both side edges of the low impurity concentration region (12) where the channel forming region (I4) is not formed, and the side surfaces of these opposing edges are formed by the channel forming region (I4). It is inclined due to the sloped shape of the side surface of the region (14), and in particular, for example, the stepped side surface of the insulation 1 (13), which serves as a mask for ion implantation, that is, the side surface of the thick portion (13B) is placed on the substrate (11) side. If the slope is sufficiently tilted by forming an inclined surface that spreads toward It can be in a deep position. This makes it possible to generate an electric field concentration area inside the semiconductor substrate (11) at this tip edge, especially at the drain side tip edge (17d), and the source of hot carriers is shifted from the gate insulating film (16). As a result, instability of characteristics caused by hot carriers being trapped in the gate insulating film (16) can be avoided.

〔Example〕

As shown in the first recess, a silicon semiconductor substrate (II) requiring n-type or p-type is provided, and a low impurity impurity of a conductivity type different from that of this substrate (11), for example, p-type or n-type, is provided facing the main surface thereof. A doped region (12) is formed, and on both sides thereof, a highly doped source region (18s) and a heavily doped drain region (18d) for a source and a drain are formed by selective diffusion or the like. And each of these areas (12
), (18s), and (18d) are formed thereon, a 5iOz oxide film "4tA edge layer (13) having a required thickness is formed entirely by thermal oxidation or the like. Then, a predetermined portion of the low impurity concentration region (12), that is, a double-headed region (
18s) and (18d) are removed by selective etching with a required width at a position separated by a required distance, and the etched portion is again etched to a required thin thickness, such as a thickness that can form a gate insulating film. Thin part of SiO□ (1
3A) is formed.

Next, as shown in FIG. 1B, using the insulator (13) as a mask, the p-type or n-type
A channel forming region (14
), a high concentration source region (18s), and a low impurity concentration region (
A channel forming region (14) having the opposite conductivity type is selectively formed by canceling the conductivity type (12).

As shown in FIG. 1C, the thin part (13A) is used as a gate insulating film (16), and a metal gate electrode (15) is formed thereon, and the thick part (13B) of the insulating film (13) is
Electrode windows were opened in each region to form high-concentration source regions (18
3) A source electrode (19s) and a drain electrode (19d) are ohmically deposited on the high concentration drain region (18d) as required. The gate electrode (15) can be formed exclusively on the thin part (13A) of the insulating layer (13), or can be formed over the thick part (13B).

In the above example, 1, the thin part (13A) of the insulation N (13)
) is used as a gate insulating film (16), the thin part (13A) is removed by etching the entire surface using the difference in thickness with the thick part (13B), and a new gate insulator is added here. A membrane (16) can also be formed. Further, each part (13^) and (13B) of the insulating layer (13) is
The etching is not limited to being made of the same material, such as, but may be made of materials that use different etching liquids, or the thinner part (13A) is made of a material that has a faster etching speed than the thicker part (13B). By doing so, selective removal of the thin portion (13A) can be performed more reliably and with high precision.

〔Effect of the invention〕

As described above, according to the manufacturing method of the present invention, the channel forming region (14) is formed in self-alignment with the gate forming part, that is, the adhered part of the thin part (13A) of the insulating layer (13). It is possible to avoid the generation of parasitic capacitance caused by the portions of the source and drain regions that penetrate under the thin gate insulating film, and as described above, the source of hot carriers can be moved inside from the surface of the gate insulating film of the semiconductor substrate (11). By being able to bring hot carriers to the position where they have entered, it is possible to avoid instability of characteristics caused by trapping of hot carriers in the gate insulating film. The problem of generation can be avoided, and the practical benefits are great.

[Brief explanation of the drawing]

FIG. 1 is an enlarged linear sectional view of each step of an example of the manufacturing method of the present invention, and FIG. 2 is an enlarged linear sectional view of the main part of an insulated gate field effect transistor manufactured by a conventional manufacturing method. (11) is a semiconductor substrate, (12) is a low impurity concentration region,
(13) is an insulating layer, (13A) is a thin part, (13B) is a thick part, (16) is a gate insulating film, and (15) is a gate electrode.

Claims (1)

[Claims] A step of forming a low impurity concentration region of a first conductivity type on a semiconductor surface; a step of doping a second conductivity type impurity through the thin portion of the insulating layer as a mask to transform a part of the low impurity concentration region into a second conductivity type channel forming region; A method for manufacturing an insulated gate field effect transistor, comprising the step of forming a gate electrode on the thin portion on the insulating layer.