JPS6320917A - Phase comparator - Google Patents

Abstract

PURPOSE:To contrive to decrease the locking time and to exclude the side band synchronization by adding the frequency detection using a monostable multivibrator for phase comparison as an accessory device. CONSTITUTION:Suppose that a comparison signal having a frequency lower than the frequency set in a prescribed range based on a reference signal is inputted to each of monostable multivibrators 20, 21 (MM1, MM2), the MM 1 and MM 2 both generate a pulse as shown in figure (a). When the frequency enters the prescribed range, although the pulse remains at the output of the MM 1 as shown in figure (b), the output of the MM 2 goes to a high level because the leading of the next signal comes while the pulse exists. If a signal with a higher frequency than the prescribed range comes, both the MMs go to a high level as shown in figure (c). The states above are inputted to latches 22, 23 using a clock as a comparison signal to obtain 3 kinds of signals to be outputted, and the signals are given to a logic circuit 24, from which a frequency deciding signal and a deciding signal representing out of range of frequency are formed and fed to a switch section.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a phase comparator.

2. Description of the Related Art A block diagram of a phase comparator in a conventional PLL is shown in FIG. 60 is a phase comparator, 61 is a low pass filter (LPF), and 62 is a voltage controlled oscillator (VCO).
It is. In the phase comparator in the PLL configured as described above, when the reference signal, comparison signal, and comparison signal are input to the phase comparator 60, the phase difference between the two signals is calculated as a voltage value or a digital value (L ), below is called the error value), and it is output as the LPF51 A, V
Voltage-frequency conversion was performed by CO52, and its output was returned as a comparison signal to form a loop.

Problems to be Solved by the Invention However, with the above configuration, it takes some time for the loop to synchronize, especially in low frequency phase comparisons, and synchronization may be delayed in sidebands, that is, harmonics. Therefore, an object of the present invention is to provide a phase comparator with a simple configuration that can shorten the pull-in time in a PLL and eliminate sideband synchronization.

Means for Solving the Problems The present invention provides a phase comparator that compares the phases of a reference signal and a comparison signal, and a phase comparator that inputs only the comparison signal and determines whether its frequency is within a certain range from the value of the reference signal or not. A frequency detection section that generates a control signal indicating whether it is low or high, a fixed error value generation section that generates a preset error value, and an error value output from the phase comparison section based on the control signal output from the frequency detection section. The phase comparator is characterized in that it includes a switching section that switches between the error value and the error value output from the fixed error value generation section.

Operation The present invention provides a PLL using the phase comparator having the above-mentioned configuration.
In this case, only when the comparison signal falls within a certain range from the value of the reference signal, the phase-compared error value is output, and a loop is formed using conventional phase comparison.

Otherwise, if it is lower or higher than a certain range, it outputs the error value set by the fixed error value generator, draws the comparison signal to a certain range, and then forms a loop that performs conventional phase comparison. Then, from this phase comparator, PLL
This speeds up the loop pull-in time and eliminates sideband synchronization.

Example Hereinafter, the present invention will be explained in more detail based on the drawings.

FIG. 1 shows an overall diagram of an embodiment of the present invention. In FIG. 1, 1o is a phase comparison unit that compares the phases of the reference signal and comparison signal, and 11 is a control signal that inputs only the comparison signal and determines whether the frequency is within a certain range or lower than the value of the reference signal. 12 is a fixed error value generation section that generates a preset error value; 13 is a control signal output from the frequency detection section 11; an error value output from the phase comparator 10; and a fixed error. This is a switching unit that performs switching between the error value and the error value output from the value generation unit 12.

The operation of the phase comparator of this embodiment configured as described above will be explained below. When the reference signal and comparison signal are input to the phase comparison section 10, a phase comparison is performed and an error value is output. If not, a control signal indicating whether it is low or high is output, and if it is, the error value of the phase comparator 10 becomes the output of the phase comparator. However, if it is not within the range, a signal indicating whether it is low or high is output, and the corresponding error value is output from the fixed error value generator 12 and used as the output of the phase comparator. As described above, according to this embodiment, if the frequency detection section 11 is viewed as an additional device of the phase comparison section 10,
A simple configuration can be achieved without changing the shape of the conventional phase comparator.

FIG. 2 shows the frequency detection section 11 in the phase comparator of the present invention.
The block diagram is shown below. Further, FIG. 3 is an operational waveform diagram of the frequency detection section 11. In Fig. 2, 20.21 is a monostable multivibrator that maintains a high or low level for a certain period determined by the respective time constants depending on the rising or falling EIK of the comparison signal, and 22.23 is a monostable multivibrator 20.21. Latch 24 latches the generated output according to the comparison signal.
2. From the combination of output signal states in 23, is the frequency of the comparison signal within a certain range than the frequency of the reference signal?
This is a logic circuit that forms a frequency determination signal to determine whether the frequency is present or not, and a determination signal outside the frequency range to determine whether it is low or high if it is outside the range. The operation of the frequency detection section 11 configured as described above will be explained below with reference to FIG. 3. First of all, monostable multivibrator 20
．． 21 (hereinafter abbreviated as MM1 and MM2), if a comparison signal with a frequency lower than the reference signal within a certain range is input, MM1 and MM2 will be as shown in the waveform diagram of Fig. 3 (al). Both generate pulses. Next, when the frequency falls within the range, M
A pulse remains in M1, but MM2 becomes high level because the next signal rises while the pulse is being output.

Finally, when a frequency higher than the range enters, both MMl and MM2 become high level as shown in FIG. 3(0).

A latch 22 which uses a clock as a comparison signal for these states.
By inputting to 23, as shown in Figure 3, when a pulse is output, it is latched to low level, and when it is high level, it is latched to high level, and three types of signals can be output in each case. , by passing the signal through the logic circuit 24, a frequency determination signal and a determination signal outside the frequency range are formed and sent to the switching section 13. According to the embodiments described above, it is possible to create a kind of frequency pull-in part in the conventional phase comparator, and when a PLL loop is configured, the pull-in time can be shortened and sideband synchronization can be eliminated. . Finally, FIG. 4 is a block diagram of a PLL configured using the phase comparator of the present invention. 40 is the phase comparator of the present invention, 41 is an LPF, and 42 is a vCO. The phase comparator configured above and shown in the block diagram below treats the frequency pull-in part as an additional device, so it is a phase comparator in a broad sense, so it is no different from a PLL using a conventional phase comparator. Become.

In the present invention, an unchanging signal is input as the reference signal, but MMl of the frequency detection section 11.

By changing the range of the time constant that determines the pulse width of MM2, a similar phase comparison can be performed for any signal without increasing the number of components.

As described in detail, the present invention provides a PL using the same.
In L, a simple configuration that adds frequency detection using a monostable multivibrator to phase comparison as an additional device can make the pull-in time faster than PLL using a conventional phase comparator, and also eliminates sideband synchronization. The practical effect is great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a phase comparator according to an embodiment of the present invention, FIG. 2 is a block diagram of a frequency detection section in the same phase comparator, FIG. 3 is an operation waveform diagram of the frequency detection section, and FIG.
The figure is a block diagram of a PLL configured using the phase comparator of the present invention, and FIG. 6 is a block diagram of a PLL configured using a conventional phase comparator. 10... Phase comparison section, 11... Frequency detection section, 12... Fixed error value generation section, 13...
...Switching unit, 20.21...Monostable multi, Kuitsutatsuta, 22゜23...Latch, 24°゛°...Logic circuit, 40°°° °°゛Phase comparator, 41...LPF, 42...VC
Name of D0 agent: Patent attorney Toshio Nakao and one other person Figure 1, 2 LtJaJllX** Figure 4 Figure 5

Claims (2)

[Claims] (1) A phase comparison unit that compares the phases of the reference signal and comparison signal, and a frequency that inputs only the comparison signal and generates a control signal that indicates whether the frequency is within a certain range from the value of the reference signal, or is lower or higher than that. a detection section, a fixed error value generation section that generates a preset error value, and an error value output from the phase comparison section according to a control signal output from the frequency detection section and an output from the fixed error value generation section. 1. A phase comparator, comprising: a switching unit that switches between an error value and an error value. (2) Two monostable multivibrators that hold a high or low level for a certain period determined by a time constant from the rise or fall of a comparison signal, and each output of the monostable multivibrator is latched by the comparison signal. A control signal is output that indicates whether the frequency of the comparison signal is within a certain range or not from the frequency of the reference signal based on the combination of the output signal states of the two latch sections, and if it is outside the range. , and a logic circuit that outputs a control signal indicating whether the frequency is lower or higher than within the range.