JPS63209172A - Insulated-gate self-turn-off thyristor - Google Patents

Abstract

PURPOSE:To shorten the turn-on time by augmenting the trigger sensitivity while sustaining the high turn-off capacity by a method wherein a MIS-GTO region and a conductive modulation type MOSFET region are formed adjacently to be parallel-actuated. CONSTITUTION:Gate electrodes 8, 15 are impressed with positive voltage to turn on a conductive modulation type MOSFET. Thus, electrons are injected from n<+>-type source layer 13 in a conductive modulation type MOSFET region (a) into an n-type base layer 2 so that holes corresponding to the injected electrons may be injected from a p-type emitter layer 1 to turn off said MOSFET (a). On the other hand, within an insulated-gate type self on-off thyristor (MIS-GTO) region (b), a base current in proportion to the rising factor of gate voltage runs to a p-type base layer 3 to inject electrons from n-type emitter layer 4 while these electrons passing through a depletion layer reach the n<+>-type base layer 2 accelerating the injection of holes from the p-type emitter layer 1 to turn off the MIS-GTO. Through these procedures, the time to increase the carrier concentration in the n-type base layer 2 can be cut down to shorten the turn-on time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the invention] (Industrial application field) The present invention relates to an insulated gate self-turn-off thyristor that performs on/off control using an insulated gate.

(Prior art) A gate turn-off Nyristor (hereinafter referred to as GTO) usually applies a negative bias QO to the gate 4 poles and supplies part of the anode 4 flow to the gate ¥! By discharging to the outside as L flow,
Configured to self-turn off. However, since the current is 1ilIJ@fll, a large gate power is required. On the other hand, gate
An MI8 transistor is provided to short-circuit the cathodes, and this MI8 transistor discharges the gate tta to the outside.q GTO (11, MII-GTO) is 1
Since the 111 product has a 11E pressure and a 11JMM, it can self-turn off with a small gate force. This M
Some I5-GTOs have an n-channel type MI8 transistor and some have a p-type channel type MI8 transistor. The n-channel WMIS-GTO is designated by Special Publication No. 59-47469,
The p-channel type MIS-GTO is disclosed in Japanese Patent Publication No. 60-9668 and has a known structure.

FIG. 6 is a cross-sectional view of a p-channel type MIS-GTO element. In the figure, l is the p-type first emitter 1
-12 is n bandit @1 bass singing, 3 is p type 2nd bass 1
．． 4 is an n-type Ka2 emitter layer. 1st emitter 41
The anode 'tit pole 10 is connected to the second emitter +d 4
Vc has cathode electrodes 11 ohmically attached to each other. A low concentration n-type transistor 5 is formed so as to be electrically connected to the second emitter I1I4.

A Vcp+ffi channel 6 is provided inside the Vcp+ffi channel 6, and the six-sided portion of the n-type well 1i15 sandwiched between this p alarm 6 and the second base plate 3 is used as a channel region.
An IS gate electrode 8 is formed to constitute a p-channel type MIS transistor for turn-off. 9 is an insulating film.

This element's turn-off II! jJ production is performed as follows. When a negative voltage is applied 7JO to the MIS gate electrode 8 of the turn-off p-channel MIS transistor, @2
The base layer 3 is connected via the channel region under the MI8 gate CLW18 to p+凰rF! Shorted to J6 and further p+ type @6
It is short-circuited with the cathode t M 11 which is in ohmic FeQ. This turns off the MIS-GTO.

On the other hand, the turn-on operation of this element is performed as follows. Applying positive voltage to MI8 gate electrode 8fb and 1Ml
8G) 1cW & 8 etc. 2 H-*r@3 are capacitively coupled via the insulating film 7, so the base current proportional to the rise rate of the positive voltage applied to the MI8 gate polarization 8 is @2 The current flows to the base 113, prompting injection of electrons from the second emitter tm<, and turning on the 1M1s-GTO.

However, this method of turning on at the displacement '11CfL due to the rise of the gate voltage 1 has the problem that a large base current cannot be obtained and the turn-on time becomes long. conventionally.

In order to avoid this problem, the total amount of impurities in @2 base Ii3 is reduced and the first base 112. 2nd base 13, 2nd
A method has been taken in which the current amplification factor of the NPN transistor consisting of the emitter layer 4 is increased to a large extent. However, if this method is adopted, the second base +1
It is a common problem that the peak turn-off current decreases as the resistance of 3 increases.

(Problem that Yangming is trying to solve) As mentioned above, the conventional MI 5-GTO is turned on only by the displacement current caused by the rise of the gate voltage, so a sufficient base current cannot be obtained and the turn-on time is long. There was a period of time.

The purpose of this proportion is to develop a Mid-GTt (Nagahama model) that solves these problems.

[Takumei's configuration] (Means for solving the problem) The MI8-GTO of the present invention includes a @1 conductivity type emitter layer, a second conductivity type base layer, a first conductivity type base layer, and a second conductivity type emitter layer. 1
The Nyristor structure that fits from the 1Lm emitter layer and @1'
The 16fJL type emitter layer and the second conductivity type base layer are adjacent to the MIS-GTO area that connects the first conductivity type base 1 and the second conductivity type emitter layer to the element. The first conductor'lt of the area is the same as the area.
The base layer is essentially separated from the friend first guide storm type base-
1 and the insulated gate 41 element of the 2nd conductivity type base layer and the 2nd conductivity type base layer short-circuited with the @1 conductivity type base layer and the 2nd conductivity type base layer and the 2nd conductivity type base layer. The first conductor 1 of the region in which the top region of the modulated MO8FET is formed has a modulation type MO8FET! The first main electrode is on the mold emitter layer.

The second conductivity is applied to the type emitter layer and the second conductivity type source layer.
A common main electrode is provided.

(l'F, for) In the present element structure, the MIS-GTO region and the
Since the rL modulation type MO8F'ET region is configured in parallel, when the gate voltage is applied, not only the base 'wall current due to the nightstand'4 flow flows through the first conductor to the type base layer, but also the base' Since the base 1 current is supplied to the second curtain type base layer from around the modulation over M08FgT, the turn-on time becomes shorter.

(Actual power sequence) Hereinafter, one actual power sequence of the present invention will be explained with reference to the drawings. In all the following power columns, the p seat is used as the @1 conductor't& type, and the n member is used as the second conductor.

FIG. 1 is a sectional view of the element structure of the real column of the @ layer. First, the structure of the Mis-GTO region will be explained.

An n-type base 12 is formed in contact with the p-type emitter 1,
The iCp base 3 and the nψ emitters 1 to 4 are successively diffused into the n base 12 to form a pn pn structure. An anode electrode (the king of the third layer) 10 is formed on the p-type emitter 1, and the n-type emitter iJ
In 41c, the cathode electrode (second main electrode) 11 is covered with cedar. A low-concentration NG well ii5, which is similar to the nfJJ emitter lii 4, has a p+ well 6 in it, which has been reshaped around 1 and is a region sandwiched between the p+ type [-6 and the p-type base layer 3. A p-channel dMO8FgT for turn-off is constructed by using six surfaces of the n-type well 115 as a channel region, and forming an edate electrode 8 thereon via a gate insulating film 7. Reference numeral 9 denotes an insulating film that insulates the gate electrode 8 and the cathode' polarization layer. Then modulate the conductor fiM08FgTJ
Explain the structure of the area.

The n-type emitter layer 1 and the ng base 12 are formed in common with the MIS-GTO area.
A type base layer 12 and an n-type source @13 are sequentially diffused and formed, and a gate is formed on the thorny surface of the p-type base @12 in the region sandwiched between the n-type source @13 and the n-type base @2 as a channel region. A conductivity modulation type M08FgT is constructed by forming a gate electrode 15 with an insulating film 7 interposed therebetween. p type 1m14 is p base li low under n ten crab source 113,
This is provided to lower resistance and prevent latch-up.

The p-type base layer 116 is provided to diffuse p-type at the same time as the base layer 12 and to determine the gap between the p-type base layers in one region by 41C. As described above, the nine MI8-GTU robust regions and conductive modulation type MO8FF, T regions are provided adjacently, and the n-type emitter 1i is connected so that their tops are connected in parallel.
Both the lf and n acid sources 1113 are ohmically connected to the cand to the pole 11. In this example, the gate electrode 8 and the gate electrode 15 are integrally formed.

The details of this element are as follows. The turn-on operation is
This is done by applying a positive voltage to the gate '4CIi8.15. As a result, the conductivity modulation type MO8-FgT
Electrons are injected from the n ten base source I@13 in the region into the n base layer 2, and corresponding holes are injected from the n-type emitter layer 1, turning off the conductivity modulation type MO8FET.

On the other hand, in the MIS-GTO region, the t-base ta flows into the p-type base l113 in proportion to the rise rate of the gate pressure, electrons are injected from the n-type emitter layer 4, and these electrons pass through the depletion layer and pass through the n-type emitter layer 4. The holes reach the type base li2, prompting injection of holes from the n-type emitter layer 1, and turning off the MIS-GTO. - Displacement due to rise of gate 1 pressure! Since the flow is small, it is
The turn-on time is longer for i[fi-G 'I' O. The operation that actually occurs in the follower is that the conductor modulation implanted M08FET is first turned on, and the concentration in the n-type base transistor 2 increases, and as a result of this, the MI3-GTO is turned on by the gate displacement current. the result.

The turn-on time is shortened because time is saved to increase the gearia concentration in the n-type base II Z of the MIS-GTO region. In addition, the turn-off operation is performed by the gate electrode 8,
This is done by applying a negative voltage to 15. As a result, the p1 base 113 of MIS-GTO and the n-type emitter r
The p-channel (MID) transistor that shorts f714 becomes conductive, and the MIS-GTO is turned off. Further, since the conductivity modulation WMO8FgT is an n-channel type, the channel becomes non-conductive and turns off. According to the structure of the present invention, M
P-type pace @ to increase the trigger sensitivity of IS-GTO
1Ml5-GT since there is no need to reduce the total amount of impurities in 3.
The problem that the peak turn-off current of O becomes small does not occur.

FIG. 2 is a sectional view of the element structure of the 20th implementation row. In this implementation column, n1! of the MIS-GTO area! I! Base layer 2
Conductive modulation of minority carrier lifetime in WMO8
The cage is set to be larger than that of the FET area. As a result, the latch-up current of the JWMO8FET can be made larger than the peak turn-off current a of the MIS-GTO, so that the self-turn-off ability of the MIS-G'rO can be maximized. Maku, conductivity modulation type MO8Fg
Since T turns off faster, is it better to use guide at turn off?
[The hair flow in the area around MO8-FgT is concentrated'
! tR, the density increases and no longer exceeds the rough rise.

FIG. 3 is a cross-sectional view of the practical element structure of @3. In this embodiment, one emitter layer is removed from the p part of the conductivity modulation type MO8FET region to create an anode short structure. As a result, the same effect as in the second implementation column can be obtained for q''C.

However, in the structure of this embodiment, the conductor 4f tone Fil M (J
When SFET turns off.

Since hole injection occurs from the p-type emitter 11 on the M I 8-GTO region side, the ng of the MiS-GTOd region
The carrier filI in the bases 1 and 2 can be raised quickly, and the turn-on time of 1Ml8-GTO can be shortened. Since this case has a short anode structure, it is necessary to set the minority Φ carrier lifetime to a large value. In addition to this T'L, it is also possible to use a method in which the [4Ml5-GTO region also has an anode short structure.

FIG. 4 is a sectional view of the element structure of the fourth embodiment. In this embodiment, the gate electrode 8 in the MIS-GTOL region and the gate electrode 15 in the 14-type MO8FET region are separated and can be controlled independently. A sequence of control methods is shown in Figure 5. In Figure 2, GI is MIS
- G is applying the voltage applied to the gate 8 of the GTO, and G is applying the voltage applied to the gate 1tffi15 of the conduction modulation type MO8FE'r. First, when G and VC positive voltages are applied, the conduction modulation type MO8FgT turns on, and the anode 1 voltage drops to just below the voltage drop of the conduction modulation type M (JSFET), and the anode 11t current begins to flow.Next, the negative bias When applying a positive voltage to 901, M
IS-GTO turns on. At this time, it was already turned on! liM (JSFET increases the gear density in the n-type base layer, so MId
- GTO turn-on occurs quickly. Moreover, when turning off, the voltage of G is first made zero to turn off the conduction modulation type MO8FET. At this time.

Since the current concentrates in the MIS-GTO region, the voltage drop increases and the anode voltage becomes slightly higher. Thereafter, a negative bias is applied to G to turn off the MIS-GTO. According to this implementation, before turning on the MIS-GTO, the conduction f! -/lIMO8FET can sufficiently increase the middle layer density in the n-type base@2, so that a 1Ml5-GTO with high trigger sensitivity can be obtained. In addition, after a positive voltage is applied to G at turn-on, a flow of ', will be concentrated in the conductivity modulation type MO8-FgT region between the time when a positive voltage is applied to G and However, at this time, there is no problem even if the latch-up current is exceeded. G
, is set to zero? Then, the anode current is shunted to the MIS-GTO switch and at 9 o'clock the conduction modulation type M (J8FET region's current density decreases and becomes below the latch-up current. Type MO8FE
Since T is turned off, this type of problem does not occur.

The present invention is not limited to the above-described actual series, but can be implemented with various modifications.

[Effect of activity]

As described above, according to the present invention, by forming the MIS-GTO region and the conductive modulation region adjacent to the M08FET region and operating them in parallel, it is possible to increase the trigger sensitivity and shorten the turn-on time while maintaining high turn-off capability. M.I.S.
- GTO can be realized.

[Brief explanation of the drawing]

Figures 1 to 4 are @works to 41 of the present invention...
n-type emitter layer, 2...n-type base layer, 3...p-pear base layer, 4...n-type emitter layer, 5...nfi well layer, 6...p+-type layer, 7. ...Gate insulating film, 8
...Gate 4 poles, 9...Insulating film, 10...Anode electrode. 11... Cathode polarization, 12... pW base layer, 1
3...n+ type north 1, 14...p ten type layer, 15.
...Gate station! 6 like [, 16 ・-' p
Be V layer. Figure 5, A Figure 6

Claims (4)

[Claims] (1) having a second conductivity type base layer in contact with the first conductivity type emitter layer, the first conductivity type base layer and the second conductivity type emitter layer being diffused and formed on the surface of the second conductivity type base layer;
The thyristor structure has a thyristor structure in which a first conductivity type emitter layer is formed with a first main electrode, a second conductivity type emitter layer is formed with a second main electrode, and a first conductivity type base layer is formed on a surface of the first conductivity type base layer. an insulated gate self-turn-off thyristor region in which an insulated gate turn-off element is formed; a second conductivity type base layer in contact with the first conductivity type emitter layer;
A first conductivity type base layer and a second conductivity type source layer, which are substantially separated from the first conductivity type base layer in the region, are diffused and formed on the surface of the conductivity type base layer, and the first conductivity type emitter layer is formed by diffusion. A first main electrode formed in common with the area is a second main electrode.
A second main electrode formed in common with the region is formed on the conductive type source layer and the first conductive type base layer, respectively, and an insulating material short-circuiting the second conductive type base layer and the second conductive type source layer. Conductivity modulation type MOSFE with gate type element formed
An insulated gate self-turn-off thyristor characterized in that a T region is formed adjacent to the T region. (2) The insulated gate self-turn-off thyristor region according to claim 1, wherein the minority carrier lifetime in the first base layer is larger than that of the conductivity modulation MOSFET region. turn-off thyristor. (3) A portion of the first conductivity type emitter layer of the conductivity modulation type MOSFET region is removed, and the second conductivity type base layer is brought into contact with the first main electrode. Insulated gate self-turn-off thyristor as described in . (4) The gate electrode of the turn-off insulated gate element formed in the insulated gate self-turnoff thyristor region is separated from the insulated gate gate electrode formed in the conductivity modulation dust MOSFET region. An insulated gate self-turn-off thyristor according to claim 1.