JPH06204463A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide semiconductor devices such as an electrostatic induction thyristor, which dose not necessitate a large external driving circuit and has a mechanism which surely performs turning off operation by small drawing current, and other normal thyristors. CONSTITUTION:An N<+> type gate short region 18 is provided on the surface layer of a semiconductor substrate 11 which is positioned on a part whereupon a P<+> type gate region 16 faces a P channel region 15, a first gate electrode 22 is provided over the top plane of the N<+> type gate short region 18 and the top plane of the P<+> type gate region 16 and a second gate electrode 19 is provided on the top of the P type channel region 15 which positions between the N<+> gate short region 18 and an N<+> type cathode region 17 through a gate oxide film 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as an electrostatic induction thyristor used as a power device and other ordinary thyristors.

[0002]

2. Description of the Related Art Generally, among various semiconductor devices used as a power device, an electrostatic induction thyristor has a sensitivity at turn-on operation (hereinafter referred to as turn-on sensitivity) more than other semiconductor devices of the same kind. Known as a good element. The structure and operating principle of the static induction thyristor will be described below.

FIG. 3 is a diagram for explaining the configuration and operation of a conventional static induction thyristor, respectively. Of these, FIG. 1A is a vertical cross-sectional view showing the internal structure of a conventional electrostatic induction thyristor, and FIG. 1B is a diagram showing the anode current with respect to the gate current during operation of the conventional electrostatic induction thyristor. It is a figure which shows a response.

First, as shown in FIG. 1A, in a conventional static induction thyristor, as a semiconductor region which constitutes the entire semiconductor substrate 1, a P-type impurity is contained in a high concentration below the semiconductor region. Is provided with a P ⁺ type anode region 2 on which a silicon wafer is formed. Further, by epitaxially growing the upper surface portion of the P ⁺ type anode region 2, N type impurities are made to have a low concentration thereabove. An N ⁻ -type base region 3 containing is provided. Further, on the upper surface portion of the semiconductor substrate 1 composed of these two layers of semiconductor regions,
A silicon oxide film (Si
A field oxide film 4 obtained by selectively etching O ₂ ) is provided. Hereinafter, for example, by a diffusion method or an opening obtained in the process of etching the silicon oxide film to be the field oxide film 4. By introducing a P-type impurity or an N-type impurity using a technique such as an ion implantation method, various semiconductor regions are provided from the upper layer portion to the surface layer portion of the semiconductor substrate 1.

That is, in the upper layer portion of the N ⁻ type base region 3 corresponding to the upper layer portion of the semiconductor substrate 1, a P ⁻ type channel region 5 containing a low concentration of P type impurities is provided at a predetermined depth. Further, in the upper layer portion of the N ⁻ type base region 3 corresponding to the upper layer portion of the semiconductor substrate 1 located around the P ⁻ type channel region 5, a P ⁺ type gate region containing a high concentration of P type impurities is formed. 6 are provided at a depth deeper than the depth of the P ⁻ type channel region 5. Further, in the upper layer portion of the P ⁻ type channel region 5 corresponding to the surface layer portion of the semiconductor substrate 1, an N ⁺ type cathode region 7 containing a high concentration of N type impurities is provided at a predetermined depth in the central portion thereof. ing.
Then, in order to pull out various terminals (not shown) necessary for the operation of the static induction thyristor from the semiconductor substrate 1 provided with various semiconductor regions in this way, a predetermined semiconductor facing the back surface and the front surface of the semiconductor substrate 1 is obtained. Various electrodes are installed in the area.

That is, on the back surface of the semiconductor substrate 1, for example, by depositing a conductive material such as aluminum on the entire surface by a method such as a vacuum deposition method or a sputtering method, the bottom surface of the P ⁺ -type anode region 2 is deposited. The anode electrode 8 is installed in a state of being electrically connected to the part. The surface of the semiconductor substrate 1 is exposed from the opening of the field oxide film 4 by selectively etching a conductive material such as aluminum deposited on the entire surface by the above-described method. ^A gate electrode 9 and a cathode electrode 10 are provided in a conductive state on the upper surface portions of the ⁺ type gate region 6 and the N ⁺ type cathode region 7, respectively.

Then, as shown in FIG. 1B, when the turn-on operation of the electrostatic induction thyristor having the above-mentioned structure is actually performed, the anode current I _A as a main current flowing into the anode electrode 8 at the time of actual operation thereof. At time t ₁ shown in the figure, the gate electrode 9 is immediately increased by a control of an external drive circuit (not shown) to a slight gate current I _G to immediately increase to a latch-up state. By continuing to apply the previous gate current I _G to the gate electrode 9 as a holding current for stabilizing the level of the current I _A , this static induction thyristor comes to maintain the ON state. In order to perform the turn-off operation of the electrostatic induction thyristor in the ON state, the gate current 9 is applied from the gate electrode 9 by the control of the external drive circuit.
_G (current in the direction opposite to the gate current I _G at the time of turn-on operation) is forcibly drawn out, and when the level of the anode current I _A begins to drop at time t ₂ shown in the figure, the gate from the gate electrode 9 thereof is started. The extraction of the current I _G may be stopped.

[0008]

By the way, in this type of electrostatic induction thyristor, since its turn-on sensitivity is very good, the turn-on operation can be performed even with a small gate current I _G as shown in FIG. Although is easily done, on the other hand, in the pull-out current is required to turn-off operation ratio of the magnitude of the main current to the size of (the gate current I _G) (anode current _{I a) (I a / I} G) Turn off
Since the gain is as low as 1 to 3, in order to reliably perform the turn-off operation of this electrostatic induction thyristor, a large gate current I _G corresponding to the magnitude of the anode current I _A which is the main current is applied from the gate electrode 9. Need to be pulled out. In other words, in order to reliably perform the turn-off operation of this type of electrostatic induction thyristor, it is necessary to use a large external drive circuit having high withstand current characteristics that is not destroyed even by a large drawing current.

The present invention has been made on the basis of such an actual situation, and an object thereof is to eliminate a need for using a large external drive circuit, and to provide a statically turning-off mechanism by a slight drawing current. An object is to provide a semiconductor device such as an electric induction thyristor and other ordinary thyristors.

[0010]

First, according to the invention of claim 1, a P-type semiconductor region is provided in an upper layer portion of a semiconductor substrate, and P is provided in an upper layer portion of the semiconductor substrate located around the P-type semiconductor region. The present invention is applied to a semiconductor device such as an electrostatic induction thyristor in which a type gate region is provided and an N type cathode region is provided in the surface layer portion of a semiconductor substrate located in the center of the P type semiconductor region. N is formed on the surface layer of the semiconductor substrate located in the portion where the gate region faces the P-type semiconductor region.
A type gate short circuit region is provided, and a first gate electrode is provided over both the upper surface of the N type gate short circuit region and the upper surface of the P type gate region.
The second gate electrode is provided above the P-type semiconductor region located between the type gate short region and the N-type cathode region with an insulating film interposed therebetween.

According to a second aspect of the invention, an N-type semiconductor region is provided in the upper layer portion of the semiconductor substrate, and an N-type gate region is provided in the upper layer portion of the semiconductor substrate located around the N-type semiconductor region. Further, the present invention is applied to a semiconductor device such as an electrostatic induction thyristor in which a P-type cathode region is provided in the surface layer portion of a semiconductor substrate located in the center of the N-type semiconductor region, and the N-type gate region is an N-type semiconductor A P-type gate short circuit region is provided in the surface layer portion of the semiconductor substrate located in a portion facing the region, and a first gate electrode is provided over both the upper surface portion of the P-type gate short circuit region and the upper surface portion of the N-type gate region. And a second gate electrode provided above the N-type semiconductor region located between the P-type gate short region and the P-type cathode region with an insulating film interposed therebetween. It is an feature.

Further, according to the invention of claim 3, a P-type semiconductor region is provided in an upper layer portion of the semiconductor substrate and the P-type semiconductor region is provided.
The present invention is applied to a semiconductor device such as an ordinary thyristor in which an N-type cathode region is provided on a surface layer portion of a semiconductor substrate located in a predetermined portion of the N-type semiconductor region, and is separated from the N-type cathode region by a predetermined distance. An N-type gate short circuit region is provided on the surface layer of the semiconductor substrate located at the portion, and a first gate electrode is provided over both the upper surface of the N-type gate short circuit region and the upper surface of the P-type semiconductor region. In addition, a second gate electrode is provided above the P-type semiconductor region located between the N-type gate short region and the N-type cathode region with an insulating film interposed therebetween. is there.

According to a fourth aspect of the invention, the N-type semiconductor region is provided in the upper layer portion of the semiconductor substrate, and the N-type semiconductor region is provided.
The present invention is applied to a semiconductor device such as an ordinary thyristor in which a P-type cathode region is provided on a surface layer portion of a semiconductor substrate located at a predetermined portion of the P-type semiconductor region, and is separated from the P-type cathode region by a predetermined distance. A P-type gate short circuit region is provided in the surface layer portion of the semiconductor substrate located in the portion, and a first gate electrode is provided over both the upper surface portion of the P-type gate short circuit region and the upper surface portion of the N-type semiconductor region, In addition, the second gate electrode is provided above the N-type semiconductor region located between the P-type gate short region and the P-type cathode region with the insulating film interposed therebetween. is there.

The invention according to claim 5 is characterized in that the depth of the N-type gate short region in the invention according to claim 1 or 3 is set to be substantially equal to the depth of the N-type cathode region. On the other hand, according to the invention of claim 6, the depth of the P-type gate short region in the invention of claim 2 or 4 is set to be substantially equal to the depth of the P-type cathode region. It is a feature.

[0015]

First, in the invention according to claim 1 or 3, an electrode having a MOS (metal-oxide-semiconductor) structure is constituted by the second gate electrode, the insulating film and the P-type semiconductor region. The electrode, the N-type cathode region, and the N-type gate short region form the NM
An OS transistor is formed. And this NMOS
When the transistor is turned on by the positive bias applied to the second gate electrode during the turn-off operation, the P-type gate is formed through the N-type gate short region connected to the ground potential through the first gate electrode. Excess carriers accumulated in the region or the P-type semiconductor region and the N-type cathode region are discharged from each other.

In the invention according to claim 2 or 4, the second gate electrode, the insulating film and the N-type semiconductor region constitute an electrode having a MOS structure.
The S-structure electrode, the P-type cathode region and the P-type gate short region form a PMOS transistor. When the PMOS transistor is turned on by the negative bias applied to the second gate electrode during the turn-off operation, the PMOS transistor is connected through the first gate electrode to the ground potential via the P-type gate short region. , The N-type gate region or the N-type semiconductor region and the P-type cathode region are discharged with excess carriers stored in each other.

According to the invention of claim 5, the depth of the N-type gate short region in the invention of claim 1 or 3 is set to be substantially equal to the depth of the N-type cathode region. Region is simultaneously formed, while the depth of the P-type gate short region in the invention of claim 2 or 4 is substantially equal to the depth of the P-type cathode region as in the invention of claim 6. By setting, similarly, both regions are formed simultaneously.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. In this example,
First, an electrostatic induction thyristor, which is a main application target of the present invention, will be mainly described as a first embodiment, and then a normal thyristor to which the present invention can be applied will be described as a second embodiment. This will be additionally described.

First, FIG. 1 is a diagram for explaining the configuration and operation of the electrostatic induction thyristor according to the first embodiment of the present invention. However, FIG. 7A is a vertical cross-sectional view showing the internal structure of the electrostatic induction thyristor according to the first embodiment, and FIG. 6B is the vertical cross-sectional view of the electrostatic induction thyristor according to the first embodiment. It is a figure which shows the response of the anode current with respect to the gate voltage at the time of operation.

First, as shown in FIG. 1A, this static induction thyristor contains a high concentration of P-type impurities as a semiconductor region forming the entire semiconductor substrate 11 as in the conventional case. A P ⁺ type anode region 12 and an N ⁻ type base region 13 containing a low concentration of N type impurities are provided. Further, a gate oxide film 14 (substantially the same as the field oxide film 4 shown in the conventional example, which is substantially the same as the field oxide film 4 shown in the conventional example, is formed on the upper surface of the semiconductor substrate 11 composed of these two layers of semiconductor regions. Is used, and by introducing a P-type impurity or an N-type impurity from the opening obtained in the process of molding the gate oxide film 14, the upper layer portion of the semiconductor substrate 11 is also formed in the same manner as in the conventional case. To the surface layer portion, a P ⁻ type channel region 15 containing a P type impurity at a low concentration, a P ⁺ type gate region 16 containing a P type impurity at a high concentration, and an N region, respectively.
Comprising the type impurity at a high concentration N ⁺ type cathode region 1
7 is provided.

Here, as a characteristic part of the present invention, P
^In the surface layer portion of the semiconductor substrate 11 located in the portion where the ⁺ type gate region 16 faces the P ⁻ type channel region 15, the N ⁺ type gate short region 1 containing the N type impurity at a high concentration is formed.
8 are provided. If the depth of the N ⁺ type gate short region 18 is set to be substantially equal to the depth of the N ⁺ type cathode region 17, the both regions should be formed simultaneously by using a method such as a diffusion method. Is possible.

Strictly speaking, the above N ⁺ type cathode region 17
When both the N ⁺ type gate short region 18 and the N ⁺ type gate short region 18 are simultaneously formed by the diffusion method, there is a difference in impurity concentration between the P ⁻ type channel region 15 and the P ⁺ type gate region 16 which are the respective formation regions. Therefore, the depths of both the N ⁺ type cathode region 17 and the N ⁺ type gate short region 18 are different. That is, P having a high impurity concentration
The depth of the N ⁺ type gate short region 18 provided in the ⁺ type gate region 16 is shallower than the depth of the N ⁺ type cathode region 17 provided in the P ⁻ type channel region 15 having a low impurity concentration. In the present application, such a difference in depth is considered to be substantially equal depth.

Further, it is not necessary to strictly set the range of the N ⁺ type gate short region 18 so as to be completely included in the range of the existing P ⁺ type gate region 16 as shown in the figure. Even if the range slightly extends to the range of the side P ⁻ type channel region 15 due to the formation method or the like, it does not particularly affect the operation characteristics of the static induction thyristor.

On the other hand, in addition to the above, the above-mentioned N ⁺ type gate
Above the P ⁻ type channel region 15 located between the short region 18 and the N ⁺ type cathode region 17, for example, a method such as a CVD method (chemical vapor deposition method) is formed on the entire surface of the semiconductor substrate 11. By selectively etching a conductive material such as polysilicon deposited by using, the second gate electrode 19 is provided with the gate oxide film 14 interposed therebetween. That is, by the second gate electrode 19, the gate oxide film 14 and the P ⁻ type channel region 15, the MO
An electrode having an S structure is formed, and an NMOS transistor is formed by the electrode having the MOS structure and the N ⁺ type cathode region 17 and the N ⁺ type gate short region 18, and as a result, the electrostatic induction thyristor is slightly A mechanism for surely performing the turn-off operation even with such a drawing current is provided.

Then, by selectively etching an insulating material such as a silicon oxide material (SiO ₂ ) deposited on the entire surface of the semiconductor substrate 11 by a method such as the above-mentioned CVD method, the second An interlayer insulating film 20 is provided so as to surround the gate electrode 19 from above and laterally, and hereinafter, the lower surface portion of the P ⁺ -type anode region 12 and the above P ⁺
An anode electrode 21 and a first gate electrode made of a conductive material such as aluminum are provided on the upper surface of the P ⁺ type gate area 16 including the upper surface of the type gate / short area 18 and the upper surface of the N ⁺ type cathode area 17, respectively. 22 and the cathode electrode 23 are installed, and the desired electrostatic induction thyristor can be obtained as described above.

Next, the turn-on operation and turn-off operation of the electrostatic induction thyristor configured as described above will be described with reference to FIG. First, at the time of turn-on operation, the first gate voltage V _G1 which is a positive bias is applied from the external drive circuit to the P ⁺ type gate region 16 through the first gate electrode 22 (time t in the figure).
₁₁ ). Then, the P contacting the P ⁺ type gate region 16
^- to type channel region 15, electrons from the N ⁺ -type cathode region 17 is connected to the negative side of the potential through the cathode electrode 23 are injected, along with this, N ^- -type base region 13, P ^- -type channel region 15 The NPN transistor composed of the N ⁺ -type cathode region 17 and the N ⁺ -type cathode region 17 is turned on, and as a result, electrons are injected into the N ⁻ -type base region 13 corresponding to the collector of the NPN transistor to generate a collector current. Further, this collector current corresponds to the base current for turning on the PNP transistor formed of the P ⁺ type anode region 12, the N ⁻ type base region 13 and the P ⁺ type gate region 16, so that the base current Holes are injected from the P ⁺ -type anode region 12 connected to the positive side potential through the anode electrode 21 to the P ⁺ -type gate region 16, and most of the holes correspond to the base of the NPN transistor. ^A base current is generated by being injected into the ⁻ type channel region 15. Then, this base current is the same as the above-mentioned N ⁺ type cathode region 17
Acts to further promote the injection of electrons from
A positive feedback loop is formed between the above NPN transistor and PNP transistor to increase the anode current I _A , and as a result, this static induction thyristor is turned on.

In addition, it should be noted that, even after the electrostatic induction thyristor is turned on, the first gate voltage V _G1 is still applied as shown in the figure because the anode current I _A in the on state is changed. This is for stabilizing the level, and the supply of the first gate voltage V _G1 to the first gate electrode 22 is normally continued until just before the turn-off operation of the static induction thyristor needs to be performed.

On the other hand, in the turn-off operation, the second gate voltage V _G2 , which is the same positive bias as in the previous turn-off operation, is applied from the external drive circuit to the second gate electrode 19.
As a pulse (time t ₁₂ shown). Then, the gate oxide film 1 on the lower surface of the second gate electrode 19 is formed.
4, the surface layer portion of the P ⁻ type channel region 15 located immediately below 4 is inverted to the N type, and includes the N ⁺ type cathode region 17 and the N ⁺ type gate short region 18
The OS transistor is turned on. And this NM
When the OS transistor is turned on, the P ⁺ type gate region 16 and the N ⁺ type gate short region 18 are connected via the first gate electrode 22, so that the P ⁺ type gate region 16 and the N ⁺ type cathode are connected. Area 17 shorts and P
The holes of the excess carriers accumulated in the ⁺ type gate region 16 are extracted to the cathode electrode 23 via the above NMOS transistor. As a result, the inflow of electrons from the N ⁺ type cathode region 17 to the N ⁻ type base region 13 is stopped, the positive feedback loop between the NPN transistor and the PNP transistor is released, and the anode current I _A is cut off. , The static induction thyristor is turned off.

Here, since the turn-off operation by the electrostatic induction thyristor is a method of short-circuiting the P ⁺ type gate region 16 and the N ⁺ type cathode region 17 to extract excess carriers, as in the conventional case, an external drive circuit is used. It is not necessary to forcibly pull out the gate current I _G by the control of the control circuit, and its turn-off operation is performed by applying the second gate voltage V _G2 to the second gate electrode 19 of the MOS structure, so that almost no current flows. . Moreover, this second
Since the polarity of the gate voltage V _G2 is the same positive bias as the polarity of the first gate voltage V _G1 during the turn-on operation,
For this electrostatic induction thyristor, it is possible to use a small external drive circuit of the simplest configuration in which only one side power source that generates a positive bias is built in.

In the first embodiment described above, N
Since the N ⁺ type gate short region 18 for forming the MOS transistor is formed by utilizing the range of the existing P ⁺ type gate region 16, this new N ⁺ type gate short region 18 is formed.
Providing the short region 18 on the semiconductor substrate 11 does not increase the chip area.

Even if the conductivity type of each semiconductor region constituting the first embodiment is changed from P type to N type and N type to P type, the same operation is performed. However, in this case, the second
Since the gate electrode 19, the gate oxide film 14, the N ⁻ type channel region (15), the P ⁺ type cathode region (17) and the P ⁺ type gate short region (18) form a PMOS transistor, During the turn-on operation, the negative drive first gate voltage V _G1 is applied to the first gate electrode 22 from the external drive circuit, and during the turn-off operation, the negative bias second gate voltage V _G2 is also applied. I will add it to 19.

Next, FIG. 2 is a vertical sectional view showing the internal structure of a normal thyristor according to the second embodiment of the present invention.
The operation principle of this thyristor is the same as that of the electrostatic induction thyristor according to the first embodiment described above, and therefore its explanation is omitted.

As shown in the figure, this thyristor has
Similar to the first embodiment, the semiconductor substrate 31 has a P ⁺ type anode region 32, an N ⁻ type base region 33,
A gate oxide film 34, P-type channel region 35 and the N ⁺ -type cathode region 37 is provided, further, the surface layer portion of the semiconductor substrate 31 positioned from the N ⁺ type cathode region 37 in a portion at a predetermined distance (previously P in the first embodiment of
^An N ⁺ type gate short region 38 containing a high concentration of N type impurities is provided in a surface layer portion of the semiconductor substrate 11 located in a portion where the ⁺ type gate region 16 faces the P type channel region 15. ing.

Then, above the P type channel region 35 located between the N ⁺ type gate short region 38 and the N ⁺ type cathode region 37, the second gate electrode is formed with the gate oxide film 34 interposed therebetween. 39, the second gate electrode 39, the gate oxide film 34, and the P-type channel region 35 constitute an electrode of a MOS structure, and the electrode of the MOS structure and the N ⁺ -type cathode region 37.
And N ⁺ type gate short region 38
The OS transistor is configured, and as described above, the thyristor is provided with the mechanism for performing the turn-off operation.
Further, the interlayer insulating film 40 is provided so as to surround the second gate electrode 39 from above and laterally, and hereinafter, as in the first embodiment, the lower surface portion of the P ⁺ -type anode region 32, P ⁺ including the upper surface of the P ⁺ type gate short region 38
The anode electrode 41 and the first electrode are formed on the upper surface of the mold channel region 35 and the upper surface of the N ⁺ -type cathode region 37, respectively.
The gate electrode 42 and the cathode electrode 43 are provided, and as described above, a desired thyristor can be obtained.

Incidentally, each semiconductor constituting the second embodiment is
Place the conductivity type of the body region from P-type to N-type, N-type to P-type
It is also possible to change, and in this case, the first real
As in the example, the second gate electrode 39, the gate
Oxide film 34, N-type channel region (35), P⁺Type
Area (37) and P⁺Type gate short area
(38) forms a PMOS transistor
Therefore, the external drive
The first gate voltage V with a negative bias from the circuit _G1The first
1 In addition to the gate electrode 42, the same is true during turn-off operation.
The second gate voltage V, which is a negative bias_G2The second
It may be added to the gate electrode 39.

[0036]

As described above in detail, the first aspect of the present invention is as follows.
Alternatively, according to the invention described in 3, the NMOS transistor configured by the second gate electrode, the insulating film, the P-type semiconductor region, the N-type cathode region, and the N-type gate short region serves as the second gate electrode during the turn-off operation. When it is turned on by the applied positive bias, it is connected to the ground potential through the first gate electrode.
Excess carriers accumulated in the P-type gate region or the P-type semiconductor region and the N-type cathode region are discharged from each other via the type gate / short region. It is not necessary to forcibly pull out the gate current by the control, and as a result, it becomes possible to perform control by a small external drive circuit of the simplest configuration in which only one side power source that generates a positive bias is built in.

Similarly, according to the invention of claim 2 or 4, a PMOS transistor constituted by a second gate electrode, an insulating film, an N-type semiconductor region, a P-type cathode region and a P-type gate short region is formed. When turned on by a negative bias applied to the second gate electrode during the turn-off operation, the N-type gate region or the N-type gate region or the N-type gate region is connected through the P-type gate short region connected to the ground potential through the first gate electrode. Since excess carriers accumulated in the P-type semiconductor region and the P-type cathode region are discharged from each other, in this case, only one side power source that generates a negative bias is built-in, and the simplest structure and small size are provided. Can be controlled by the external drive circuit.

According to the invention of claim 5, the depth of the N-type gate short region in the invention of claim 1 or 3 is set to be substantially equal to the depth of the N-type cathode region. As described in Item 6, by setting the depth of the P-type gate short region in the invention of Claim 2 or 4 to be substantially equal to the depth of the P-type cathode region, the formation of both regions is performed simultaneously. Since the N-type gate short-circuit region or the P-type gate short-circuit region is formed by utilizing the existing semiconductor region, the chip area of this semiconductor device does not increase.

[Brief description of drawings]

1A and 1B are views for respectively explaining a configuration and an operation of an electrostatic induction thyristor according to a first embodiment of the present invention, FIG. 1A is a longitudinal sectional view showing the internal structure thereof, and FIG.
FIG. 4 is a diagram showing a response of an anode current to a gate voltage during the operation.

FIG. 2 is a vertical cross-sectional view showing the internal structure of a normal thyristor according to a second embodiment of the present invention.

3A and 3B are views for explaining a configuration and an operation of a conventional electrostatic induction thyristor, respectively, FIG. 3A being a longitudinal sectional view showing an internal structure thereof, and FIG. 3B being an anode current with respect to a gate current during the operation. It is a figure which shows the response of.

[Explanation of symbols]

11, 31 Semiconductor substrate 14, 34 Gate oxide film 15, 35 P ⁻ type (P type) channel region 16 P ⁺ type gate region 17, 37 N ⁺ type cathode region 18, 38 N ⁺ type gate short region 19, 39 Second gate electrode 22, 42 First gate electrode

Claims (6)

[Claims] 1. A P-type semiconductor region is provided in an upper layer portion of a semiconductor substrate, a P-type gate region is provided in an upper layer portion of the semiconductor substrate located around the P-type semiconductor region, and the P-type semiconductor region is provided. A semiconductor device having an N-type cathode region provided in a surface layer portion of the semiconductor substrate located in a central portion of the semiconductor substrate, the N-type cathode region being provided in a surface layer portion of the semiconductor substrate located in a portion facing the P-type semiconductor region. A type gate short circuit region is provided, a first gate electrode is provided over both the upper surface of the N type gate short circuit region and the upper surface of the P type gate region, and the N type gate short circuit region is provided. A semiconductor device, comprising: a second gate electrode provided above the P-type semiconductor region located between the N-type cathode region and an insulating film. 2. An N-type semiconductor region is provided in an upper layer portion of a semiconductor substrate, an N-type gate region is provided in an upper layer portion of the semiconductor substrate located around the N-type semiconductor region, and the N-type semiconductor region is provided. A semiconductor device having a P-type cathode region provided in the surface layer portion of the semiconductor substrate located in the center of the semiconductor substrate, wherein P is provided in the surface layer portion of the semiconductor substrate located in a portion where the N-type gate region faces the N-type semiconductor region. And a first gate electrode is provided over both the upper surface of the P-type gate short area and the upper surface of the N-type gate area. A semiconductor device comprising a second gate electrode provided above the N-type semiconductor region located between the P-type cathode region and an insulating film. 3. A semiconductor device comprising a P-type semiconductor region provided in an upper layer portion of a semiconductor substrate, and an N-type cathode region provided in a surface layer portion of the semiconductor substrate located at a predetermined portion of the P-type semiconductor region. An N-type gate short-circuit region is provided in a surface layer portion of the semiconductor substrate located at a portion separated from the N-type cathode region by a predetermined distance, and an upper surface of the N-type gate short-circuit region and the P-type semiconductor region are formed. The first gate electrode is provided on both the upper surface portion and the N-type gate electrode.
A semiconductor device, comprising: a second gate electrode provided above the P-type semiconductor region located between the short-circuit region and the N-type cathode region with an insulating film interposed therebetween. 4. A semiconductor device comprising an N-type semiconductor region provided in an upper layer portion of a semiconductor substrate, and a P-type cathode region provided in a surface layer portion of the semiconductor substrate located at a predetermined portion of the N-type semiconductor region. A P-type gate short-circuit region is provided in a surface layer portion of the semiconductor substrate located at a portion separated from the P-type cathode region by a predetermined distance, and an upper surface portion of the P-type gate short-circuit region and the N-type semiconductor region are formed. A first gate electrode is provided on both the upper surface portion and the P-type gate electrode.
A semiconductor device comprising a second gate electrode provided above the N-type semiconductor region located between the short region and the P-type cathode region with an insulating film interposed therebetween. 5. The semiconductor device according to claim 1, wherein the depth of the N-type gate short region is set to be substantially equal to the depth of the N-type cathode region. 6. The semiconductor device according to claim 2, wherein the depth of the P-type gate short region is set to be substantially equal to the depth of the P-type cathode region.