JPS6320653A - Memory access method for multiprocessor system - Google Patents

Abstract

PURPOSE:To prevent the collision for a bus by constituting a system where one processor confirms contents of a read-only area after writing a flag on a write-only area and starts the access to a shared memory after confirming that another processor does not access the shared memory. CONSTITUTION:Even if CPUs 1 and 2 write flags in the first semaphore 4 and the second semaphore 5 for the purpose of accessing a shared memory 3, CPUs 1 and 2 do not access it because they read out flags from semaphores for read, and simultaneous access is prevented. When both flags are set, the flag of the semaphore set by one CPU is cleared, and the access is stopped to wait for reset of the flag of the semaphore set by the other CPU.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a memory access method in a system that includes a plurality of microprocessors and performs complex processing.
For example, it is used in a plastic extrusion molding machine system in which a control section that performs main control and a control section that performs input/output interface control are each configured by individual microprocessors.

(Prior Art) Conventionally, simple control systems are controlled by one microprocessor (CPU), but complex systems are equipped with multiple CPUs, and these CPUs
A so-called multi-processor system is constructed in which two processors work together. For example, among the plurality of CPUs 0, the master CPU is the one that also controls the remaining CPUs, and the slave CPU is the one that controls each part according to commands from the master CPU. Such a system is
For example, they are now used in various controllers such as plastic extrusion molding machines, which require increasingly complex control. In such a multiprocessor system, a shared memory that can be shared by both CPUs is provided, and mutual operations are mutually regulated. A flag called a semaphore is used to access this shared memory, and each CPU accesses the shared memory based on this flag.

(Problem to be Solved by the Invention) Conventionally, however, when accessing shared memory, one CPU first reads the contents of the semaphore and checks that no other CPU is using the shared memory, and then accesses the semaphore. I had flagged it for my own use. Therefore, if multiple CPUs read the contents of a semaphore at the same time, the semaphore flag is not set when one CPU reads the contents, so multiple CPtJs access the shared memory at the same time, and the address bus A data bus collision occurs.

(Means for Solving the Problems) The present invention provides a multiprocessor system in which a plurality of processors can each access a shared memory, in which a semaphore that stores flags for managing access to the shared memory is used for writing. It is separated into a dedicated area and a read-only area, and one processor writes a flag to the write-only area and then checks the contents of the read-only area to check that other processors are not accessing the shared memory.
Access to the shared memory is started only after jU.

(Function) When one processor accesses shared memory,
First, a flag is written in the write-only area, and then the contents of the read-only area are checked. If another processor is accessing the shared memory, a flag written by the other processor is set in this read-only area, so that one processor will not access the shared memory.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

The drawing is a block diagram showing the configuration of a semaphore in a multiprocessor system according to the present invention.

This example illustrates a multiprocessor system composed of two processors (hereinafter referred to as CPUs) 1 and 2, which share a shared memory 3. The CPUI is a control unit that monitors the CPU 2, for example, and performs automatic control according to its own control procedure and also regulates the operation of the CPU 2. That is, CPU2
CPtJl reads out the contents written in the shared memory 3 as appropriate, and CPtJl successively reads the contents to check the operating state of the CPU 2. Further, the operating procedure of the CPU 2 is executed according to the instruction procedure stored in the shared memory 3 by the CPUI. For example, in a plastic extrusion molding machine, the CPU 1 is used to control a heater for heating resin, an extrusion screw, etc. I
It automatically controls the target to start according to predetermined start-up conditions, and the CPU 2 controls input/output devices such as temperature sensors and sensors that detect the rotation speed of the extrusion screw. It is. Note that although two CPUIs 2 are illustrated in the drawing, of course three or more CPUs actually exist.

Two semaphores, a first semaphore 4 and a second semaphore 50, are connected to the CPU 1.2, and these semaphores 4 and 5 are readable and writable.

The first semaphore 4 can be written to by CPU 1, and
This is an area that can be read from PU2. Contrary to the first semaphore 4, the second semaphore 5 is an area where writing is performed by the CPU 2, and the CPU 2 is an area where only reading is performed. In this way, in this example, each of the two semaphores is
This configuration allows only reading or writing to one CPU.

In the multiprocessor system configured as described above, when the CPU accesses the shared memory 3, it first writes a flag to the first semaphore 4, and then reads the contents of the second semaphore 5. This second semaphore 5
is an area in which a flag that is set when the CPU 2 accesses the shared memory 3 is stored, so the second
If the flag is set on semaphore 5, CPU2
is accessing shared memory 3.

If the second semaphore 5 is not flagged, the CPU can recognize that the CPU 2 is not accessing the shared memory 3, so the CPU accesses the shared memory 3. When the CPU 2 accesses the shared memory 3, the procedure is the same as when the CPU 2 accesses the shared memory 3 described above. Therefore, even if the CPUI, 2 writes flags to the first semaphore 4 and the second semaphore 5 in order to access the shared memory 3, both CPtJl, 2
Since the flag is read from the read semaphore, no access is performed, and simultaneous access is prevented. When both flags are set, one CPU clears the semaphore flag set and stops access, and the other CPU clears the semaphore flag set by the other CPU.
All you have to do is wait for the semaphore flag set by the PU to fall.

(Effects of the Invention) As described above, according to the present invention, in a multiprocessor system, simultaneous access to shared memory is prevented and bus collisions do not occur.

[Brief explanation of the drawing]

The drawing is a block diagram illustrating a memory access method of a multiprocessor system according to the present invention. 1.2... CPU 3... Shared memory 4... First semaphore 5... Second semaphore Patent applicant Sekisui Chemical Co., Ltd. Representative Hiroshi 1) Kaoru

Claims (1)

[Claims] 1) In a multiprocessor system in which a plurality of processors can each access a shared memory, a semaphore that stores flags for managing access to the shared memory is separated into a write-only area and a read-only area. The processor writes a flag in the write-only area, checks the contents of the read-only area, and starts accessing the shared memory only after confirming that no other processor is accessing the shared memory. Memory access method for multiprocessor systems.