JP2003030042A - Microcomputer with cores - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform access to a shared memory among a plurality of cores. SOLUTION: Structure of a microcomputer with the plurality of cores including a plurality of cores 1, 2, 3 and a shared memory 10 is integrated on the same semiconductor integrated circuit chip. The individual cores independently execute program processing as exclusively accessing memories 11, 12, 13, respectively. The common data, etc., can be mutually used via the shared memory 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device with multiple cores having a plurality of cores and a shared memory on the same semiconductor integrated circuit chip.

[0002]

2. Description of the Related Art Conventionally, as a microcomputer realized by a semiconductor integrated circuit, a microcomputer having a plurality of cores including a CPU, a memory, peripheral circuits and the like is used.
Japanese Unexamined Patent Publication No. 2-244252 discloses a method in which a plurality of microprocessors are integrated on the same semiconductor integrated circuit chip.
With chip multiprocessor, common external bus,
Prior art about arbitration when memory accesses etc. are performed simultaneously is disclosed. One like this
A chip multiprocessor is used for the purpose of increasing throughput as a whole by a plurality of microprocessors sharing the same program and processing them in parallel. Each microprocessor shares a memory space and executes a program. In this prior art, priority is given to a plurality of microprocessors, and when at least two microprocessors simultaneously make an external access, the arbitration is performed so that the microprocessor having the highest priority makes the external access. .

A dual port RAM has also been commercialized as a memory device that allows simultaneous access from a plurality of processors. Dual-port RAM is a dual-core RAM in which two processors have the same RA in a microcomputer system.
It has a hardware configuration so that M can be accessed. Generally, a function of arbitrating access to the same memory cell is provided so that the address bus and the data bus do not conflict with each other. Simultaneous access is possible such that when one processor writes, the other processor reads. If one of the two processors is a CPU and the other is a dedicated processor for images and input / output, it is possible to transfer data and the like without synchronizing with each other, so that data and parameters can be efficiently transferred. Can be delivered. Dual port R
The AM can also be used for communication between microprocessors operating independently of each other and in parallel.

[0004]

Advances in semiconductor integrated circuit manufacturing technology have made it possible to realize large-scale integrated circuits with a relatively small chip area. Further, when designing an integrated circuit, it has become possible to use CAD (Computer Aided Design) to reduce the layout pattern of the integrated circuit manufactured in the past and use it as a part of a new integrated circuit. There is. Therefore, it is possible to further integrate a simultaneously accessible memory such as a dual port RAM on a semiconductor integrated circuit chip having a plurality of microprocessors as disclosed in Japanese Patent Laid-Open No. 2-244252. Has become.

However, it is merely disclosed in Japanese Patent Laid-Open No. 24-42525.
When access to the dual port RAM is performed by performing access arbitration with a plurality of microprocessors as disclosed in Japanese Patent Laid-Open No. 2 publication, only the microprocessor with a high priority preselected among the plurality of microprocessors has a dual port R
I cannot access the AM. Further, even if the dual port RAM allows simultaneous access from two microprocessors, the one having the earlier access has the right to write. Therefore, the processing of the important program may be postponed. Moreover, no simultaneous access from three or more microprocessors is considered. Therefore, Japanese Patent Laid-Open No. 2-24
The shared memory such as the dual port RAM cannot be effectively used for efficient data communication and exchange between the multi processors simply by integrating the dual port RAM in the one-chip multiprocessor disclosed in Japanese Patent No. 4252. .

It is an object of the present invention to provide a microcomputer device with a plurality of cores which can efficiently access a shared memory among a plurality of cores.

[0007]

The present invention provides a microcomputer device with a plurality of cores, which has a plurality of cores and a shared memory accessible from the plurality of cores on the same semiconductor integrated circuit chip. , For shared memory,
A microcomputer device with a plurality of cores, which comprises arbitration means for arbitrating a race condition between cores according to a predetermined arbitration condition when access is made from at least two cores.

According to the present invention, a microcomputer device with a plurality of cores has a plurality of cores and a shared memory accessible from the plurality of cores on the same semiconductor integrated circuit chip, and further, arbitration means. including. The arbitration unit arbitrates the race condition between the cores according to a predetermined arbitration condition when the shared memory is accessed from at least two cores, so that each core can freely access the shared memory. You can try. If the arbitration condition is satisfied, access can be continued, so
The shared memory can be accessed quickly.

Furthermore, the present invention is a microcomputer device with a plurality of cores having a plurality of cores and a shared memory accessible from the plurality of cores on the same semiconductor integrated circuit chip, wherein the shared memory comprises: Access from at least two cores is possible according to a predetermined arbitration condition, and each core detects the presence or absence of access from other cores when accessing the shared memory. , A plurality of characterized in that when there is no access from another core, the access to the shared memory is continued, and when there is an access from another core, it is judged whether the access is continued or suspended according to the arbitration condition. It is a microcomputer device with a core.

According to the present invention, a microcomputer device with a plurality of cores has a plurality of cores and a shared memory accessible from the plurality of cores on the same semiconductor integrated circuit chip. When accessing the shared memory, each core detects the presence / absence of an access from another core, and when there is no access from another core, continues the access to the shared memory, and When there is an access from, it is determined whether the access is continued or interrupted according to the arbitration condition, and therefore it is possible to access the shared memory among the plurality of cores according to the arbitration condition. A plurality of cores can use shared memory to share data and the like, and mutually mutually effective programs can be efficiently executed.

Further, in the present invention, priorities are set in advance for the plurality of cores, and the arbitration condition depends on a core having a higher priority when access from at least two cores competes with each other. It is characterized by continuation of access and interruption of access by a core having a lower priority.

According to the present invention, contention of access to the shared memory by at least two cores can be arbitrated according to a preset priority order. If important cores are set to perform important processing, the shared memory can be used preferentially for important processing.

Further, in the present invention, the arbitration condition is that when access from at least two cores competes, simultaneous access is continued if any access is read, and if there is a core to be written, It is characterized by continuation of writing from a core and interruption of reading from another core.

According to the present invention, when at least two cores all perform read access to the shared memory, simultaneous access is permitted, so that data or the like stored in the shared memory can be quickly read by two or more cores. be able to. When there is a core that writes to the shared memory, writing has priority, so when writing and reading conflict for data at the same address,
Arbitration can be performed so that data is written and then data is read.

Further, in the present invention, priorities are set in advance for the plurality of cores, and when there is at least two cores to be written as the arbitration condition, access by a core with a higher priority is performed. And the interruption of access by the core with the lower priority.

According to the invention, when there is contention for writing to shared memory from at least two cores,
Arbitration is performed according to a preset priority order. As a result of the arbitration, writing is performed by the core with the higher priority, so if the priority of the core performing the important processing is set high, the important processing can be performed quickly.

Further, the present invention is characterized in that the core is contained in three or more. According to the present invention, since the plurality of cores and the shared memory are integrated on the same semiconductor integrated circuit chip, there is no limitation such as the number of terminals as in the case where the shared memory is manufactured as a single semiconductor integrated circuit chip. ,
It is possible to easily realize not only access by two systems of address buses such as a dual port RAM, but also access by three or more systems of address buses, so that efficient use can be achieved.

[0018]

1 shows a schematic functional configuration of a microcomputer device with a plurality of cores as a first and second embodiment of the present invention. In this embodiment, a plurality of cores 1, 2, 3 are provided on the same semiconductor integrated circuit chip,
A shared memory 10, which is a RAM accessible from a plurality of cores 1, 2, 3 is integrated. Each core 1, 2,
3 also comprises dedicated memories 11, 12, 13. For the shared memory 10, at least two cores 1, 2,
When access is made from 3, access conflict occurs. The shared memory 10 is provided with an arbitration unit 20 to arbitrate the race condition between the cores according to a predetermined arbitration condition. The cores 1, 2, and 3 can be independently programmed, and three cores are provided. However, the present invention can be similarly applied as long as the cores are two or more. Since it is formed on the same semiconductor integrated circuit chip, it is a so-called multi-port RAM provided with ports capable of accessing three or more cores 1, 2 and 3, and many address signal lines and data signal lines are wired. Even if necessary, it can be realized more easily than when a wiring pattern is formed on a printed wiring board.

That is, the microcomputer device with a plurality of cores according to the present embodiment has a plurality of cores 1, 2, and 3 and a shared core which is accessible from the plurality of cores 1, 2, and 3 on the same semiconductor integrated circuit chip. And a arbitration means 20. The arbitration means 20 arbitrates the race condition between the cores 1, 2, and 3 according to a predetermined arbitration condition, so that each core 1, 2, and 3 can freely try to access the shared memory 10. If the arbitration condition is satisfied, the access can be continued, so the shared memory 1
Access to 0 can be performed quickly.

FIG. 2 shows a first embodiment of the present invention.
The arbitration procedure with respect to access competition performed by the arbitration means 20 of FIG. 1 is shown. In this embodiment, the plurality of cores 1,
Priority is set in advance for access to the shared memory 10 in 2 and 3, and when access conflicts,
Arbitrate according to priority. For example, the priority is
It is assumed that core 1> core 2> core 3. The procedure is started from step a0, and at step a1, it waits for any one of the cores 1, 2 and 3 to detect access to the shared memory 10 for reading or writing. One core 1,
When access from 2 or 3 is detected, step Ua2
Then, it is determined whether or not there is access from the other cores 1, 2, 3. If there is no access from the other cores 1, 2, 3, the core 1, detected in step a1 in step a3
Access from 2 and 3 is executed, and the process returns to step a1. If there is an access from the other cores 1, 2 and 3 in step a2 and there is a conflict in access to the shared memory 10, the access to the cores 1, 2 and 3 with lower priority is interrupted in step a4, and in step a5. Access from the cores 1, 2, and 3 having a high priority is executed. Step a5
Is completed, the process returns to step a1.

The interruption of access can be performed in various ways by the core 1,
A few can be notified. For example, a signal that forces a wait state can be used. The cores 1, 2, and 3 whose access has been interrupted suspend their operations until they become accessible, and resume their operations when they become accessible. Further, it is also possible to notify whether or not the access is permitted by a flag or the like, and the cores 1, 2, and 3 which are not permitted the access monitor the flag and wait for the access to be permitted. The flags are monitored intermittently, and other processing operations can be performed during the monitoring.

The microcomputer device with a plurality of cores as in the first embodiment is installed in, for example, an automobile, and the cores 1, 2 and 3 share the function of controlling various traveling-related functions, and the shared memory 10 is used. Can be used for control such that data and parameters are shared. The core 1, which has the highest priority, can be used for control related to engine ignition and fuel injection. The core 2 having the intermediate priority can be used for constant speed traveling control by controlling the throttle valve. Core 3 with the lowest priority
Can be used for transmission related control. The shared memory 10 can be used for commonization of common data and parameters such as engine rotation speed, vehicle traveling speed, and temperature. When an independent electronic control unit (ECU) is used instead of the cores 1, 2, and 3, common data and parameters must be transmitted by data communication processing between the electronic control units. The data communication process requires many configurations and is time consuming.
In the transmission via the shared memory 10, even if the access is interrupted at the time of contention of the access, the data can be transmitted very quickly as compared with the case of performing the data communication. If access is not interrupted, data can be transmitted more quickly.

FIG. 3 shows a second embodiment of the present invention.
The arbitration procedure with respect to access competition performed by the arbitration means 20 of FIG. 1 is shown. In this embodiment, the shared memory 10
When read and write conflict with each other, write is given priority, and when write conflict with each other, a preset priority order is followed. A plurality of read-only accesses to the shared memory 10 can be made simultaneously. Since writing is prioritized over reading, when there is a conflict between writing for updating data and reading for using the data, the data is prioritized and the data to be read is updated. Guaranteed to be data.

The procedure is started from step b0, and in step b1, it waits until an access from one core 1, 2, 3 is detected. When access from one core 1, 2, 3 is detected, it is determined in step b2 whether or not there is an access from another core 1, 2, 3. Other cores 1, 2,
If there is an access from 3 as well, the process moves to step b3, and it is determined whether or not the plurality of cores 1, 2 and 3 are trying to access the shared memory 10 for writing. When a plurality of cores 1, 2, 3 are about to write, the process moves to step b4, and the writing of cores 1, 2, 3 having a lower priority is interrupted. If multiple cores 1,
When there is a conflict in read access in addition to the write by 2 and 3, the access to the cores 1, 2 and 3 that is trying to read is interrupted regardless of the priority. Next, the process proceeds to step b5, and the writing of the cores 1, 2 and 3 having a high priority is executed. When step b5 ends, the process returns to step b1.

If it is determined in step b3 that the writing is not from a plurality of cores 1, 2, 3, then step b
At 6, it is judged whether or not the writing is from one core 1, 2, 3. If the writing is from one core 1, 2, or 3, the access from the reading cores 1, 2, or 3 is suspended in step b7, and the access from the writing cores 1, 2, or 3 is executed in step b8. Then, the process returns to step b1. Step b6
Cores 1, 2, 3 trying to access for writing with
If it is determined that there is no such a case, the simultaneous access is executed in step b9, and the process returns to step b1.

FIG. 4 shows a schematic functional configuration of a microcomputer device with a plurality of cores according to the third and fourth embodiments of the present invention. In the present embodiment, parts corresponding to those in the embodiment of FIG. 1 are designated by the same reference numerals, and overlapping description will be omitted. In this embodiment, a plurality of cores 21, 22, 23 and a plurality of cores 2 are provided on the same semiconductor integrated circuit chip.
A shared memory 10, which is a RAM accessible from 1, 22, and 23, is integrated. Each core 21, 22, 2
3 has dedicated memories 11, 12 and 13, respectively, and accesses the shared memory 10 to
It also has a function of arbitrating according to a predetermined arbitration condition when competing with access from other cores 21, 22, 23. The cores 21, 22, and 23 can be independently programmed, and three cores are provided. However, the present invention can be similarly applied to two or more cores.

That is, the microcomputer device with a plurality of cores according to the present embodiment has a plurality of cores 21, 22 and 23, and a plurality of cores 21 and 21, on the same semiconductor integrated circuit chip.
22 and 23, the shared memory 10 that can be accessed, and the shared memory 10 includes at least two cores 21 and 2.
It is possible to access from 2 and 23 according to a predetermined arbitration condition. Each core 21, 22, 23
Detects whether or not there is an access from the other cores 21, 22 and 23 when accessing the shared memory 10, and when there is no access from the other cores 21, 22 and 23 to the shared memory 10. When the access is continued and there is an access from another core 21, 22, 23, it is determined whether the access is continued or interrupted according to the arbitration condition. Since a plurality of cores 21, 22, and 23 can access the shared memory 10 according to the arbitration condition, the shared memory 10 is used to share data and the like, and the mutual programs are executed independently. Such an operation can be efficiently performed.

FIG. 5 shows a third embodiment of the present invention.
Similar to FIG. 2, the priority order is set in advance for the plurality of cores 21, 22, 23, and the arbitration procedure in each core 21, 22, 23 when the arbitration condition is to follow the priority order is shown. The procedure is started from step c0, and at the time of starting access to the shared memory 10 in step c1, it is determined whether or not there is an access from another core 21, 22, 23. When it is determined that there is an access from the other cores 21, 22, and 23, the process proceeds to step c2, and it is determined whether or not the priority order of the own core is higher than the priority order of the other cores. When it is determined that the priority of the own core is not higher, the access of the own core is interrupted in step c3, the access of another core is executed in step c4, and the process returns to step c1. If it is determined in step c2 that the priority of the local core is higher than the priority of other cores, the access of the local core is executed in step c5, and the step c1 is executed.
Return to.

In this embodiment, each core 21, 22, 23
It has a function of arbitrating contention of access to the shared memory 10 by at least two cores 21, 22 and 23 by itself according to a preset priority order. If the important processing is performed by the cores 21, 22, 23 having a high priority, the shared memory 10 can be preferentially used for the important processing.

FIG. 6 shows a fourth embodiment of the present invention.
A procedure in which each core 21, 22, 23 itself performs arbitration for access competition under the same arbitration condition as in FIG. In the present embodiment, when there is a conflict between reading and writing in the shared memory 10, the writing is prioritized, and when there is a conflict between the writing, the preset priority order is followed. A plurality of read-only accesses to the shared memory 10 can be made simultaneously.

The procedure is started from step d0, and in step d1, the shared memory 1 from the other cores 21, 22, 23.
It is determined whether or not 0 is accessed. When it is determined that there is an access from the other cores 21, 22, 23, it is determined in step d2 whether or not the other cores 21, 22, 23 are about to write. When the writing is not attempted, the access is executed in step d3. Even when it is determined in step d1 that there is no access from the other cores 21, 22, 23, the access is executed in step d3.

In step d2, the other cores 21, 22, 23
If it is determined that the cores 21, 22 and 23 are also writing, it is determined whether or not the cores 21, 22, 23 are also writing. Own core 21,2
When 2 and 23 are also trying to write, a write conflict occurs, so check the priority order in step d5,
When the priority order of the own cores 21, 22, 23 is higher, the writing is executed in step d6 and the process returns to step d1.
When it is determined in step d4 that the own cores 21, 22, and 23 are not writing, or in step d5, the priority order of the own cores is about to write the other cores 21, 22, and 23.
If the priority is not higher than 23, step d7
Access is interrupted and the process returns to step d1.

[0033]

As described above, according to the present invention, when the shared memory is accessed from at least two cores, the arbitration means arbitrates the race condition between the cores according to a predetermined arbitration condition. To be done. Since each core can freely access the shared memory and continue the access if the arbitration condition as a predetermined rule is satisfied, the shared memory can be quickly accessed.

Further, according to the present invention, when a plurality of cores access the shared memory, each core arbitrates in response to an access from another core, so that the plurality of cores are shared according to the arbitration condition. The memory can be accessed. The plurality of cores execute programs mutually independently, and can efficiently perform an operation of sharing some data.

Further, according to the present invention, it is possible to arbitrate contention for access to the shared memory according to a preset priority order. If important processes are assigned to cores with a high priority, the shared memory can be used preferentially to execute the processes.

Further, according to the present invention, since simultaneous access is permitted if only read access to the shared memory is allowed, two or more cores can quickly read data from the shared memory. When there is a core that writes to the shared memory, the write is prioritized, so that it is possible to perform arbitration so that the data is read and then the data is read.

Further, according to the present invention, it is possible to arbitrate the contention of writing to the shared memory according to the priority order. By setting the priority of cores that perform important processing to be high, important processing can be performed quickly.

Further, according to the present invention, by utilizing the fact that a plurality of cores and a shared memory are integrated on the same semiconductor integrated circuit chip, simultaneous access by three or more cores is possible and the efficiency of the shared memory is improved. It can be used for various purposes.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic functional configuration of a microcomputer device with a plurality of cores according to first and second embodiments of the present invention.

FIG. 2 is a flowchart showing an arbitration procedure according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing an arbitration procedure according to the second embodiment of the present invention.

FIG. 4 is a block diagram showing a schematic functional configuration of a microcomputer device with a plurality of cores according to third and fourth embodiments of the present invention.

FIG. 5 is a flowchart showing an arbitration procedure in the third embodiment of the invention.

FIG. 6 is a flowchart showing an arbitration procedure according to the fourth embodiment of the present invention.

[Explanation of symbols]

1,2,3,21,22,23 core 10 shared memory 11,12,13 memory 20 Mediation means

Claims (6)

[Claims] 1. A microcomputer device with a plurality of cores, comprising: a plurality of cores; and a shared memory accessible from the plurality of cores on the same semiconductor integrated circuit chip. When access is performed from two cores, according to the predetermined arbitration condition,
A microcomputer device with a plurality of cores, which comprises arbitration means for arbitrating a race condition between cores. 2. A microcomputer device with a plurality of cores having a plurality of cores and a shared memory accessible from the plurality of cores on the same semiconductor integrated circuit chip, wherein the shared memory comprises at least two. It is possible to access from a core according to a predetermined arbitration condition. When each core accesses the shared memory, it detects the presence or absence of an access from another core, and When there is no access from the core, the access to the shared memory is continued, and when there is an access from another core,
A microcomputer device with a plurality of cores, which determines whether access is continued or interrupted according to the arbitration condition. 3. A priority order is set in advance for the plurality of cores, and the arbitration condition is that continuation of access by a core with a higher priority order when access from at least two cores competes with each other. 3. The microcomputer device with a plurality of cores according to claim 1 or 2, characterized in that the access is interrupted by a core having a lower priority. 4. The arbitration condition is that, when access from at least two cores competes with each other, if any access is read, simultaneous access is continued. The microcomputer device with a plurality of cores according to claim 1 or 2, characterized in that the writing is continued and the reading from the other core is interrupted. 5. A priority order is set in advance for the plurality of cores, and when the arbitration condition includes at least two cores to be written, continuation of access by a core with a higher priority order is performed. 5. The microcomputer device with multiple cores according to claim 4, further comprising: interruption of access by a core having a lower priority. 6. The microcomputer device with a plurality of cores according to claim 1, wherein three or more cores are included.