JPS63200565A - Manufacture of hetero junction semiconductor device - Google Patents

Abstract

PURPOSE:To accurately selectively etch a hetero junction by etching the hetero junction of an In-Ga-As layer and an In-Al-As layer with gas containing chlorine. CONSTITUTION:In a hetero junction semiconductor device having a hetero junction 3 of an In-Ga-As layer 1 and an In-Al-As layer 2, the junction 3 is etched with gas containing chlorine. The layer 1 is etched by this etching, and the layer 2 is stopped from etching at its surface 2a. Thus, the junction 3 can be selectively etched accurately.

Description

[Detailed Description of the Invention] [Summary] Method for manufacturing a heterojunction semiconductor device having a heterojunction of an indium-gallium-arsenide layer and an indium-aluminum-arsenide layer or an indium-aluminum-gallium-arsenide layer By etching the heterojunction with a gas containing chlorine, the indium/gallium/arsenic layer is etched and the surface of the indium/aluminum/arsenic layer or the indium/aluminum/gallium/arsenic layer is etched. This makes it possible to perform selective etching of heterojunctions with high precision.

[Industrial application field]

The present invention relates to a method for manufacturing a heterojunction semiconductor device, and particularly 1. an indium-gallium-arsenide (InGaAs) layer and an indium-aluminum-arsenide (InAIAs) layer or an indium-aluminum-gallium-arsenide (InAIAs) layer;
The present invention relates to a method for manufacturing a heterojunction semiconductor device having a heterojunction with a GaAIAs) layer.

[Conventional technology]

In recent years, high electron mobility transistors (HEMT) and R1 (ET and RB
Resonant tunneling transistors such as T
T-Tunneling Transistor:
RTT) etc. are attracting attention. These HEMTs, R
Elements such as HET and RBT are each made of InGaAs.
It has a heterojunction between the layer and the InAlAs layer or the InGaAlAs layer.

FIG. 5 is a sectional view showing a HEMT device manufactured by a conventional method, and FIG. 6 is a sectional view showing a RHET device manufactured by a conventional method.

According to conventional methods, HEMT devices are manufactured using, for example, molecular beam epitaxy (MBE), as shown in FIG. 5(a).
An InGaAs buffer 52, an InGaAs layer 53, an n-InAIAs layer 5 are formed on an InP substrate 51 by
Furthermore, resist layers 56 are formed on both sides of the n''-1nQaAs layer 55, as shown in FIG. 5(b). Predetermined portions of layer 55 are etched. Here, n''-1nQaAs layer 55 is a layer for ohmic contact. Then, as shown in FIG. 5(C), the resist layer 56 is removed and the n''
A source electrode 57a and a drain electrode 57b are formed on both sides of the InGaAs layer 55, and
- A gate electrode 58 is formed on the InAIAs layer 54 to manufacture a HEMT device.

Furthermore, according to the conventional method, the RHET element is
), for example, by the MBE method, n”
-1nP substrate 61 has n”-1nQa as a collector.
As layer 62.1-1nAIAs barrier 63, n-InGaAs layer 64.1-1nAIAs barrier 6
5 and an n''-1nQaAs layer 66 which will serve as an emitter are successively formed.

Further, a resist layer 67 is formed on the upper center of the n''-1nQaAs layer 66, and predetermined portions of the n'''-1nQaAs layer 66 are etched. Then, as shown in FIGS. 6(b) and 6(c), the resist layer 67 is removed and space electrodes 67a and 67b are formed on both sides of the 1-1nAIAs barrier 65, and the n''-1nQa
An emitter electrode 68 is formed at the upper center of the As layer 66 to manufacture a RHET device.

In the above, the etching of the heterojunction of the HEMT element and the RHET element is performed using, for example, H2O2: (2
0: 1 = H2O: HF): HzO = 4:5
Wet etching is performed using a hydrofluoric acid-based etching solution of :260.

[Problem that the invention seeks to solve]

As mentioned above, conventional HEMTs with heterojunctions
When manufacturing a semiconductor device such as a semiconductor device or a RHET, wet etching is performed using a hydrofluoric acid-based etching solution.

By the way, for example, H20□: (20:1 = H20
:HF):H20=4:5:260 etching properties of InGa, As and InAlAs with an etching solution of 950 people/ll1i for InGaAs.
n, and InAlAs force<1900 people/min. Therefore, it is difficult to selectively etch only InGaAs and not InAIAs, and as shown in FIGS. 5(b) and 6(b), the n-InAIAs layer 54 Ya n
In some cases, the -1nQaAs layer 64 was etched too much (overetched) or not etched enough.

In this way, for example, as shown in FIG. 5(b),
If the n-InAlAs layer 54 could not be etched accurately, the dark voltage of the HEMT device would vary, making it impossible to manufacture the device as designed. Also,
As shown in FIG. 6(b), if the n-InGaAs layer 64 that forms the base of the RHET is overetched, the base resistance increases and the operating speed decreases, and the frequency characteristics worsen and the yield decreases. was there.

In view of the above-described conventional method for manufacturing a heterojunction semiconductor device, the present invention etches the indium, gallium, and arsenic layer by etching the heterojunction with a gas containing chlorine. Etching is stopped at the surface of the indium, aluminum, gallium, and arsenic layers, allowing selective etching of heterojunctions.
The purpose is to perform notching with high precision.

[Means for solving problems]

FIG. 1 is a sectional view showing the principle of a method for manufacturing a heterojunction semiconductor device according to the present invention.

According to the present invention, there is provided a method for manufacturing a heterojunction semiconductor device having a heterojunction 3 between an indium-gallium-arsenide layer l and an indium-aluminum-arsenide layer or an indium-aluminum-gallium-arsenide layer 2, comprising: By etching the heterojunction 3 with a gas containing chlorine, the indium-gallium-arsenic layer 1 is etched.
There is provided a method for manufacturing a heterojunction semiconductor device, characterized in that the etching is stopped at the surface 2a of the indium-aluminum-arsenic layer or the indium-aluminum-gallium-arsenic layer by etching and notching.

[For production]

According to the method for manufacturing a semiconductor device of the present invention having the above-described configuration, a heterojunction 3 is formed between an indium-gallium-arsenic layer I and an indium-aluminum-arsenic layer or an indium-aluminum-gallium-arsenic layer 2. In the junction semiconductor device, the heterojunction 3 is etched with a gas containing chlorine, so the indium-gallium-arsenic layer 1 is etched, and the indium-aluminum-arsenic layer or the indium-aluminum-gallium-arsenic layer 2 is etched. Etching is stopped at surface 2a.

Thereby, the heterojunction 3 can be selectively etched with high precision.

〔Example〕

Embodiments of the method for manufacturing a heterojunction semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram schematically showing an etching apparatus to which the method for manufacturing a heterojunction semiconductor device of the present invention is applied.

The etching apparatus shown in FIG. 2 is a photoexcitation type etching apparatus that performs dry etching using ultraviolet rays irradiated from a high-pressure mercury lamp 11. That is, a sample mounting table 14 is provided at the lower center of the chamber 10, and a sample 15 to be etched is placed on the sample mounting table 14. A high pressure mercury lamp 11 is located above the center of the chamber 10.
is provided, and the ultraviolet rays emitted from this high-pressure mercury lamp 11 are controlled by a shutter 11a so as to be irradiated onto the sample 15. Further, an intake pipe 12 is provided above one side of the chamber IO, and chlorine gas (CIx gas) is introduced into the chamber 10 from this intake pipe 2.

Further, an exhaust pipe I3 is provided below the other side of the chamber 10 to exhaust the C12 gas used for etching and the remaining gas from the chamber 10.

In such an etching apparatus, CI2 gas introduced into the chamber 10 from the intake pipe 12 is radicalized by ultraviolet rays irradiated from the high-pressure mercury lamp 11, and the sample 15 is dry-etched by the chlorine radicals (CI). will be held.

Here, the etching apparatus to which the method for manufacturing a heterojunction semiconductor device of the present invention is applied is not limited to the photoexcitation type etching apparatus shown in FIG. Various etching apparatuses for reactive ion etching (RIE) may be used.

FIG. 3 is a diagram showing the etching characteristics of each layer etched by the method for manufacturing a heterojunction semiconductor device of the present invention. Specifically, FIG. layer and InA
FIG. 3 is a diagram showing etching characteristics with an lAs layer.

In FIG. 3, the horizontal axis represents the distance between the shutter 11a (light source) of the high-pressure mercury lamp 11 in FIG. 2 and the sample 15, and the vertical axis represents the amount of etching per minute. As is clear from this Figure 3, the distance between the sample and the light source is approximately 3a.
In the range of 11 to 5 cm, the etching amount of the InGaAs layer is about 1 pm (1000 people)/min, while the etching amount of the InAlAs layer is about 1 pm (1000 people)/min.
00 people/min. This means that in dry etching using C12 gas and ultraviolet light, InA
This shows that the lAs layer is less easily etched than the InGaAs layer. Thus, in dry etching using C1, gas and ultraviolet light, InAl
For example, the As layer is more difficult to be etched than the InC; aAsJi layer in the chamber 10 of the etching apparatus shown in FIG.
A small amount of oxygen gas exists in the InAlAs layer of AI (
aluminum atoms) to form an aluminum oxide film on the surface of the InAlAs layer, and the aluminum oxide film causes CI□
This is thought to be to prevent enching by gas.

The etching characteristics in Fig. 3 show the etching characteristics in the case of dry etching using CI□ gas and ultraviolet rays, but dry etching is performed using C12 gas and plasma etc. without using ultraviolet rays. The same applies to the case. Also, InAlAs layer is replaced by InA layer.
Even if an IGaAs layer is used, the aluminum atoms in the InAlGaAs layer react with oxygen gas to form an aluminum oxide film on the surface of the InAlGaAs layer.
The layer will be more difficult to warmly etch than the InGaAs layer.

As described above, the method for manufacturing a heterojunction semiconductor device of the present invention includes an InC;aAs layer and an InAlAs layer or a HnC;
In a heterojunction semiconductor device having a heterojunction with the AIGAs layer, In is etched with a gas containing chlorine to the heterojunction.
The GaAs layer is etched to form an InAlAs layer or an In
Etching is stopped at the surface of the AlGaAs layer, and selective etching of the heterojunction is performed with high precision.

FIG. 4 is a cross-sectional view showing each element manufactured by the method for manufacturing a heterojunction semiconductor device of the present invention, and FIG. 4(a)
indicates a HEMT element.

As shown in FIG. 4(a), the HEMT element is fabricated on a 1-InP substrate 2 by a conventional method such as the MBE method.
1, undoped InGaAs with a thickness of 3000 nm
Buffer 22, non-doped, 1-1 thickness of 1000 people
nGaAS layer 23, doping amount is 5 X I Q 17c
n-1n AIAs layer 24 with a thickness of 1000 m and a doping amount of 2×1 O111CI11-3 and a thickness of 2
Next, resist layers 20 are formed on both sides of the n''-1 nGaAs layer 25, and dry etching is performed using C1□ gas. By this dry etching using C1□ gas, a predetermined portion of the n"-InGaAs layer 25 is etched. However, the etching of the n-1n AIAs layer 24 stops at its surface, and
Selective etching of the As layer 25 and the n-1n AIAs layer 24 is performed with high precision. This allows HE
The dark voltage of the MT element can be stabilized as designed and manufactured.

FIG. 4(b) shows a RHET element.

As shown in FIG. 4(b), for example, by a conventional method such as the MBE method, a doping amount of I x 1019 cm-3 and a thickness of 3000 n
-InGaAs layer 32, non-doped 1-1n AIGaAs layer 33 with a thickness of 2000 nm, doping amount 1×IQ”
an n-InGaAs layer 34 with a thickness of 500 cm-';
Non-doped 1-1n AIAS layer 35a with a thickness of 30 people
, an undoped 1-1 nGaAs layer 36 with a thickness of 30 nm.
, a non-doped i-InAlAs layer 35 with a thickness of 30 nm.
An n'''-1n GaAs layer 37 having an As doping amount of 1.times.10I9Cfll-'' and a thickness of 2000 layers is successively formed. Furthermore, a resist layer 30 is formed on the upper center of the n.-InGaAs layer 37, and dry etching is performed using C1° gas. By this dry etching using CL gas, a predetermined portion of the n''-1n GaAs layer 37 is etched.
Etching of the IA 5 layer 35b stops at its surface,
n”-InGaAs layer 37 and 1-1nAIAs layer 35b
Selective etching can be performed with high precision.

In this way, since the 1-1n AIAs layer 35b is not over-etched, the base resistance does not increase, the operating speed does not decrease, or the frequency characteristics do not deteriorate, and the yield can be improved.

FIG. 4(C) shows an inversion type RBT element.

As shown in FIG. 4(C), for example, a doping amount of l is applied onto an InP substrate 41 by a conventional method such as the MBE method.
X I Q "am-' and thickness of 2000 people n+-
InGaAs layer 42, doping amount is 5×10I7cIn-
n-1n AIGaAs layer 43 with a thickness of 3 and 1000,
Non-doped 1-InAIAs layer 44a with a thickness of 20 nm
1 undoped and 30mm thick InGaAs layer 4
5. Non-doped 1-1n AIAs layer 4 with a thickness of 20 people
4b, doping amount I x 1019 cm-' and thickness 1
000 μm p” I nGaAs layer 46, 30 μm thick n”-InAIAsnGaAs layer 4 which is a stopper.
6 quantity is l X I Q 17cm-” and thickness is 3000
(7) n-I nGaAs layer 48 and doping amount l
Xl019c11-” with a thickness of 3000 people n”-I
An nGaAs layer 49 is sequentially formed. Furthermore, n”-In
A resist layer 40 is formed on the upper center of the GaAs layer 49,
Then, dry etching is performed using CI2 gas. By dry etching using this C12 gas,
n''-InGaAs layer 49 and n-1nGaAs layer 4
8 predetermined locations are etched.

However, the n′″-1nA I As layer 4 which is a stopper
7, etching stops on the surface, and n-1nGaAS
Etching of the layer 48 and the n'' InAlAsnGaAs layer 46 is performed with high precision. This allows for improved yield.

As mentioned above, the HE shown in Fig. 4 (a), (b) and (C)
The MT element, the RHET element, and the inverted RBT element are each coated with a resist 20. Resist 30 and resist 40 are removed, electrodes are formed at predetermined portions, and each element is manufactured.

In the above embodiments, the method for manufacturing a heterojunction semiconductor device of the present invention is described for manufacturing a HEMT element, a RHET element, and an inverted RBT element.
Needless to say, the present invention can be applied to a heterojunction semiconductor device having a heterojunction with an As layer or an InAlGaAs layer.

〔Effect of the invention〕

As described above in detail, the method for manufacturing a semiconductor device according to the present invention includes etching the heterojunction with a gas containing chlorine, etching the indium, aluminum, arsenic layer, and etching the indium, aluminum, arsenic layer. Etching is stopped at the surface of the indium, aluminum, gallium, and arsenic layer, and selective etching of the heterojunction can be performed with high precision.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the principle of the method for manufacturing a heterojunction semiconductor device according to the present invention, FIG. 2 is a diagram schematically showing an etching apparatus to which the method for manufacturing a heterojunction semiconductor device according to the invention is applied, and FIG. 4 is a diagram showing the etching characteristics of each layer etched by the method for manufacturing a heterojunction semiconductor device of the present invention; FIG. 4 is a sectional view showing each element manufactured by the method for manufacturing a heterojunction semiconductor device of the present invention; FIG. 5 is a sectional view showing a HEMT element manufactured by a conventional method, and FIG. 6 is a sectional view showing a RHET element manufactured by a conventional method. (Explanation of symbols) 1... Indium-gallium-arsenic layer, 2... Indium-aluminum-arsenic layer or indium-aluminum-gallium-arsenic layer, 3... Heterojunction.

Claims (1)

[Claims] 1. Heterojunction (3) between an indium-gallium-arsenic layer (1) and an indium-aluminum-arsenic layer (2)
A method for manufacturing a heterojunction semiconductor device having the steps of: etching the heterojunction (3) with a gas containing chlorine;
A method for manufacturing a heterojunction semiconductor device, characterized in that the arsenic layer (1) is etched and the etching is stopped at the surface (2a) of the indium-aluminum-arsenic layer (2). 2. A method for manufacturing a heterojunction semiconductor device having a heterojunction (3) of an indium-gallium-arsenide layer (1) and an indium-aluminum-gallium-arsenide layer (2), the method comprising: ) by etching with a chlorine-containing gas, the indium, gallium,
A method for manufacturing a heterojunction semiconductor device, characterized in that the arsenic layer (1) is etched and the etching is stopped at the surface (2a) of the indium-aluminum-gallium-arsenic layer (2).