JPS63200549A - Integrated circuit package - Google Patents
Integrated circuit packageInfo
- Publication number
- JPS63200549A JPS63200549A JP62033953A JP3395387A JPS63200549A JP S63200549 A JPS63200549 A JP S63200549A JP 62033953 A JP62033953 A JP 62033953A JP 3395387 A JP3395387 A JP 3395387A JP S63200549 A JPS63200549 A JP S63200549A
- Authority
- JP
- Japan
- Prior art keywords
- package
- main body
- base
- screw
- pedestal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003780 insertion Methods 0.000 claims abstract description 3
- 230000037431 insertion Effects 0.000 claims abstract description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 16
- 238000001816 cooling Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 2
- 235000008331 Pinus X rigitaeda Nutrition 0.000 abstract 1
- 235000011613 Pinus brutia Nutrition 0.000 abstract 1
- 241000018646 Pinus brutia Species 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路パッケージの冷却方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of cooling an integrated circuit package.
従来、集積回路パッケージとして各種形状のものが使用
されて来たｙｊＺ、特にディジタル集積回路パッケージ
の場合、多ビン化傾向ならびに高集積化、高速化に比例
して増大する熱を効率よく放熱するなどのために、ピン
・グリッド・アレイ（以降ＰＧＡと略す）タイプのパッ
ケージが多用されつつある。Hitherto, various shapes of YJZ have been used as integrated circuit packages, especially in the case of digital integrated circuit packages, which has a tendency to increase the number of bins, as well as to efficiently dissipate heat, which increases in proportion to higher integration and higher speeds. For this reason, pin grid array (hereinafter abbreviated as PGA) type packages are increasingly being used.
第２図（ａ）は従来のこの棟のＰＧＡタイプパッケージ
の平面図、同図（ｂ）は断面図である。第２図（ａ）。FIG. 2(a) is a plan view of a conventional PGA type package of this type, and FIG. 2(b) is a sectional view. Figure 2(a).
（ｂ）において％ＬＳＩチップ７は、パッケージ本体１
１の上部よりパッケージ内の台座１２に実装さｎ、その
優パッケージ上部のふた１３により封止される。この型
のパッケージＨ，ＬＳＩチップ表面が上向きに実装され
ることから、以降フェースアップ実装型と呼ぶことにす
る。In (b), the %LSI chip 7 is package body 1
1 is mounted on a pedestal 12 in the package from the top, and is sealed by a lid 13 on the top of the package. Since this type of package H is mounted with the LSI chip surface facing upward, it will hereinafter be referred to as a face-up mounting type.
さらに放熱性が要求さｎる場合には、第３区の断面図に
示すパッケージが用いられる。第３因において、これは
第２図のパッケージにおける台座に比べ、台座の位置が
上、下関係が逆になっており、チッ１７はパッケージ本
体２１の底部より実装され、その後ふた２３により封止
さｎる。台座２２はパッケージ本体２１の上部に露出し
ており、ヒートシンク２５は、この台座２２とパッケー
ジ本体２１の上部表面で接続される。この方法によりＬ
ＳＩチップ７で発生した熱は台座２２を介してヒートシ
ンク２５により放熱される。この型のパッケージｉＬｓ
Ｉチップ７の表面が下向きに実やさｎることより、以
降フェースダウン実装型と呼ぶ。フェースダウン実装型
は、特に放熱性を要求する場合に有効であるが、ＬＳＩ
チップの最大サイズがピン５の内側の寸法ＷＫより制限
されるという欠点があった。If further heat dissipation is required, the package shown in the cross-sectional view of section 3 is used. In the third factor, compared to the pedestal in the package shown in FIG. Sanru. The pedestal 22 is exposed at the upper part of the package body 21, and the heat sink 25 is connected to the pedestal 22 at the upper surface of the package body 21. By this method, L
Heat generated by the SI chip 7 is radiated by the heat sink 25 via the pedestal 22. This type of package iLs
Since the surface of the I-chip 7 is oriented downward, it is hereinafter referred to as a face-down mounting type. The face-down mounting type is particularly effective when heat dissipation is required, but
There was a drawback that the maximum size of the chip was limited by the inner dimension WK of the pin 5.
最近ＬＳＩは大型化傾向にあり、発熱量も増大する傾向
にある為、フェースダウン実装型が多用されつつある。Recently, LSIs have tended to become larger and generate more heat, so face-down mounting types are increasingly being used.
しかしながら、前述の制限により、チップサイズがリー
ドピンの配置により制限されることから、チップの大型
化が難しく、この為、フェースダウン実装型のメリット
ヲ生かすことが難しくなりつつある。However, due to the above-mentioned limitations, the chip size is limited by the arrangement of lead pins, making it difficult to increase the size of the chip, and therefore making it difficult to take advantage of the advantages of the face-down mounting type.
本発明は、フェースアップ実装を採用しつつ、ＬＳＩチ
ップの搭載される台座をパッケージの底部に露出させ、
そこにねじ大全形成し、一方ヒー、トシンク部も前記ね
じ穴に合うねじ全形成し、パッケージならびにヒートシ
ンクをパッケージが搭載される基板を間にして接続する
ことにより上記問題の解決をはかるものである。The present invention employs face-up mounting while exposing the pedestal on which the LSI chip is mounted at the bottom of the package.
The above problem is solved by fully forming a screw there, and also forming a fully screwed screw that fits the screw hole in the heat sink part, and connecting the package and heat sink with the board on which the package is mounted in between. .
つぎに本発明全実施例により説明する。 Next, all embodiments of the present invention will be explained.
第１図に本発明の一実施例をプリント基板に実装した状
態を示す断面図である。第１図において、パッケージ本
体１の内部底面に、下面中心部に外方に突出した突出部
２ａｉもつ台座２が、突出部２ａをパッケージ本体１の
外部底面に露出した形に固着されている。パッケージ本
体１の上部開口からパッケージ内の台座２の上にＬＳＩ
チップ７が固着され、ふた３でふたをして内部が気密に
封〈シ
止さ扛ている。このように、内部ＬＳＩチップ７を収納
したパッケージ本体部ニ、リードピン４をプリント基板
８のピン挿入穴に挿入して取付けた後、中心部にねじ５
ａが突出して設けられており、これケバッケージ本体部
の台座２の突出部２ａに設けら扛ているねじ穴にねじ込
み、ヒートシンク５をパッケージ本体部の台座２に固く
固定し、パッケージの実装が終る。FIG. 1 is a sectional view showing an embodiment of the present invention mounted on a printed circuit board. In FIG. 1, a pedestal 2 having an outwardly projecting protrusion 2ai at the center of the lower surface is fixed to the inner bottom surface of the package body 1, with the protrusion 2a exposed at the outer bottom surface of the package body 1. The LSI is placed from the upper opening of the package body 1 onto the pedestal 2 inside the package.
The chip 7 is fixed, and the inside is hermetically sealed with a lid 3. In this way, after inserting the lead pin 4 into the pin insertion hole of the printed circuit board 8 and attaching it to the package body part 2 containing the internal LSI chip 7, screw the screw 5 into the center part.
A is provided protrudingly, and this is screwed into the screw hole provided in the protrusion 2a of the pedestal 2 of the package main body, and the heat sink 5 is firmly fixed to the pedestal 2 of the package main body, and the package mounting is completed. .
このように本発明のパッケージでは、ＬＳＩチップ７の
寸法に、リードピン４の位置の制限を受けず、年にパッ
ケージ本体１の大きさで犬まる寸法までチップを大形化
することが可能となる。また、基本的には、プリント基
板全問にしての両面実装となるため、高密度実装が可能
となり、フェースダウンタイプのＰＧＡでありながら、
多ビン構成も可能となり、ＰＧＡの利点全充分生かすこ
とができる。In this way, in the package of the present invention, the size of the LSI chip 7 is not limited by the position of the lead pins 4, and it is possible to increase the size of the chip to the size of the package body 1 in a year. . In addition, since it is basically double-sided mounting on the entire printed circuit board, high-density mounting is possible, and even though it is a face-down type PGA,
A multi-bin configuration is also possible, and all the advantages of PGA can be fully utilized.
以上説明したように、不発明は、特にフェースアップ実
装型のＰＧＡパッケージであり、ＬＳＩチップの搭載さ
れる台座をパッケージの底部に露出させ、一部にねじ穴
を形成し、このパッケージが実装される基板を間にして
、上記ねじ穴に結合するねじ部を持つヒートシンクと接
続することでフェースアップ構造でありながら効率の良
い冷却が可能となる。As explained above, the invention is particularly a face-up mounting type PGA package, in which the pedestal on which the LSI chip is mounted is exposed at the bottom of the package, a screw hole is formed in a part, and this package is mounted. By connecting a heat sink with a screw portion that connects to the screw hole with a substrate in between, efficient cooling is possible despite the face-up structure.
第１図は本発明の一実施例をプリント基板に実装した状
態上水す断面図、第２図（ａ） 、 （ｂ）は従来の７
工−スアツプ実装型集積回路パッケージの平面図および
断面図、第３図は従来のフェースダウン実装型集積回路
パッケージの断面図である。
１．１１．２１・・・・・・パッケージ本体、２．１２
゜２２・・・・・・台座、２ａ・・・・・・台座の突出
部、３，１３゜２３・・・・・・ふた、４・・・・・・
リードピン、５．２５・・・・・・ヒートシンク、５ａ
・・・・・・ヒートシンクのねじ。Figure 1 is a cross-sectional view of one embodiment of the present invention mounted on a printed circuit board, and Figures 2 (a) and (b) are the conventional 7
A plan view and a sectional view of a factory-fabricated integrated circuit package. FIG. 3 is a sectional view of a conventional face-down integrated circuit package. 1.11.21...Package body, 2.12
゜22...Pedestal, 2a...Protrusion of pedestal, 3,13゜23...Lid, 4...
Lead pin, 5.25...Heat sink, 5a
...Heat sink screw.
Claims (1)
収納し、前記パッケージ本体の下面から外部に突出して
いる多数のリードピンをプリント基板のリードピン挿入
穴に挿入し実装するタイプのピングリッドアレイタイプ
のパッケージであって、前記チップの固着される台座の
一部が前記パッケージ本体の下面に突出露出されて設け
られ、さらに、中心部にねじを有するヒートシンクが、
該ねじを前記パッケージ本体の台座突出部に設けられて
いるねじ穴にねじ込み前記台座に取付けられることを特
徴とする集積回路パッケージ。This is a pin grid array type package in which an integrated circuit chip is housed inside through an opening on the top surface of the package body, and is mounted by inserting a large number of lead pins protruding outside from the bottom surface of the package body into lead pin insertion holes on a printed circuit board. A part of the pedestal to which the chip is fixed is provided to protrude and be exposed on the lower surface of the package body, and further a heat sink having a screw in the center,
An integrated circuit package characterized in that the integrated circuit package is attached to the pedestal by screwing the screw into a screw hole provided in a pedestal protrusion of the package body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62033953A JPS63200549A (en) | 1987-02-16 | 1987-02-16 | Integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62033953A JPS63200549A (en) | 1987-02-16 | 1987-02-16 | Integrated circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63200549A true JPS63200549A (en) | 1988-08-18 |
Family
ID=12400857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62033953A Pending JPS63200549A (en) | 1987-02-16 | 1987-02-16 | Integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63200549A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5216283A (en) * | 1990-05-03 | 1993-06-01 | Motorola, Inc. | Semiconductor device having an insertable heat sink and method for mounting the same |
| US6023413A (en) * | 1997-02-03 | 2000-02-08 | Nec Corporation | Cooling structure for multi-chip module |
-
1987
- 1987-02-16 JP JP62033953A patent/JPS63200549A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5216283A (en) * | 1990-05-03 | 1993-06-01 | Motorola, Inc. | Semiconductor device having an insertable heat sink and method for mounting the same |
| US6023413A (en) * | 1997-02-03 | 2000-02-08 | Nec Corporation | Cooling structure for multi-chip module |
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