JPS63196954A - Information processor - Google Patents

Abstract

PURPOSE:To measure without an error the number of times of execution of a part (instruction code, etc.) of an instruction word by providing an inserting instruction register, an address subordinate register, an insertion timing control circuit, an instruction buffer and an executing instruction register, etc. CONSTITUTION:An instruction code, etc., for reading out the contents of an operand address, adding '1' and storing them in the same operand address are set to an inserting instruction register 1. Also, a part (an instruction code and an addressing mode part) of an executed instruction word on a program is set to an address subordinate register 4. Moreover, an insertion timing control circuit 5 executes a timing control so as to set alternately an instruction word from an instruction buffer 10 and instruction words from the register 1 and the register 4, to an executing instruction register 20. Accordingly, when a selecting and designating register 2 designates an instruction code, and sets a start address of an area for counting the number of times of execution of each separate instruction with respect to an address upper digit of the inside of the register 1, the number of times of execution is counted on a memory, and the number of times of execution can be measured without an error through the memory.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an information processing bag WtK. Measurement of the number of executions of each type of instruction word that is executed [Related].

(Prior art) Regarding instructions executed in various programs, the number of executions for each instruction code and the number of executions for each address modification type are important data for evaluating computer performance. Measured using a hardware monitor. The number of executions is measured by the hardware monitor by inputting a signal representing an executed command to the hardware monitor and counting the number of executions for each type of command.

(While the invention is trying to solve the problem @a) In the above-mentioned prior art, measurement using a computer hardware monitor involves drawing out a signal representing a command word to the outside of the computer,
It is necessary to connect to a hardware monitor. However, with the recent increase in the degree of integration and speed of semiconductor devices, it is difficult to extract the internal signals of a computer to the outside of the device.

Also, when counting the number of executions for each instruction code using the hardware monitor, the number of executions depends on the processing speed of the computer under test and the controller air monitor. You can ask for it.

However, in this case, there is a drawback that normally only a count of 1 @ sampling can be obtained for several hundred instructions. Furthermore, measurement by sampling has the disadvantage that the frequency of execution of an instruction that is executed less often has a larger error.

The purpose of the present invention is to insert an instruction that adds 1 to a memory address every time one instruction on a program is executed, and to decorate the operand address of the inserted instruction with the instruction word on the program that was executed immediately before. It is therefore an object of the present invention to provide an information processing apparatus configured to eliminate the above drawbacks and measure the number of executions without error.

(Top Means for Solving Problems) An information processing device according to the present invention includes insertion instruction register means,
The computer is equipped with address modification means and is configured to be able to execute a program.

The insertion instruction register means is for inserting an insertion instruction that adds 1 to a memory address when one instruction on the program is executed.

The address modification means is for modifying the operand address of the insertion instruction with an instruction word on the program executed immediately before.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 111 is a block diagram showing an embodiment of an information processing device according to the present invention.

81, 10 is an instruction buffer, 2G is an execution instruction register, 1 is an insertion instruction register, -2 is a selection designation register, 3 is a selection circuit, 4 is an address lower register, and S is an insertion timing control circuit.

In FIG. 1, when only instructions on a program are executed, the instructions in the instruction buffer 1o are sequentially set in the execution instruction register 2o and executed. In FIG. 1, insert command register 1 contains AO8 (Add one
(to storage) instruction code and the upper digits of the instruction operand address are set. A.O.
The 8-instruction is an instruction that reads the contents of an operand address, adds 1, and stores the result at the same operand address. A
The lower digits of the operand address of the O8 instruction are supplied from address lower register 4 in FIG.

A part of the executed instruction word (instruction code and addressing mode part) on the program is set in the address lower register 4 as follows. Selection designation register 2 represents the pit to be selected in the instruction word. The selection circuit 3 extracts the pit designated by the selection designation register 2 from the nine command words read from the execution command register 20, and sets it in the address lower register 4. The insertion timing control circuit S receives the instruction word from the instruction buffer 1o, the insertion instruction register 1, and the address lower register 4.
Timing control is carried out so that the instruction words from and to the execution instruction register 20 are set alternately.

When the selection specification register 2 specifies the instruction code and the upper digit of the internal address of the insertion instruction register 1 (for which the start address of the area that counts the number of executions of each instruction is set),
The number of executions of each instruction code of the program being executed is counted on the memory as (start address)+(instruction code). After the execution of the program is completed, the number of executions of each instruction code executed in the program can be obtained by looking at the memory t.

(Effects of the Invention) As explained above, the present invention is capable of adding 1 to a memory address having an operand address modified by a part of the executed instruction word when one instruction on a program is executed. By inserting and executing each instruction word, it is possible to count the number of times a part of an instruction word (instruction code, etc.) is executed for each code.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of information processing *gt according to the present invention. 1...-Insertion instruction register 2...-Selection specification register 3...Selection circuit 4...Address lower register S...Insertion timing control circuit 10...Instruction buffer 20...Fist execution instruction register

Claims (1)

[Claims] an insertion instruction register means for inserting an insertion instruction that adds 1 to a memory address each time one instruction on the program is executed; and an operand address of the insertion instruction is modified with an instruction word on the program executed immediately before. What is claimed is: 1. An information processing device configured to include address modification means for executing a program.