JPS63195582A - Test circuit for lsi internal circuit - Google Patents

Abstract

PURPOSE:To add a test circuit automatically by replacing an existent pin with a two-way pin and utilizing it as test data input and output pins, and adding the test circuit. CONSTITUTION:When a test is conducted, the input test pin 4 and output test pin 5 are both held at '1' to place a two-way buffer 21 for test data input in an input mode and two-way buffer 22 for test data output in an output mode. Here, data inputted from the two-way pin 19 for test data input is inputted to the TD pin of a FF 23 through the buffer 21 and latched at the rise of the signal of a clock input pin 2, and the signal is further passed through a circuit 12 to be tested, latched by a FF 24 at the next rise of the input pin 2, and outputted from the TQ pin. Then the data is outputted from the two-way pin 20 for test data output through the buffer 22. Thus, the test circuit is added automatically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field J] The present invention relates to testing of internal circuits of LSIs.

[Prior Art J] Figure 5 is a diagram showing, for example, a conventional LSI internal circuit test circuit. In the figure, (1) is a data input pin;
(2) H clock input pin, (3) H test data input pin, (4) input test pin, (5) output test pin, (6) Fi data output pin, (71 test data output pin, (8 )Fi input pad 7a, (su) is output buffer, (10) (11) Selector where Y=A when J-t S -= 0, Y=B when S!=1, (12
) is the internal circuit under test, (13) Fi is the 7-limp flop just before the circuit under test (11), (14) d is the 7-limp flop after i of the circuit under test, (15) #: t flip-flop (13) Internal circuit in front of (16) #i
Internal circuit after flip-flop (14), (17
)(1g) is an internal circuit.

Next, the operation will be explained. When the system is running.

Both input test pin (4) and output test pin (5) are OK.
The data input from the data input pin (1) passes through the input capacitor 7a (8), the internal circuit (tS), and the selector (10), and becomes a flip-flop at the rising edge of the signal at the tarock input pin (2). (13) kC latched,
Following the circuit under test (12), it is launched at the next rising edge of the clock input pin (2) to the 7-lip front (14), passes through the internal circuit (16), the output buffer (9), and is output to the data output pin (6). ) is output. Also, the data input from the test data input pin is transferred to the internal circuit (
16), and the data of the internal circuit (18) is output to the test data output pin. During testing, both the input test pin (4) and output test pin (5) are set to 1, and the data input from the test data input pin (3) passes through the input buffer (controller) and selector (lO).
At the rising edge of the clock input pin (2), the 7-rip 70 amplifier (13) is launched, and the circuit under test (
12), is launched to the 7-link 7-o pin (14) at the next rising edge of the tarok input pin (2), passes through the selector (11), the output buffer (9), and is output to the test data output pin (7). Ru.

[Problems that Komoe tries to solve] The conventional LSI internal circuit test circuit, as described above,
Since the JT is configured, a test circuit must be added from the system design stage, which makes the circuit complicated, and adding a selector increases the number of gates and changes the creation timing. This invention was made to solve the above problems, and it is possible to automatically add a test circuit after system design, and to suppress the increase in the number of gates. The object of the present invention is to obtain an LSI internal circuit test circuit whose timing hardly changes.

[Means for Solving the Problems] In the L31 internal circuit test circuit according to the present invention, a system-only circuit is first created, and a flip 70 amplifier to which data is to be directly input and its data are inserted into the circuit. Specify the output pin to input the data, and also specify the input pin to output the data of the 7 flip-flop to which you want to directly output the data. and change the buffer connected to the specified input/output pin to a bidirectional buffer,
It is designed to connect signal lines.

[Operation J] The test circuit according to the present invention automatically adds the test circuit Vζ after the system is designed, and there is no need for the system designer I/I to consider the addition of the test circuit at all.

[Embodiments of the invention]

An embodiment of the present invention will be explained below with reference to the drawings.

In Figure 1, (19) Bi-directional pin for Fi test data input, (20) Bi-directional pin for test data output, (21) Fi test data input/next station direction buffer.
(22) bidirectional buffer for outputting test data;
(23) #-i test data input test ν test 7 lip amplifier used for test, (24) #:t test data output test 7 lip amplifier used for test.

Figure 2 shows the test 7-lip 70 amplifier used in Figure 1 (
23) (24), (25) is the system data input pin: D, (26) Hr data input pin: TD
.

(27) #-jri ON input pin: CLK,
(2g) are mode switching pins: TMSC29) u system data output pin: Q, and (30) #-i test data output pin: TQ. This is a blind guide table with the value ÷ 3 + 11 - + - test data 11 pf 0 test, and the system data input pin (25) or the test data input pin (26
) is launched at the rising edge of the clock input pin (27) and output to the system data output pin (4) and the test data output pin (30).

Next, let's discuss the MJ issue. When creating system 11, both the input test pin (4) and output test pin (5) are set to 0, and the input buffer (8) and internal circuit (15) are used to input poor data from the data input pin (1). As shown, the tallock input pin (23) is launched to the 7th lip-flop (23) at the rising edge of Ig15, and the P is launched to the circuit under test (23).
12) km, then 7 on the next rising edge of the tarok input pin
The internal circuit (16)
), through the output buffer (9), to the data output pin (6
) V is output. In addition, the test data input bidirectional buffer becomes the output mode, and the data of the internal circuit (18) is output from the test data input pin, and becomes the test data output bidirectional buffer (22) H1 input pin. The data input from the test data output pin C20) is input to the internal circuit (17).

During testing, input test pin (4), output test pin (
5) Both are set to 1, and the test data input bidirectional buffer (21) is set to input mode, and the test data output buffer (22) is set to output mode. The data input from the test data input bidirectional pin (19) passes through the test data input bidirectional buffer (21), is input to the TD upper pin of the 7 limb 70 amplifier (23), and is input to the rear input pin ( It is latched at the rising edge of the signal 2), further traces the circuit under test (12), is latched by the flip-flop (24) at the next rising edge of the tarock input pin (2), is output from the TQ pin, and is used for test data output. Bidirectional buffer (22) km Output from the retest data output bidirectional pin (20).

Further, in the above embodiment, one test data input bidirectional buffer is connected to one test 7 rib 7a tube, but a mantissa test flip 70 tube may be connected to the test data input bidirectional buffer. The same effects as in the embodiment are achieved.

The procedure for adding test circuits has regularity and can be added automatically. FIG. 4 shows a flowchart for adding an automatic test circuit. In Figure 4, (:jl)
Logic connection information before adding the test circuit, (32) #-j Correspondence table of flip-flops and pins to which you want to directly input and output data, (33), (34), and (35) are processing, (36)
is the logical connection information of the test circuit addition modification.

Next, the procedure for adding a test circuit will be explained. First, in process (33), the flip-flop specified by the 7-lip flop and pin pair 16 (32) in the logical connection information (31) is changed to a 7-lip flop for testing. Next, in process (34), the buffer connected to the pin specified in the flip-flop and pin correspondence table (32) in the logical connection information (31) is changed to a bidirectional pants pattern. ), connect the changed 7-ring 7'70 panel, bidirectional pan 7-a, and test pin, and output the logical connection information after adding the test circuit.

[Effects of the Invention] As mentioned above - C1 According to this invention, the existing pins are changed to bidirectional pins and used as test data input/output pins, and a test circuit is added, so that the system design can be completed easily. After R, the test circuit can be added only by adding two test pins, and the procedure for adding a further test circuit has much regularity, which has the effect of automatically adding a 1ζ test circuit. .

[Brief explanation of the drawing]

FIG. 1 is a test circuit diagram of an LSI internal circuit according to an embodiment of the present invention, FIG. 2 is a test flip-flop of a test circuit according to an embodiment of the present invention, and the third quotient is the truth #ip of a test clip-prop. , FIG. 4 is a flowchart for adding the first test circuit, and FIG. 5 is a circuit diagram according to a conventional LSI internal circuit testing method. As shown in the figure, (IJ data input pin, Q) is tarokku input pin, (3J H test data input pin,
(4) H input test pin, (S) Fi output test pin, (6) data output pin, (7) test data output pin, (8) input bag 7A, (9) output bag 7A. ,
(10) (11) is a selector, (12) is an internal circuit under test, (13) (14) is a 7-lip tube, (1
5) (16) (17) (18) are internal times! 1p1
．． (19) is a bidirectional pin for test data input, (2
0) is a bidirectional pin for test data output, (21) (2
2) I″i two-way Kutufa, (23) (24)
test flip 7a tab, (25) HD pin, (2
6) Put TD top pin (27) put CLK pin, (28) is T
M pin, (29) Q pin, (30) T Q pin,
(31) is the logical connection information before adding the test circuit, (32)
is the correspondence table of flip 70 knobs and pins, (33) (
34) Cooking connection information after (35) ri processing and (36) addition of test circuit. In addition, in the figures, the same or equivalent parts are shown. Agent Masuo Oiwa Diagram 2 Zσ Diagram 3 X: 1 Shiri Diagram 4

Claims (2)

[Claims] (1) Change the flip-flop to which you want to input/output data directly from outside the LSI to a test flip-flop, change the existing output pins and input pins to bidirectional pins, and use the existing output pins as test data input pins during testing. 1. A test circuit for an internal circuit of an LSI, which uses an existing input pin as a test data output pin, and switches between system operation and test operation using an input pin from outside the LSI. (2) A test circuit for an LSI internal circuit according to claim 1, wherein the test circuit is automatically added.