JPS63193273A - Designing device for integrated circuit logic - Google Patents

Abstract

PURPOSE:To decrease the man-hours of circuit optimization by operators and to prevent a miss from being generated by equipping an integrated circuit logic designing device with a circuit optimizing device for an integrated circuit. CONSTITUTION:The circuit optimizing device 1 which optimizes the circuit is connected to a controller 2 which controls the whole of the integrated circuit logic designing device and the optimization rule for the integrated circuit is stored in a circuit condition storage device 3. Further, a logic macroinput device 7 connected to the controller 2 outputs a basic logic symbol circuit diagram from a logic macrocircuit. Further, a logic macrostorage device 4, a logic symbol storage device 5, a temporary storage device 6, a logic macrooverlap elimination arithmetic unit 8, a logic macroexpansion arithmetic unit, etc., are connected to the controller 2. Then a redundant circuit deleting mechanism 15, a converting mechanism 16 for conversion from a basic element to a composite element, and an adjusting mechanism 17 for the inside of the circuit are arranged on the controller 2, and the integrated circuit is optimized by the optimizing device 1 under the control of the controller 2 to eliminate operator's processes, thereby preventing a miss from being generated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an integrated circuit logic design device, and in particular,
The present invention relates to a circuit design device using logic macros at the SI and LSI levels.

[Conventional technology]

2. Description of the Related Art Conventionally, as a device for designing large-scale integrated circuits (LSI), there is an integrated circuit logic design apparatus that receives a logic macro circuit diagram as input and outputs a basic logic symbol circuit diagram.

[Problem that the invention seeks to solve]

The conventional logic design device described above receives a logic circuit diagram using a logic macro as input and creates a logic symbol circuit diagram of an integrated circuit. In the case of master slice type LSI design, circuit optimization such as load adjustment and conversion to complex logic gates to reduce the number of gates depends on the operator, so human errors and circuit design can occur. The disadvantage is that it requires a lot of man-hours.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit logic design apparatus that eliminates such conventional drawbacks and reduces the occurrence of errors and the number of steps required by the operator.

[Means for solving problems]

The integrated circuit logic design device of the present invention includes a logic operation device that outputs a logic symbol circuit diagram from a logic macro circuit diagram; and a logic operation device that outputs a logic symbol circuit diagram from a logic macro circuit diagram; a circuit condition storage unit that stores conversion rules to complex logic symbols; a circuit deletion means for deleting redundant circuits that have empty input or output terminals of the logic circuit; and circuit optimization according to the storage conditions of the circuit condition storage unit. circuit conversion means for converting the
A circuit optimization device including a load adjustment means for detecting the load state from the connection conditions of each circuit and adjusting the load; and a temporary storage device for temporarily storing the output of the circuit optimization device. do.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

This device consists of a circuit optimization device 1 that performs circuit f&optimization, and circuit conditions (optimization) that store optimization rules for integrated circuits.
A storage device 3, a logic macro input device 7 that outputs a basic logic symbol circuit diagram from a logic macro circuit diagram, a logic macro overlap resolution calculation device 8, a logic macro expansion calculation device, and a logic symbol wiring calculation device 10. , a logic symbol circuit diagram output device 11, a logic macro storage device 4, a logic symbol storage device 5, a temporary storage device 6, and a control device 2 that controls each of these devices.

As shown in FIG. 4, FIG. 5, or FIG. 6, the circuit condition storage device 3 stores conversion rules for logic symbols into other logic symbols depending on the input/input field states, and inverter as a keyword. It stores rules for converting logical symbols into other logical symbols and rules for converting a combination of two-stage logical symbols into a composite logical symbol having the same function.

The circuit optimization device 1 operates with the configuration shown in the block diagram shown in FIG. The connection information between logical symbols held in the temporary storage device 6 which stores the calculation results of the logical macro expansion device 9, the functions of the logical symbols stored in the logical symbol storage device 5, and the fan and terminal of each terminal of the logical symbols. Based on the circuit optimization storage 3 storing out, fan-in values and circuit optimization rules, the redundant circuit removal mechanism 15 is first implemented.
Next, the basic logic element to complex logic element conversion mechanism 16 converts the redundant circuit to a complex logic element, and finally the load adjustment mechanism 17 inside the integrated circuit adjusts the load inside the integrated circuit. The calculation results are stored in the temporary storage device 6.

As shown in FIG. 3, the redundant circuit deletion mechanism 15 of the circuit optimization device 1 deletes a symbol whose output terminals are all empty terminals (outputs a NANDAND circuit and removes the logic symbol from the symbol) based on the terminal usage state of the logic symbol. Delete from temporary storage device 6,
The connection information of the deleted symbol is also released. The above calculations are performed until the target logical symbol is no longer detected on the temporary storage device 6. Next, empty input terminals of logic symbols are detected, symbols whose input terminals are all empty are deleted, and connection information is released. Other information is stored in the circuit optimization storage device 3, as shown in Fig. 4, so that when the input state of the inverter is determined, the output is determined, and when the single-handed power of an N-input circuit is determined, the circuit becomes an N-1 human-powered circuit. Replaces and deletes logical symbols according to the specified conversion rules.

The above calculations are performed until the target logical symbol is no longer detected on the temporary storage device 6.

Furthermore, as shown in FIG. 5, logic symbols are deleted and replaced according to the conversion rules using the inverter stored in the circuit optimization storage device 3, such as a NANDAND circuit, as a keyword, so that the AND circuit and the inverter become the target. Operations are performed until no combination of logical symbols is detected on the temporary storage device 6.

As shown in FIG. 6, the conversion mechanism 16 from a basic logic element to a complex logic element converts conversion rules stored in the circuit optimization storage device 3, for example, an AND circuit and a NOR circuit into one logic circuit. According to such rules, combinations of symbols that can be converted using the target symbol as a keyword are detected on the temporary storage device 6, and conversion is performed. This conversion is also performed until the target combination of logical symbols is no longer detected on the temporary storage device 6.

A load adjustment mechanism 17 inside the integrated circuit stores connection information between logical symbols stored in the temporary storage device 6 and fan-out and fan-in information of each terminal of the logical symbols stored in the logical symbol storage device 5. Based on the value, the load state is detected for each net, and if the load is excessive, a logic symbol with a driving capacity corresponding to the load is detected from the logic symbol storage device 5 and inserted for the target net. . If the load is too low, the logic symbol storage device 5 stores a logic symbol with the same function and a drive capacity corresponding to the load.
1. Then, the symbol of the target net is replaced. This replacement is also performed until the target net is no longer detected in the temporary storage device 6.

〔Effect of the invention〕

As explained above, the present invention reduces the number of man-hours for circuit optimization, which conventionally relied on human labor, by equipping an integrated circuit logic design device with a circuit optimization device for integrated circuits.
This has the effect of shortening the process and preventing human errors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A block diagram of an example of the circuit optimization device shown in Fig. 3 is shown in Fig. 1.
A circuit diagram showing an example of the operation of the redundant circuit deletion mechanism shown in FIG. 4,
5 and 6 are circuit diagrams showing an example of the operation of the conversion rules stored in the circuit optimization storage device 3 of FIG. 1. 1...Circuit optimization device, 2...Control device, 3...
circuit condition storage device, 4... logic macro storage device, 5.
...Logical symbol storage device, 6...Temporary storage device, 7
...Logic macro input device, 8...Logic macro overlap resolution calculation device, 9...Logic macro expansion calculation device, 10
...Logic symbol wiring calculation device, 11...Logic symbol circuit diagram output device, 15...Redundant circuit deletion mechanism,
16... Conversion mechanism from basic element to composite element, 17.
...Load adjustment mechanism inside the circuit.

Claims (1)

[Claims] a logic operation device that outputs a logic symbol circuit diagram from a logic macro circuit diagram; and a logic operation device that stores conversion rules to other logic symbols and conversion rules from a combination of two-stage logic symbols to a composite logic symbol depending on the input state of the logic symbol; a circuit condition storage section; a circuit deletion means for deleting a redundant circuit under an empty condition of an input or output terminal of a logic circuit; and a circuit conversion section for performing circuit optimization conversion according to the storage conditions of the circuit condition storage section. and a circuit optimization device that detects the load state of each circuit from the connection conditions of each circuit and adjusts the load; and a temporary storage device that temporarily stores the output of the circuit optimization device. Features of integrated circuit logic design equipment.