JPS63193273A - Designing device for integrated circuit logic - Google Patents
Designing device for integrated circuit logicInfo
- Publication number
- JPS63193273A JPS63193273A JP62026602A JP2660287A JPS63193273A JP S63193273 A JPS63193273 A JP S63193273A JP 62026602 A JP62026602 A JP 62026602A JP 2660287 A JP2660287 A JP 2660287A JP S63193273 A JPS63193273 A JP S63193273A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- logic
- integrated circuit
- symbol
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005457 optimization Methods 0.000 claims abstract description 25
- 238000010586 diagram Methods 0.000 claims abstract description 22
- 238000006243 chemical reaction Methods 0.000 claims abstract description 18
- 239000002131 composite material Substances 0.000 claims abstract description 4
- 238000012217 deletion Methods 0.000 claims description 5
- 230000037430 deletion Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 2
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路論理設計装置に関し、特にSSI、M
SI、LSIレベルの論理マクロを用いた回路設計装置
に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an integrated circuit logic design device, and in particular,
The present invention relates to a circuit design device using logic macros at the SI and LSI levels.
従来、大規模な集積回路(LSI)を設計するものとし
ては、論理マクロ回路図を入力とし、基本論理シンボル
回路図を出力する集積回路論理設計装置がある。2. Description of the Related Art Conventionally, as a device for designing large-scale integrated circuits (LSI), there is an integrated circuit logic design apparatus that receives a logic macro circuit diagram as input and outputs a basic logic symbol circuit diagram.
上述した従来の論理設計装置は、論理マクロを用いた論
理回路図を入力とし、集積回路の論理シンボル回路図を
作成するが、論理マクロ内で使用していない論理シンボ
ルの削除、集積回路内部の負荷調整、またマスタースラ
イス方式LSIの設計の場合、ゲート数削減のための複
合論理ゲートへの変換、などの回路最適化が操作者に依
存しているので、人為的なミスの発生や回路設計者の工
数が必要となるという欠点がある。The conventional logic design device described above receives a logic circuit diagram using a logic macro as input and creates a logic symbol circuit diagram of an integrated circuit. In the case of master slice type LSI design, circuit optimization such as load adjustment and conversion to complex logic gates to reduce the number of gates depends on the operator, so human errors and circuit design can occur. The disadvantage is that it requires a lot of man-hours.
本発明の目的は、このような従来の欠点を除き、ミスの
発生や操作者の工数を削減した集積回路論理設計装置を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit logic design apparatus that eliminates such conventional drawbacks and reduces the occurrence of errors and the number of steps required by the operator.
本発明の集積回路論理設計装置は、論理マクロ回路図か
ら論理シンボル回路図を出力する論理演算装置と;前記
論理シンボルの入力状態により他の論理シンボルへの変
換規則および二段論理シンボルの組合せから複合論理シ
ンボルへの変換規則を記憶させた回路条件記憶部と;論
理回路の入力あるいは出力端子の空条件にある冗長回路
を削除する回路削除手段と、前記回路条件記憶部の記憶
条件に従って回路最適化の変換を行う回路変換手段と、
各回路の接続条件からその負荷状態を検出して負荷調整
を行う負荷調整手段とを含む回路最適化装置と;この回
路最適化装置の出力を一時記憶する一時記憶装置とを備
えることを特徴とする。The integrated circuit logic design device of the present invention includes a logic operation device that outputs a logic symbol circuit diagram from a logic macro circuit diagram; and a logic operation device that outputs a logic symbol circuit diagram from a logic macro circuit diagram; a circuit condition storage unit that stores conversion rules to complex logic symbols; a circuit deletion means for deleting redundant circuits that have empty input or output terminals of the logic circuit; and circuit optimization according to the storage conditions of the circuit condition storage unit. circuit conversion means for converting the
A circuit optimization device including a load adjustment means for detecting the load state from the connection conditions of each circuit and adjusting the load; and a temporary storage device for temporarily storing the output of the circuit optimization device. do.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の装置のブロック図である。FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.
本装置は、回路f&適化を行う回路最適化装置1と、集
積回路の最適化規則を格納している回路条件(最適化)
記憶装置3と、論理マクロ回路図から基本論理シンボル
回路図を出力する論理マクロ入力装置7と、論理マク口
重なり解消演算装置8と、論理マクロ展開演算装置つと
、論理シンボル間配線演算装置10と、論理シンボル回
路図出力装置11と、論理マクロ記憶装置4と、論理シ
ボル記憶装置5と、一時記憶装置6と、これらの各装置
を制御する制御装置2とから構成される。This device consists of a circuit optimization device 1 that performs circuit f&optimization, and circuit conditions (optimization) that store optimization rules for integrated circuits.
A storage device 3, a logic macro input device 7 that outputs a basic logic symbol circuit diagram from a logic macro circuit diagram, a logic macro overlap resolution calculation device 8, a logic macro expansion calculation device, and a logic symbol wiring calculation device 10. , a logic symbol circuit diagram output device 11, a logic macro storage device 4, a logic symbol storage device 5, a temporary storage device 6, and a control device 2 that controls each of these devices.
回路条件記憶装置3は、第4図、第5図あるいは第6図
に示すように、論理シンボルの入・力場子の状態による
他の論理シンボルへの変換規則と、・インバータをキー
ワードとした論理シンボルの他の論理シンボルへの変換
規則と、二段構成の論理シンボルの組合せを同一機能を
もつ複合論理シンボルへの変換規則を格納している。As shown in FIG. 4, FIG. 5, or FIG. 6, the circuit condition storage device 3 stores conversion rules for logic symbols into other logic symbols depending on the input/input field states, and inverter as a keyword. It stores rules for converting logical symbols into other logical symbols and rules for converting a combination of two-stage logical symbols into a composite logical symbol having the same function.
回路最適化装置1は、第2図に示すブロック図の構成で
動作を行う。論理マクロ展開装置9の演算結果を格納し
ている一時記憶装置6のもつ論理シンボル間の接続情報
と論理シンボル記憶装置5が格納してい、る論理シンボ
ルの機能、論理シンボルの各端子のファン・アウト、フ
ァン・イン値と回路最適化規則を格納している回路最適
化記憶装置3を基にして、最初に冗長回路削除機構15
で冗長回路の削除を行なう0次に、基本論理素子から複
合論理素子への変換機構16で複合論理素子への変換を
行ない、最後に集積回路内部の負荷調整機構17で集積
回路内部の負荷調整を行ない、その演算結果を一時記憶
装置6へ格納する。The circuit optimization device 1 operates with the configuration shown in the block diagram shown in FIG. The connection information between logical symbols held in the temporary storage device 6 which stores the calculation results of the logical macro expansion device 9, the functions of the logical symbols stored in the logical symbol storage device 5, and the fan and terminal of each terminal of the logical symbols. Based on the circuit optimization storage 3 storing out, fan-in values and circuit optimization rules, the redundant circuit removal mechanism 15 is first implemented.
Next, the basic logic element to complex logic element conversion mechanism 16 converts the redundant circuit to a complex logic element, and finally the load adjustment mechanism 17 inside the integrated circuit adjusts the load inside the integrated circuit. The calculation results are stored in the temporary storage device 6.
回路最適化装置1の冗長回路の削除機構15は、論理シ
ンボルの端子使用状態を基に、第3図に示すように、全
部の出力端子が空端子のシンボル(NANDAND回路
出し、その論理シンボルを一時記憶装置6から削除し、
削除されたシンボルのもつ接続情報も開放する。この対
象となる論理シンボルが一時記憶装置6上で検出されな
くなるまで以上の演算を行なう。次に、論理シンボルの
入力端子の空端子を検出し、入力端子が全部空であるシ
ンボルの削除、接続情報の開放を行なう。その他は、第
4図に示すように、インバータの入力状態が決まれば出
力が決り、N入力回路の一人力が決まれば、N−1人力
の回路となるような回路最適化記憶装置3に格納されて
いる変換規則に従って論理シンボルの置換、削除を行な
う。As shown in FIG. 3, the redundant circuit deletion mechanism 15 of the circuit optimization device 1 deletes a symbol whose output terminals are all empty terminals (outputs a NANDAND circuit and removes the logic symbol from the symbol) based on the terminal usage state of the logic symbol. Delete from temporary storage device 6,
The connection information of the deleted symbol is also released. The above calculations are performed until the target logical symbol is no longer detected on the temporary storage device 6. Next, empty input terminals of logic symbols are detected, symbols whose input terminals are all empty are deleted, and connection information is released. Other information is stored in the circuit optimization storage device 3, as shown in Fig. 4, so that when the input state of the inverter is determined, the output is determined, and when the single-handed power of an N-input circuit is determined, the circuit becomes an N-1 human-powered circuit. Replaces and deletes logical symbols according to the specified conversion rules.
この対象となる論理シンボルが一時記憶装置6上で検出
されなくなるまで以上の演算を行なう。The above calculations are performed until the target logical symbol is no longer detected on the temporary storage device 6.
さらに、第5図に示すように、AND回路とインバータ
がNANDAND回路ような回路最適化記憶装置3に格
納されているインバータをキーワードとして変換規則に
従って、論理シンボルの削除・置換を行ない、対象とな
る論理シンボルの組合せが一時記憶装置6上で検出され
なくなるまで演算を行なう。Furthermore, as shown in FIG. 5, logic symbols are deleted and replaced according to the conversion rules using the inverter stored in the circuit optimization storage device 3, such as a NANDAND circuit, as a keyword, so that the AND circuit and the inverter become the target. Operations are performed until no combination of logical symbols is detected on the temporary storage device 6.
基本論理素子から複合論理素子への変換機構16は、第
6図に示すように、回路最適化記憶装置3に格納されて
いる変換規則、例えばAND回路とNOR回路とを1個
の論理回路とするような規則に従って、対象となるシン
ボルをキーワードとして変換できるシンボルの組合せを
一時記憶装置6上で検出し変換を行なう。この変換も対
象となる論理シンボルの組合せが一時記憶装置6上で検
出されなくなるまで演算を行なう。As shown in FIG. 6, the conversion mechanism 16 from a basic logic element to a complex logic element converts conversion rules stored in the circuit optimization storage device 3, for example, an AND circuit and a NOR circuit into one logic circuit. According to such rules, combinations of symbols that can be converted using the target symbol as a keyword are detected on the temporary storage device 6, and conversion is performed. This conversion is also performed until the target combination of logical symbols is no longer detected on the temporary storage device 6.
集積回路内部の負荷調整機構17は、一時記憶装置6上
に格納されている論理シンボル間の接続情報と論理シン
ボル記憶装置5に格納されている論理シンボルの各端子
のファン・アウト、ファン・イン値を基に、各ネット単
位に負荷の状態を検出し、負荷が過多の場合はその負荷
に応じた駆動能力をもつ論理シンボルを論理シンボル記
憶装置5から検出し、対象となるネットについて挿入す
る。負荷が過少の場合は、その負荷に応じた駆動能力を
もつ同一機能の論理シンボルを論理シンボル記憶装置5
から検出し、対象となるネットのシンボルの置換を行な
う1゜この置換も対象となるネットが一時記憶装置6で
検出されなくなるまで演算を行なう。A load adjustment mechanism 17 inside the integrated circuit stores connection information between logical symbols stored in the temporary storage device 6 and fan-out and fan-in information of each terminal of the logical symbols stored in the logical symbol storage device 5. Based on the value, the load state is detected for each net, and if the load is excessive, a logic symbol with a driving capacity corresponding to the load is detected from the logic symbol storage device 5 and inserted for the target net. . If the load is too low, the logic symbol storage device 5 stores a logic symbol with the same function and a drive capacity corresponding to the load.
1. Then, the symbol of the target net is replaced. This replacement is also performed until the target net is no longer detected in the temporary storage device 6.
以上説明したように本発明は、集積回路の回路最適化装
置を集積回路論理設計装置に備えることにより、従来人
手に依存していた回路最適化の工数を削減、T A T
の短縮、人手ミスを防止できるという効果がある。As explained above, the present invention reduces the number of man-hours for circuit optimization, which conventionally relied on human labor, by equipping an integrated circuit logic design device with a circuit optimization device for integrated circuits.
This has the effect of shortening the process and preventing human errors.
第1図は本発明の一実施例のブロック図、第2図は第1
図の回路最適化装置の一例のブロック図、第3図は第1
図の冗長回路削除機構の動作例を示す回路図、第4図、
第5図および第6図は第1図の回路最適化記憶装置3に
記憶された変換規則の動作例を示す回路図である。
1・・・回路最適化装置、2・・・制御装置、3・・・
回路条件記憶装置、4・・・論理マクロ記憶装置、5・
・・論理シンボル記憶装置、6・・・一時記憶装置、7
・・・論理マクロ入力装置、8・・・論理マク口重なり
解消演算装置、9・・・論理マクロ展開演算装置、10
・・・論理シンボル間配線演算装置、11・・・論理シ
ンボル回路図出力装置、15・・・冗長回路削除機構、
16・・・基本素子から複合素子への変換機構、17・
・・回路内部の負荷調整機構。FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A block diagram of an example of the circuit optimization device shown in Fig. 3 is shown in Fig. 1.
A circuit diagram showing an example of the operation of the redundant circuit deletion mechanism shown in FIG. 4,
5 and 6 are circuit diagrams showing an example of the operation of the conversion rules stored in the circuit optimization storage device 3 of FIG. 1. 1...Circuit optimization device, 2...Control device, 3...
circuit condition storage device, 4... logic macro storage device, 5.
...Logical symbol storage device, 6...Temporary storage device, 7
...Logic macro input device, 8...Logic macro overlap resolution calculation device, 9...Logic macro expansion calculation device, 10
...Logic symbol wiring calculation device, 11...Logic symbol circuit diagram output device, 15...Redundant circuit deletion mechanism,
16... Conversion mechanism from basic element to composite element, 17.
...Load adjustment mechanism inside the circuit.
Claims (1)
理演算装置と;前記論理シンボルの入力状態により他の
論理シンボルへの変換規則および二段論理シンボルの組
合せから複合論理シンボルへの変換規則を記憶させた回
路条件記憶部と;論理回路の入力あるいは出力端子の空
条件にある冗長回路を削除する回路削除手段と、前記回
路条件記憶部の記憶条件に従つて回路最適化の変換を行
う回路変換手段と、各回路の接続条件からその負荷状態
を検出して負荷調整を行う負荷調整手段とを含む回路最
適化装置と;この回路最適化装置の出力を一時記憶する
一時記憶装置とを備えることを特徴とする集積回路論理
設計装置。a logic operation device that outputs a logic symbol circuit diagram from a logic macro circuit diagram; and a logic operation device that stores conversion rules to other logic symbols and conversion rules from a combination of two-stage logic symbols to a composite logic symbol depending on the input state of the logic symbol; a circuit condition storage section; a circuit deletion means for deleting a redundant circuit under an empty condition of an input or output terminal of a logic circuit; and a circuit conversion section for performing circuit optimization conversion according to the storage conditions of the circuit condition storage section. and a circuit optimization device that detects the load state of each circuit from the connection conditions of each circuit and adjusts the load; and a temporary storage device that temporarily stores the output of the circuit optimization device. Features of integrated circuit logic design equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62026602A JPS63193273A (en) | 1987-02-06 | 1987-02-06 | Designing device for integrated circuit logic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62026602A JPS63193273A (en) | 1987-02-06 | 1987-02-06 | Designing device for integrated circuit logic |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63193273A true JPS63193273A (en) | 1988-08-10 |
Family
ID=12198065
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62026602A Pending JPS63193273A (en) | 1987-02-06 | 1987-02-06 | Designing device for integrated circuit logic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63193273A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6188371A (en) * | 1984-07-16 | 1986-05-06 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Logical syntehsization |
-
1987
- 1987-02-06 JP JP62026602A patent/JPS63193273A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6188371A (en) * | 1984-07-16 | 1986-05-06 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Logical syntehsization |
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