JPH0477120A - Variable-length data encoder - Google Patents

Abstract

PURPOSE:To perform the bit shift of a parallel variable-length data in a lump and to efficiently perform the variable-length encoding processing at high speed by providing an accumulation adder accumulating the data length of the parallel variable-length data and a parallel shift circuit parallely bit-shifting the parallel variable-length data with the output of the accumulation adder. CONSTITUTION:Data of L1=8 bits are outputted from a parallel shift circuit 12, and when data of L2=10 are inputted to the parallel shift circuit 12, a bit shift number '8' is transmitted from an accumulation adder 13, and the data of L2=10 bits are outputted from the parallel shift circuit 12. Next, when data of L3=7 bits are inputted to the parallel shift circuit 12, the bit shift number outputted from the accumulation adder 13 goes to '18', the signal indicating the alignment with 16-bit width is transmitted to an alignment circuit 14, and a bit shift number '2' (18-16) is transmitted to the parallel shift circuit 12. Thus, the data of L3=7 bits are outputted from the parallel shift circuit 12 while 2 bit-shifted.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a variable length encoding device.

2. Description of the Related Art Conventionally, as a technique in this field, there has been a technique in which output data is created by shifting one bit at a time in accordance with the focus length of each variable length code data. An example of a conventional variable length encoding device is shown in FIG.

31 is a conversion circuit, 32.35 is a shift register, 33.
36 is a counter, 34 is a controller, 37 is a latch,
38 is parallel variable length data, and 39 is the data length of parallel variable length data.

First, fixed length data is input to the conversion circuit 31. Parallel variable length data 38 and its data length 39 corresponding to this fixed length data are output from the conversion circuit 31 and stored in the soft register 32 and counter 33, respectively. In response to a command from the controller 34, the counter 33 is counted down until the data length loaded into the counter 33 becomes 0. Then, the shift register 32 is shifted bit by bit by the countdown number. Furthermore, the shift register 35 receives and shifts the output. In this case, the number of input data of the shift register 35 is counted by the counter 36, and each time the counter 36 reaches a certain value,
Parallel variable length code data is loaded from the shift register 35 into the latch 37.

Problems to be Solved by the Invention As mentioned above, conventional variable length encoding devices have the problem of shifting variable length code data one bit at a time, which takes time to create the encoding and slows down the processing speed. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable length encoding device that eliminates the above-mentioned problems and can efficiently perform high-speed processing.

Means for Solving the Problems In order to solve the above problems, the present invention provides a conversion circuit that converts fixed length data into parallel variable length data and a data length corresponding to the parallel variable length data; log2N (N is a power of 2) to accumulate the data length of data
a bit accumulator, a parallel shift circuit that bit-shifts the parallel variable length data in parallel using the output of the accumulator, and the output of the parallel shift circuit is sequentially accumulated in a register so that the accumulated bit width is N bits. It is equipped with an alignment circuit that outputs N bits of data when the number exceeds the limit.

According to the present invention, as described above, there is provided a conversion circuit that converts fixed length data into parallel variable length data and a data length corresponding to the parallel variable length data, and a log2N circuit that accumulates the data length of the parallel variable length data. (N is a power of 2) bit accumulator, a parallel shift circuit that bit-shifts the parallel variable length data in parallel using the output of the accumulator, and the output of the parallel shift circuit is sequentially accumulated in a register. Equipped with an alignment circuit that outputs N bits of data when the accumulated bit width exceeds N bits, the data length is accumulated in the accumulator, and the accumulated value allows parallel variable length data to be bit-shifted all at once. can.

Therefore, variable length encoding processing can be performed efficiently and at high speed.

Example Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a variable length encoding device showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of a parallel shift circuit showing an embodiment of the present invention.

In FIG. 1, 11 is a conversion circuit, 12 is a parallel shift circuit, 13 is an accumulator, 14 is an alignment circuit, 15.18 is parallel variable length data, 16 is the data length of parallel variable length data,
17 is the number of bit shifts, and 19 is a signal.

First, fixed length data is input to the conversion circuit 11. Parallel variable length data 15 and its data length 16 corresponding to this fixed length data are output from the conversion circuit 11 and input to the parallel shift circuit 12 and accumulator 13, respectively. The data length 16 input to the accumulator 13 is accumulated, and the number of bit shifts 17 is determined by the accumulated value. This bit shift number 17 is outputted from the accumulator 13 and inputted to the parallel shift circuit 12. In the parallel shift circuit 12, the bit shift of the parallel variable length data 15 is performed using the input bit shift number 17. .

The bit-shifted parallel variable length data 18 is manually input to the alignment circuit 14. In addition, a signal 19 indicating that the parallel variable-length data has been aligned with N bit width is sent to the alignment circuit 14 based on the cumulative value accumulated in the accumulator 13.

In response to this signal 19, N-bit wide parallel variable length data is output from the alignment circuit 14.

Next, an explanation diagram of the operation of a parallel shift circuit showing an embodiment of the present invention will be described with reference to FIG.

In FIG. 2(a), 21 is parallel variable length data. In addition, is the data length of the parallel variable length data, M is the output of the parallel shift circuit 12, N is the output bit width in the alignment circuit 14, and X is the number of bit shifts.
is a variable length of maximum 19 bits, M is a fixed length of 34 bits,
N is a fixed length of 16 bits, and X takes a value of 0≦X≦(ML).

As an example, the data length of parallel variable length data is L□=8
．． L2=10. L8=7. Consider the case where L,=5.

First, as shown in FIG. 2(b), the data of L1-8 pinto is output from the parallel shift circuit 12.

Next, when L2=10 bits of data is input to the parallel shift circuit 12, the accumulator 13 outputs the bit shift number “8°”.
゛ is sent, and as shown in Figure 2 (C), L2 = 10
The bit data is output from the parallel shift circuit 12 in a form shifted by 8 bits. Next, when L3=7 bits of data is input to the parallel shift circuit 12, the number of bit shifts output from the accumulator 13 becomes "18", exceeding the output bit width of 16 bits in the alignment circuit 14. Therefore, a signal is sent to the alignment circuit 14 indicating that the bits have been aligned with a width of 16 bits, and a bit shift number .degree. "2" (1B-16) is sent to the parallel shift circuit B12. Therefore, the data of L8=7 bits is output from the parallel shift circuit 12 in a form shifted by 2 bits, as shown in FIG. 2(d). Thereafter, when data of L,=5 bits is input to the parallel shift circuit 12, it is outputted from the parallel shift circuit 12 in a form shifted by 9 bits, as shown in FIG. 2(e).

As described above, the variable length encoding device of this embodiment includes an accumulator that accumulates the data length of parallel variable length data, and a parallel shifter that shifts the focus of the parallel variable length data in parallel using the output of the accumulator. Since it is equipped with a circuit, bit software of parallel variable-length data can be processed at once, and variable-length encoding processing can be performed efficiently and at high speed.

Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

Effects of the Invention As explained in detail above, the present invention includes an accumulator that accumulates the data length of parallel variable-length data, and a parallel shift circuit that shifts the focus of the parallel variable-length data in parallel using the output of the accumulator. Since it is equipped with this feature, bit shifting of parallel variable length data can be performed all at once, and variable length encoding processing can be performed efficiently and at high speed.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a variable length encoding device showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of a parallel shift circuit showing an embodiment of the present invention, and FIG. 3 is a conventional variable length encoding device. FIG. 1 is a schematic configuration diagram of an encoding device. 11... Conversion circuit, 12... Parallel shift circuit, 13... Accumulator, 14...
Alignment circuit, 15° 18.22...Parallel variable length data, 1G...Data length of parallel variable length data,
17... Bit shift number, 19... Signal. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 1 Figure 2 2g (0,) (b) (C) (d→ (e)

Claims (1)

[Claims] a conversion circuit that converts fixed length data into parallel variable length data and a data length corresponding to the parallel variable length data; and a log_2N(N) that accumulates the data length of the parallel variable length data.
is a power of 2) bit accumulator, a parallel shift circuit that bit-shifts the parallel variable length data in parallel using the output of the accumulator, and the output of the parallel shift circuit is sequentially accumulated in a register. A variable length encoding device comprising an alignment circuit that outputs N bits worth of data when the bit width exceeds N bits.