JPH01279371A - Designing device for logic circuit of lsi - Google Patents

Abstract

PURPOSE:To realize the external control of the area and the working speed of a produced logic circuit by searching a common formula of a multi-stepped logical formula and replacing said common formula with an intermediate variable to control the number of multiple steps. CONSTITUTION:At least one or more of a truth value table, a logical formula and the state transition description are supplied as the design input data on the logical function of an LSI. Thus a logical multi-step forming means 1 turns the logic of an AND-OR, etc., into a multi-step form and factorizes the logical formula that undergone the logical compression and includes no redundant member any more to search a common formula. This formula is replaced with an intermediate variable. The depth of the stage number can be easily operated from outside in an automatic draw-out state. Thus the external control is attained to the area and the working speed of a produced logic circuit.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment An Embodiment of the Present Invention (Figures 1 to 5) Invention Effects [Summary] Regarding LSI logic circuit design equipment, the purpose is to provide an LSI logic circuit design equipment that can adjust the area and operating speed of the generated logic circuit from the outside and can satisfy required specifications. , When at least one or more of truth tables, logical formulas, and state transition descriptions are manually entered as design input data for LSI logic functions, the LSI logic compresses the logic and outputs a netlist in line with the input data. The circuit design device is provided with a logic multi-stage means for multi-stageing the logic of the LSI, and the logic multi-stage means multi-stages logic such as AND-OR so that the logical formula after the multi-stage becomes small. By detecting the common 2 and replacing it as an intermediate variable, and adjusting the number of stages during this process, the area and operating speed of the generated logic circuit can be adjusted externally. Configure.

[Industrial application field]

The present invention relates to an LSI logic circuit design device, and more particularly to a device for automatically designing logic circuits such as CMOS gate arrays and standard cell arrays.

Recently, ASIC (Application 5p
Ecific LSI (application-specific IC) is attracting attention, but within the ASIC design process, automation is already progressing up to the layout design. At present, much of the logic circuit design upstream from layout design relies on human labor. As ASICs become larger in scale, the demand for automation of logic circuit design continues to increase. In response to this, the development of many logic synthesis systems has been reported at academic conferences. In particular, with the advent of rule-based expert system techniques,
The number of presentations on logic circuit synthesis systems increased rapidly. but,
There are no practical systems that can automatically synthesize the logic circuits of an entire chip for reasons such as the inability to design PLAL and the circuits being considerably thicker than those designed by hand.

[Conventional technology]

A system that automatically designs LSI logic circuits is generally called a silicon compiler. However, the definition of silicon compiler is not necessarily fixed, and is used as a general term for design tools that automatically generate a netlist (logic circuit) by inputting required specifications in a behavioral description language.

A conventional LSI logic circuit design device using this type of silicon compiler automatically creates one circuit from input descriptive data.

[Problem to be solved by the invention]

However, although such conventional LSI logic circuit design devices can automatically generate one circuit from input descriptive data, they cannot adjust the area or operating speed of the automatically generated circuit. For example, if a logic circuit is automatically generated, only the same logic circuit (in terms of area and operating speed) will be obtained for the same input data (description data), and therefore will not meet the performance requirements of the circuit designer. However, there was a problem in that it was difficult to put it into practical use.

On the other hand, there are systems that use so-called expert system techniques to adjust circuit area and operating speed, but these can only make very small adjustments.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an LSI logic circuit design apparatus that can externally adjust the area and operating speed of the logic circuit to be generated and that can satisfy required specifications.

[Means to solve the problem]

In order to achieve the above object, the LSI logic circuit design device according to the present invention uses at least one of a truth table, a logical formula, and a state transition description as design input data regarding the logic function of an LSI.
In an LSI logic circuit design device that compresses the logic and outputs a netlist in accordance with the input data when more than one logic is input, a logic multi-stage means for multi-stageing the logic of the LSI is provided, and the logic is multi-staged. The means is to multistage logic such as AND-OR, detect a common formula such that the logical formula after the multistage is small, and replace it as an intermediate variable. By adjusting the number of stages, the area and operating speed of the generated logic circuit can be adjusted externally.

[Effect]

In the present invention, a logic multi-stage means for multi-stageing the logic of an LSI is provided, and the logic multi-stage means multi-stages the logic such as AND-OR, and a common logic formula that becomes smaller after the multi-stage logic is provided. The expression is detected and a process is performed to replace it as an intermediate variable.

At this time, by adjusting the number of multistage stages when performing the processing, the area and operating speed of the generated logic circuit can be appropriately adjusted from the outside.

Therefore, a logic circuit that satisfies the performance required by the designer is automatically generated and can be put to practical use.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 5 are diagrams showing an embodiment of an LSI logic circuit design apparatus according to the present invention. FIG. 1 is a diagram showing the overall hardware configuration of this apparatus, and in this figure, 1 is a workstation for LSI design. The workstation 1 is a high-performance personal computer equipped with advanced man-machine interface functionality.

A designer 2 is opposite the workstation 1, and the designer 2 can automatically perform functional and logical designs in a hierarchical manner by operating a mouse while facing the cathode ray tube of the workstation 1. The workstation 1 has a function as a logical multistage means, and the steps of the program corresponding to this means will be described later.

This type of interactive processing between the workstation 1 and the designer 2 is the so-called upstream (previous) process of LSI design, and when designing a logic LSI for high-mix, low-volume production,
This is the part that traditionally required the most manpower. On the other hand, subsequent downstream processes include, for example, local area network (LA)
The configuration is such that the processing is left to a large-scale computer 4 and a dedicated machine 5 that are connected via N) 3. The large computer 4 is connected to a database 6, and the database 6 stores a large amount of various data necessary for design.

In the above configuration, the logical design processing program by the workstation 1 is shown as shown in FIG.
(n=1.2.3...) indicates each step of the program.

This program is an application of this device to a system that automates the logic circuit design of an ASIC control circuit.

In other words, the logical function of the desired circuit can be expressed as a logical formula, truth table,
If you enter a state transition description, it will output two types of design (circuit) data that realize the function, one is a PLA program pattern, and the other is a small gate scale circuit (cell). ) to realize the function by combining them, that is, a netlist whose constituent elements are such cells. In this case, by selecting cells from the gate array cell library, a gate array circuit can be realized, and by selecting from the standard cell library, a standard cell circuit can be obtained.

First, design specifications are input using Pl. Specifically, the logical formula, truth table, and state transition description corresponding to the logical function description are input. These are defined with unique names. Here, logical formulas and truth tables are convenient for combinational circuits such as various decoder circuits, and state transition descriptions are convenient for sequential circuits such as sequence controllers. In addition, in a program, you can easily describe transition branches by using, for example, IF'', ``WAIT'', ``CASE'', etc. In addition, in the case of state transition description, you can also use flip-flops to represent the state. Specify the type (D, JK, T, etc.).

Next, an editor (editing) is performed at P2, and the logical function description (input data) is translated at P3. This is the work of converting input data into an object program. P
In step 4, among the input data defined by unique names, a binary code for storing the state of the flip-flop is assigned (state assignment), especially for the state transition description, and the process then proceeds to P5. On the other hand, for items other than state transition descriptions, jump P4 and proceed to P5. In P5, logical compression is performed. This is a process of removing particularly redundant parts from the design specifications at the logical function level, and optimizes the logic.

Specifically, it is as follows. When this system receives input data, it converts the logic function into a two-stage AND-OR logic. At this point, there is no limit to the number of fan-ins and fan-outs for the AND gate and the OR gate, and if the input is a state transition description, state assignment processing is also performed to determine a binary code without representing the state. When this processing power is exhausted, the functional description data becomes an AND-OR two-stage logic circuit + flip-flop. Next, the process moves to step P5, where a logic minimization algorithm is applied to the AND-OR two-stage circuit portion to reduce the number of logic gates (more precisely, the number of AND gates). In other words, the number of product terms is reduced in the AND-OR product-sum format.

When the processing at P5 is completed, the process branches depending on whether it is PLA or another logic circuit, and if it is PLA, file conversion is performed at P6. This is interface processing as pre-processing for connecting to a conventional CAD system. Next, in P7, it is converted into PLA program data and output, and in P8 it is connected to a conventional CAD system. As a result, the PLA program pattern is passed through the module generator and then input into the conventional CAD system, and the logical function description is automatically converted to the mask pattern.

On the other hand, for logic circuits other than PLA, P, to P, ~P
The process branches to step 11. P, ,P,. This step is a feature of this embodiment. This step corresponds to the step of realizing the logic multi-stage means, and is different from the conventional method.

First, in P, the logic is multi-staged. This is a process of finding the common second that makes the multi-stage logical formula the smallest and replacing it with an intermediate variable.At this time, the depth of the number of stages when replacing the intermediate variable is determined by the designer This means that the circuit area and delay time can be easily adjusted.

Note that in this system, the limitation of the two-stage AND-OR circuit is eliminated and the circuit is multi-staged for the following reason. This is because by making a circuit multi-stage, the number of gates can be reduced in many cases, and in addition, by replacing common parts of multiple logical expressions (outputs) with intermediate variables (gates), the overall logic circuit can be made smaller. In addition to reducing the number of gates, increasing the number of stages has the advantage of equalizing the fan-in and fan-out numbers of the gates.

Here, the logic multi-stage processing will be explained using a specific example. Suppose that the following 2 is given as a representation of a logical function.

X=b-d-work+b-d-f The above three equations have been subjected to logic compression processing and have no redundant terms. Therefore, the number of product terms cannot be reduced any further. However, if we properly factorize each equation, a common 2 will appear. By sharing them, it is possible to express them in a smaller format than the original expression.

Logical multi-stage processing involves finding a common formula that minimizes the multi-stage logical formula and replacing it with an intermediate variable. Such processing is performed as follows.

First, the expression to be extracted is detected. That is, in the above equation, when the partial product is extracted, the following equation is obtained, and (b-7+b-d) can be replaced with an intermediate variable.

X=f・ (b-d+b-d) Y=b-f+d, f Z=b-f+d-f+f・ (b-d+b-d)Similarly, if we divide by T, we get the following equation .

X=f (b・d+b−d) Y−1(b+d) Z=f (b+d)+f (b−d+b・d)Furthermore, if these two are each replaced by the intermediate variable tI+(2), we get the following Become.

t,, =b-d+b-d L2-bottom+T You can create an impersonation. Although the expression "depth" is used, this means that, for example, as the depth increases, the number of gates tends to decrease and the area decreases. However, the delay time increases. Therefore, since the depth can be adjusted, trade-offs between circuit area and speed can be freely made within the system in the same way as when humans design circuits by themselves.

In other words, by setting the maximum delay time for the circuit you are designing, you can realize the same logic function as multiple circuits (netlists) with different speeds and circuit sizes, which solves the conventional problem. Thus, it is possible to design an LSI that satisfies the performance required by the circuit designer 2.

The above step P is only a process in the logical formula dimension, and then in P2O, cells having specific logic elements are allocated. Cell allocation involves conversion into cells, which consists of a four-step process in detail. First, replace cells with logic gates while adjusting the fan-in number. Try to use cells with a small chip area as much as possible. For example, in CMO3, if possible, 2
For example, it is converted into a composite gate that executes the logic for stages, and NAND gates are used rather than NOR gates (in the case of positive logic). Redundant parts are then removed, such as removing consecutive inverters. The third process is delay time adjustment. After removing redundant parts, the delay time of the bus included in the circuit is calculated based on the temporary wiring length. If there is a bus with a delay that exceeds the initially specified delay time, two processes are performed: either replacing it with a cell with the same function but with a smaller delay time, or reducing the number of stages to keep it within the specified range. The final process is adjusting the fanout number. If the fanout number of a cell is insufficient, replace it with a cell with a larger fanout number. If there are no such cells, divide the output. Also,
In the third process, if the fanout number of gates on the critical bus is insufficient, the output is divided. This is because a cell with a large fan error l-I& has a low speed.

The second to fourth processes are repeated until the specified delay time is obtained. In this way, cells are allocated to LSIs having delay times that match the design specifications.

Next, Pl+ outputs the netlist, and P8 connects it to the conventional CAD system.

Next, the effects of this embodiment will be explained with reference to graphs.

FIG. 3(a) shows the relationship between area and speed in standard cells, which can be adjusted within this range when allocating cells in this system. Similarly, FIG. 3(b) shows the relationship in the case of a channelless gate array. This can be adjusted by increasing the number of stages. For example, in the case of a 4-bit adder, increasing the number of stages from 8 to 4 increases the number of gates by about 1.5 times, but on the other hand, the delay time increases by about 1.5 times. Become smaller (faster).

In addition, Figure 4.5 similarly shows the relationship between area and speed. Figure 4 is an example of a case where a hard disk control circuit is designed in particular, and Figure 4.5 (a) shows a case where a standard cell is used.
The figure (b) shows the case of a gate array. In the figure, the O mark indicates that the stage has been multi-staged (as much as possible), and the Δ mark indicates that the stage has been multi-staged by specifying 3 stages.

FIG. 5 is a graph when a 16-bit count is constructed from standard cells.

〔effect〕

According to the present invention, since the area and operating speed of the generated logic circuit can be adjusted from the outside, it is possible to automatically generate an LSI logic circuit that satisfies the performance required by the designer, and also to create an LSI that can be put to practical use. A logic circuit design device can be obtained.

[Brief explanation of the drawing]

1 to 5 are diagrams showing an embodiment of an LSI logic circuit design apparatus according to the present invention, FIG. 1 is a diagram showing its hardware configuration, FIG. 2 is a flowchart showing its logic design program, 3 to 5 are graphs for explaining the effect. 1... Workstation (logical multi-stage means)
, 2...Designer, 3...Local area network, 4...
... large computer, 5 ... dedicated machine, 6 ... database. 2゛ Hand 3° Low Force Ruelia Nezutowagu Ura Hiroshi Table 4 Rows Hard 17'7 Item Figure 1 Figure 1 One Piece Figure 2: 1 currency, 1, 1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 5,

Claims (1)

[Claims] When at least one of a truth table, a logical formula, and a state transition description is input as design input data regarding the logic function of an LSI, the logic is compressed and a netlist is created in accordance with the input data. A logic circuit design device for an LSI that outputs a logic multi-stage means for multi-stage logic of the LSI, the logic multi-stage means multi-stage logic such as AND-OR, and a logical formula after the multi-stage logic. By detecting a common expression that makes
An LSI logic circuit design device characterized in that the area and operating speed of the logic circuit to be generated can be adjusted from the outside.