JP3106374B2 - Logic circuit optimization device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit optimizing apparatus, and more particularly, to a logic circuit optimizing apparatus for optimizing a multi-stage combinational logic circuit according to design conditions in a logic circuit design supporting apparatus.

[0002]

2. Description of the Related Art There are many logic synthesizers which automatically generate a logic circuit (usually a multi-stage logic circuit) from a logical expression or a truth table as a powerful design support device for designing a logic LSI in a short time. It is starting to be used. But,
The mere synthesis of the logic results in the quality of the synthesized logic circuit (chip area, operating speed, etc. in the case of LSI).
However, in many cases, it is inferior to the one designed by a skilled person, and in order to satisfy design conditions such as required LSI chip area and operation speed, the synthesized logic circuit is further optimized by a logic circuit. Needs to be optimized by the optimization device. Conventionally, several optimization devices for the multi-stage logic circuit have been proposed which are realized by computer programs.

As one of them, for example, there is a logic circuit optimizing apparatus configured by realizing a transduction method, which is one of the most excellent techniques in terms of optimizing ability, by a computer program (see References). : S.Mu
roga, et al., “A Logic Network Synthesis System, S
YLON ", Proc. ICCD, Oct. 1989 pp. 324-328). The transduction method applies a circuit modification to a logic circuit to be optimized based on its tolerance function. The tolerance function is defined for each logic gate (NOR gate, NAND gate, etc.) that constitutes the target logic circuit and each net (wiring) that connects between the gates. A set of logic functions permitted for each gate and each net, provided that the output of the terminal is not changed.

[0004] As another example of an optimization device, an example realized by a computer program by applying a method called a weak division that handles a logical function algebraically (Reference: A. Nagoya et al., “Multi-Level Logic Optimiza
tion for Large Scale ASICs ”, Proc. ICCAD, Nov. 19
90, pp 564-567). In this example, a logic synthesis device and a logic circuit optimization device are integrated, and a method of simultaneously performing a certain degree of optimization in the process of synthesizing a multi-stage logic circuit is used. There is an advantage that optimization can be performed with a practical computer memory amount within time.

[0005]

However, the allowance function in the former transduction method is a function set that can be calculated based on the logic function of each gate and each net (a function using the input to the external input terminal as a variable). Therefore, according to the number of external input terminals and the complexity of the logic circuit, the amount of computer memory for expressing the permissible function and the calculation time of the permissible function rapidly increase. Therefore, at present, it is difficult to optimize a large-scale logic circuit within a practical time with a logic circuit optimizing device having an excellent optimizing ability by the transduction method. In addition, in many cases, this type of optimization apparatus is implemented with a limitation from the beginning, such as targeting only a small-scale logic circuit such as a logic circuit having 32 or less external input terminals.

On the other hand, in the latter weak division, only circuit deformation is performed based on the local relationship between the gates, and it is difficult to enhance the optimizing ability even by applying this. Therefore, in an optimization device such as a weak division for a large-scale logic circuit, there is often room for improvement in an optimized logic circuit.

[0007] As described above, the improvement of the optimizing ability and the shortening of the calculation time required for the optimization are generally in conflict with each other. It is difficult to optimize with good quality.

[0008] The present invention has been made in view of the above points,
An object of the present invention is to provide an efficient logic circuit optimizing device capable of achieving both a scalable circuit scale and an optimizing ability.

[0009]

In a logic circuit optimizing apparatus for optimizing a target large-scale logic circuit based on design conditions, the number of input terminals to a partial circuit is set as a design condition.
Large-scale theory as much as possible with the number of inputs not exceeding the number of input terminals
And a circuit dividing means for repeatedly divided into a number containing subcircuit gate in physical circuit, divided partial by the circuit dividing means
One or a plurality of optimizing means for optimizing a circuit according to the design condition.

[0010]

The present invention divides a target large-scale logic circuit into partial circuits within a certain scale in order to increase the efficiency of optimization, and performs high-performance optimization on each of the divided partial circuits. By applying, the target circuit scale,
Also, the restriction on the optimization capability is greatly relaxed.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration diagram of an embodiment of the present invention. The logic circuit optimizing device shown in FIG. 1 includes a logic circuit input unit 11, a logic circuit division unit 12, a logic circuit optimization unit 13, a requirement input unit 14, a logic circuit merging unit 15, and a logic circuit output unit 16.

A logic circuit to be optimized is input from a logic circuit input unit 11, passed to a logic circuit division unit 12, and divided by a predetermined method into partial circuits in a predetermined scale range. The partial circuits divided by the logic circuit dividing unit 12 are sent to the logic circuit optimizing unit 13 and various design conditions (area minimization,
The optimization of the logic circuit is performed based on the delay time minimization and the like. The optimized partial circuits are combined by the logic circuit merging unit 15 and output from the logic circuit output unit 16 as a logic circuit in an optimized state.

Here, the partial circuits divided by the logic circuit dividing unit 12 can be regarded as independent logic circuits when they are passed to the logic circuit optimizing unit 13, so that the plurality of logic circuit optimizing units 13 They may exist in parallel and operate independently. In other words, the present apparatus can prepare only a single logic circuit optimizing unit 13 and sequentially process optimization of a plurality of partial circuits. Can be prepared and processed in parallel. Among these, the latter example of parallel processing can be realized by parallelization using a multiprocessor system when the logic circuit optimization unit 13 is configured by a computer program based on a transduction method or the like.

In the following description, a single logic circuit optimization unit 13 is prepared, and the logic circuit optimization unit 13
Since the optimization is realized by using existing optimization means based on the transduction method, it is assumed that the circuit scale to which the optimization means can be applied is limited to a logic circuit having 32 inputs or less.

FIG. 2 shows an example of a large-scale logic circuit according to one embodiment of the present invention. 2A shows an example of a logic circuit to be optimized by the device of the present invention.
This is a large-scale logic circuit that is an input to the device 1. In the figure, a region 21 shows a multi-stage combinational logic circuit to be optimized, and 22 to 28 in the region 21 are a part of logic gates constituting a large-scale logic circuit. In this embodiment, when the total number of external input terminals exceeds 32, the area 21 cannot be optimized by the logic circuit optimizing unit 13 as it is.

FIG. 2B shows an example of division of a logic circuit by a logic circuit division unit. The figure shows a logic circuit dividing unit 1
2 is an example in which the logic circuit of FIG. 2A is divided into three regions 31, 32, and 33 by a method described later. In FIG. 2B, an input terminal for the logic circuit in the region 31 is a part of an external input terminal. In addition, the area 32
Are part of the external input terminals. Further, the input terminal for the area 33 is a part of the external input terminal,
It is part of the output of the area 31 and part of the output of the area 32. As described above, in this embodiment, the logic circuit is divided such that the number of input terminals in each of these areas is 32 or less. Thereby, the area 31, the area 32,
Each of the regions 33 can be optimized by the logic circuit optimization unit 13. However, the logic gates 34 to 40 shown in FIG. 2B correspond to the logic gates 22 to 28 in FIG.

Next, an example of the operation of the logic circuit dividing section 12 will be described. FIG. 3 is a diagram for explaining the operation of the logic circuit division unit according to one embodiment of the present invention. In the multi-stage combinational logic circuit under division processing, the logic circuit dividing unit 12 sets a logic circuit area which is not yet to be divided as a region U, and a region (partial circuit) in which circuit division has already been completed and separated from the region U. Is regarded as a region V. At the start of the division process, the logic circuit division unit 12 sets the entire logic circuit to be optimized as a region U. At the start stage, since no division has been completed, the region V is regarded as empty and the process is performed. The following processing will be described on the premise of this. In FIG. 3, it is assumed that the area 50 is regarded as the area V and the area 51 is regarded as the area U.

(I) First, the logic circuit dividing unit 12 is a logic circuit dividing unit which is directly connected to the input terminals of the area U (part of the external input terminal and part of the output terminal of the area V). An arbitrary one gate is selected from among them and taken into a newly generated region W (assuming that the gate 54 is selected in FIG. 3). Next, following the connection on the input side of the area W, all the logic gates in the area U are taken into the area W until the input terminal of the area U is reached (at this point, in FIG.
6, 57 are taken into the area W, and the area W is the area 5 in FIG.
2). Here, if the number of input terminals in the area W exceeds the limit number (32 in this embodiment), the process starts again with the selection of the first gate.

(Ii) Next, the logic circuit dividing section 12 selects an arbitrary one of the areas U in the area U connected to an arbitrary input / output terminal of the area W.
A gate is selected and taken into the area W (in FIG. 3, it is assumed that the gate 58 is selected). Further, following the connection on the input side of the region W, all the logic gates in the region U are taken into the region W until the input terminals of the region U are reached (at this point, the gate 59 is taken into the region W in FIG. 3). , Area W is represented as area 53 in FIG. 3). If the number of input terminals in the area W exceeds the limit, the process is repeated from the selection of any one gate in (ii).

(Iii) The logic circuit dividing unit 12 repeats the process of (ii) until there is no more logic gate to be selected in the area U. As a result, a region W in which the number of input terminals is equal to or less than the given number, that is, one of the partial circuits to be obtained is extracted.

Next, the above-described (i) to (iii) are repeated by regarding the area U from which the area W has been removed and the area V to which the area W has been added as new areas U and V, respectively.

The logic circuit division unit 12 repeats the above until the area U becomes empty, thereby converting one logic circuit to be optimized given from the logic circuit input unit 11 into a plurality of logic circuits each having a limited number of input terminals. Is divided into sub-circuits. Each of the partial circuits is sent to the logic circuit optimization unit 13 and is subjected to optimization.

The operation of the logic circuit dividing section 12 merely provides a region to which the logic gate belongs, and does not change the existing logic gate and the connection between the logic gates. Therefore, when the logic circuit division unit 12 is realized by a computer program, the calculation time required for circuit division may be sufficiently shorter than the calculation time required for the logic circuit optimization unit 13 for circuit optimization.

In general, the method of individually optimizing the divided areas has a narrower range of candidates for circuit deformation for optimization than the method of optimizing the whole area collectively, and therefore, theoretically, Will be slightly reduced. But,
In practice, in the latter method of optimizing the whole, the application of advanced circuit optimization based on the transduction method or the like, which could not be applied at all, becomes possible for each divided partial circuit. As a whole, the optimization ability improves the quality of optimization as compared with a method of optimizing the entire circuit collectively by using a method such as a weak division.

Further, in order to reduce the time required for optimizing a large-scale logic circuit, parallel processing using a plurality of logic circuit optimizing units 13 can be easily realized, and the processing capability of the present apparatus can be reduced step by step. It is possible to gradually upgrade.

In the above example, if the number of external input terminals of a given logic circuit is 32 or less, high-level optimization will occur without dividing the circuit, and the existing powerful optimization method will be used as it is. It has the same effect as applying. That is, the logic circuit optimizing apparatus according to the present invention can efficiently apply an advanced optimization technique based on the transduction method or the like to logic circuits of any scale.

[0027]

As described above, the logic circuit optimizing apparatus of the present invention realizes high-quality optimization of a large-scale logic circuit within a practical time, and achieves both the circuit scale and the optimization ability. Logic circuit optimization becomes possible.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a large-scale logic circuit according to one embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of a logic circuit division unit according to one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Logic circuit input part 12 Logic circuit division part 13 Logic circuit optimization part 14 Requirement condition input part 15 Logic circuit merging part 16 Logic circuit output part 21 Multi-stage combination logic circuit 22-28 Logic gate 31-33 Divided multi-stage logic circuit 34-40 Logic gate 50 Multi-stage logic circuit 51 already divided Logic circuit area 52 before division processing is applied 52, 53 Area where division processing is applied 54-59 Logic gate

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50

Claims (1)

(57) [Claims] In a logic circuit optimizing apparatus for optimizing a target large-scale logic circuit based on design conditions, the number of input terminals to a partial circuit is set as the design condition, and
As long as the number of inputs does not exceed the number of children,
Circuit dividing means for repeatedly dividing into partial circuits including a large number of gates in a path, and one or a plurality of optimizing means for optimizing the partial circuits divided by the circuit dividing means according to the design conditions A logic circuit optimizing device comprising: