JPS6319085A - Image accumulating device - Google Patents

Abstract

PURPOSE:To easily attain the setting of a picture frame by providing a memory means at a memory control circuit and controlling the writing and reading of a memory in accordance with a waveform stored here. CONSTITUTION:An image accumulating device has the large capacity of image memories 6aR-6dG and microcomputers 12a-12d. At the memory control 15 of the image memories 6aR-6dG, a memory means 39 is provided. An optional waveform is written from the microcomputers 12a-12d to the memory means 39, and in accordance with the written waveform, the control of the writing and reading of the image memories 6aR-6dG is executed. By changing over the wave form written into the memory means 39 optionally, the setting, etc., of the picture frame can be executed.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial application field B. General knowledge of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Overall structure of Example G1 (Fig. 1) Figure) Explanation of G2 memory control circuit (Figure 2) Explanation of G3 memory handling (Figure 3) Explanation of G4 asynchronous control circuit (Figure 4) H Effect of invention A Industrial application field The present invention is suitable for large capacity The present invention relates to an image storage device using semiconductor memory.

B. Summary of the Invention The present invention relates to an image storage device, and provides a memory control circuit with a storage means, thereby making it possible to easily set the inner frame of an image to be stored, divide the image, etc. be.

C. Conventional Technology Image signals are accumulated and the accumulated image signals are processed by a processing device such as a computer (see Japanese Patent Application Laid-Open No. 58-215813). In this case, as a device for storing images, a so-called video cheap recorder has conventionally been used.

However, for example, in an Amerog type video tape recorder, one signal such as a luminance signal or a composite signal is usually used.
Since only channel signals can be recorded and reproduced, it has been difficult to correspond to so-called three-channel signals of three primary colors, which are generally used in image processing. In addition, with video tape recorders, it is difficult to stabilize the reproduction state of the signal taken out, and the processing contents that can be used are limited.

On the other hand, as the capacity of so-called semiconductor memory ICs has increased and their prices have decreased, it has become possible to accumulate and process image signals for several seconds, both from the standpoint of implementation and cost. However, in conventional devices of this kind, the processing of image data is based on one frame, so for example, the image frame for storing data is limited to the effective screen, and storage address allocation on the memory is also limited to one frame. It was customary to be limited to each type of data. For this reason, the number of frames that are stored is limited, and even if you only want to process a portion of the inner surface, the entire screen is stored, and the number of frames that are stored cannot be increased, making it difficult to use memory effectively. I couldn't.

D. Problems to be Solved by the Invention In the conventional techniques described above, the image frame and the layout in the memory are limited, and there are problems such as the inability to use the memory effectively.

E Means for Solving Problems The present invention provides a large capacity image memory (6aR) to (6dB
) and microcomputers (12a) to (12d), and includes a memory control circuit (15) for the image memory.
) is provided with a storage means (39), an arbitrary waveform is written from the microcomputer into the storage means, and writing/reading of the image memory is controlled according to the written waveform. be.

F. Effect According to this, the memory control circuit is provided with a storage means, and the writing/reading of the memory is controlled according to the waveform stored therein, so that the image can be easily created by arbitrarily rewriting this waveform. You can set frames, etc.

G Overall configuration of Embodiment G1 In FIG. 1, (IR), (IG), and (IB) are input terminals for analog three primary color signals, and the signals from these terminals (IR) to (IB) are AD converted. circuit(
2) Three data buses (3R) (3G) through
(3B). Also (4R) (4G)
(4B> are input terminals for digital three primary color signals, and the signals from these terminals (4R) to (4B) are connected to the data bus (3R) through the interface circuit (5).
~ (3B) is supplied.

Furthermore, the data on the data bus (3R) is transferred to memory 0 (6aR).
), 3 (6bR), 6 (6cR),
9 (6dR) [however, some parts are omitted in the figure], and data on the data bus (3G) is supplied to memory 1 (
6aG).

4 (6bG), 7 (6cG), 10
(6dG), and the data on the data bus (3B) is sent to memory 2 (6aB).

5 (6bB), 8 (6cB), 11
(6dB). Also memory O (6aR)
, 3 (6bR) 6 (6cR).

9 (6dR) data is supplied to the data bus (7R), and memory 1 (6aG), 4 (6bG),
? (6cG).

10 (6dG) of data is supplied to the data bus (7G), memory 2 (6aB), 5 (6bB)
), 8 (6cB).

11 (>6dB) of data is supplied to the data bus (7B).

The data on this data bus (7R) to (7B) is passed through the DA conversion circuit (8) to the analog three primary color signal output terminal (
9R) (9G) (9B). Further, data is supplied via the data buses (7R) to (7B) to the digital three primary color signal output terminal ClOR' (IOC) (10B) through the interface circuit (5). Furthermore, the data on the data bus (7R) to (7B) is passed through the data bus (3) through the pipeline processing circuit (11).
R) to (3B).

Also, memory 0 (6aR), 1 (6aG),
2 (6aB) and microcomputer (MPU) O
(12a) via the pass line (13a), and memories 3 (6bR) to 5 (6bB) and M
Data is exchanged with the PUI (12b) via the pass line (13b), and memories 6 (6cR) to 8 (6cB
) and M, P U 2 (12c) via the pass line (13c), and the data is exchanged between the memory 9 (6
Data is exchanged between the MPU3 (12d) and the MPU3 (12d) via the pass line (i3d).

Furthermore, a host computer (not shown) and MPU0 (1
Data is exchanged with 2a) via the interface circuit (14) and the hash line (13a). Also M
A lotus line (13
Data is exchanged via a), and the signal from this control circuit (15) is transmitted to each memory 0 (6aR) -1
1 (6dB). Furthermore, M P U O (1
Data is exchanged between 2a) to 3(12d) and a general-purpose CP-1B fin (16).

Description of G2 memory control circuit and in this device, the memory control circuit (1
5) is constructed as shown in FIG. The figure shows a configuration corresponding to either writing or reading of C1 for one circuit among memories 0 (6aR) to 11 (6dB).

That is, in the figure, (21) is a register, and to this register (21), an arbitrary numerical value from the above-mentioned MPU0 (+2a) is supplied through the terminal (22), and the same value is supplied from the same <MPU0 (12a). A write pulse of M U O
The value from (12a) is written.

Also, the write pulse from the terminal (23) is sent to the inverter (24).
), ゛ζ flip-flop (2
6) is supplied to the trigger terminal of this flip-flop (
A high potential is supplied to the data terminal of 26). The Q output of this flip-flop (26) is
) is supplied to the data terminal of

Furthermore, a frame pulse synchronized with the video signal to be processed is supplied to the trigger terminal of the flip-flop (27) through the terminal (28). This flip-flop (27)
The Q output of is supplied to the clear terminal of the flip-flop (26).

Therefore, the Q output of the flip-flop (26) outputs a signal that becomes the sentencing potential from when the write pulse is supplied to the terminal (23) until the end of the next frame period.

Further, the numerical value written in the above-mentioned register (21) is supplied to the recent terminals of the counters (29a) (29b) connected in series. Furthermore, flip-flops (2
The Q output of 6) is sent to the counter (2) through the NOR circuit (30).
9a) (29b) is supplied to the load terminal.

Also, the frame pulse from the terminal (28) is sent to the counter (2
9a) (29b) is supplied to the clock terminal.

Further, the carry output of the upper counter (29b) is supplied to the NOR circuit (30), and the output of this NOR circuit (30) and the frame pulse from the above-mentioned terminal (28) are supplied to the NAND circuit (31). be done.

Therefore, a frame pulse is output from this NAND circuit (31) immediately after the write pulse is supplied to the terminal (23) and every time a frame period corresponding to the value written in the register (21) has elapsed. .

The signal from this NAND circuit (31) is transmitted to memory 0 (6a
R) to 11 (6 dB) is supplied to a terminal (32) connected to a load terminal of an address counter of an arbitrary memory board (described later).

Further, an arbitrary freeze signal is supplied to the OR circuit (25) through the terminal (33). Furthermore, the freeze signal from this terminal (33) is supplied to the data terminal of the flip-flop (34), and the carry signal from the counter (29b) mentioned above is supplied to the trigger terminal of the flip-flop (34). The d output of the pump (34) is supplied to AND circuits (35) and (36).

Therefore, when a freeze signal is supplied to the terminal (33), a numerical value is loaded into the counters (29a) (241b) at the rising edge of the freeze signal, as with the write pulse described above, and during the period of this freeze signal, the flip-flop is loaded. The Q output of the input terminal (26) remains at a high potential, and the frame pulse is continuously output to the terminal (32). Then, when the frame period corresponding to the value written in the register (21) has elapsed, the carry signal of the counter (29b) is supplied to the flip-flop (34), and the flip-flop (34) is supplied with the carry signal of the counter (29b).
The d output of 34) is brought to a low potential, thereby cutting off the AND circuits (35) and (36).

Furthermore, the address corresponding to any position on the screen from the above-mentioned MPL) O (12a) is connected to the terminal (37V) (
37H), and this address is supplied to the gate circuit (38H).
V) (38H) through random access memory (R
AM) (39V) (3911) is supplied to the address terminal.

Kokote RAM (39V) (39H) is for each at lz
, 2. consists of 2 bits. And this RAM (3
The control value of each bit of 6V) (36H) is the bidirectional gate circuit (40V) (40H) and the terminal (41V).
(41H) and is exchanged with MPU0 (12a). Furthermore, the write control pulse from MPU0 (12a) is applied to the test circuit (40V) through the terminals (42ν) (42H).
) (40)1) is supplied to the direction control terminal, and the mode pulse from MPU0 (12a) is supplied to the terminal (43).
V) (43H) through the gate circuit (38V)
(40V) (38)1) (408), and the write control pulse and mode pulse are supplied to the NAND circuit (44V) (408).
4/1) RAM (39V) (3) through 1)
9H) is supplied to the write control terminal.

Therefore, any address from MP U O (12a),
The control value, write control pulse and mode pulse are connected to the terminal (37
V ) (41V) (42V) (43V
) or (37B) (4111) (42'H)
(43B), RAM (39ν) (3
A desired control value is written to a desired address of 9H).

Further, when the above-mentioned write control pulse is inverted and supplied to each terminal, the control value of the desired address of the RAM (39VI (39H)) is read out to M P tJ (+('12a)).

The frame pulse from the terminal (28) is countered.
(45V) is supplied to the clear terminal of this counter (
A horizontal synchronizing pulse is supplied from the terminal (46) to the clock terminal of the counter (45ν), and a horizontal synchronizing pulse from this terminal (46) is supplied to the clear terminal of the counter (45)1). ) is supplied with a clock pulse from a terminal (47). The count value of this counter (45V) (45H) is transferred to the RAM through the gate circuit (48V) (48H).
(39V) (39H) is supplied to the address terminal, and the mode pulse from the terminal (43V) (43H) is supplied to the chip select terminal of the gate circuit (48V) (48H) through the inverter (49V) (49)1). Supplied.

Therefore, when the mode pulse mentioned above is inverted, the counter (
The address synchronized with the video signal to be processed formed by 45V') (45)1) is stored in RAM (39ν) (3
9H), and the control value of each address is read.

Among the two-bit control values from the Saranico (7) RAM (39V) (39H), control values of the same bits are supplied to AND circuits (35) and (36), respectively.

Therefore, from this AND circuit (35) (36), the address number determined by each counter (45V) (45H), ROM (39V) (39H
) (7) A high potential signal is output only when the control values of the same bits are both high potentials. Furthermore, this signal is cut off when the d output of the flip-flop (34) is at a low potential.

The signals from the AND circuits (35) and (36) are connected to the terminal (50) connected to the drive control terminal of the address counter of the memory board and the write/write terminal of the memory board, respectively.
It is supplied to a terminal (51) connected to the read control terminal.

Description of G3 Memory Board Next, the memory board is constructed as shown in FIG. The figure shows one circuit of memories 0 (6aR) to 11 (6 dB), and the portions corresponding to those described above are shown representatively by removing the alphabetical suffixes of the symbols.

In this figure, signals on an address bus (13A) among the pass lines (13) are supplied to an address decoder (61). Also, the data bus (1) of the pass line (13)
30) signal is write (W) address register (62W)
and the continuation (R) address register (62R). Furthermore, the signal decoded by the decoder (61) is
They are supplied to control terminals of registers (62W) and (62R), respectively.

Therefore, an arbitrary numerical value is supplied to the data bus (130),
When a predetermined address is supplied to the address bus (13^), this address is decoded by the decoder (61),
The register (62W) or (62R) is driven and the above-mentioned numerical value is written into the register (62W) or (62R). Note that different addresses are assigned to the registers (62W) (62R).

The numbers written in these registers (62W) (62R) are respectively counted as counters (63W) (63R').
is supplied to the pre-sent terminal. In addition, the above-mentioned terminal (32
) are respectively supplied to the load terminals of the counters (63W) (63R). Furthermore, signals from (50W) (5011) corresponding to the above-mentioned terminal (50) are supplied to drive control terminals of counters (63W) (63R), respectively.

Further, arbitrary write clock signals and successive clock signals are supplied to the terminals (64W < 64R), respectively.
This clock signal is divided into 16 frequency dividers (65W) (
65R) and this frequency dividing circuit (65W
) (65R) to the drive control terminal (50) (5
0R) is supplied, and this frequency divider circuit (65W
) (65R) The signal from the counter (63W)
(133R) is supplied to the clock terminal.

Therefore, in this counter (63W) (63R),
The numerical value of the ζ register (62W) (62R') is preset by the signal from the terminal (3214) (3211), and from then on, the signal from the frequency divider circuit (65) (65R) is counted and the terminal ( 5 (E) (
Counting is stopped when the signal from 50R) is at a low potential.

Also, the signal from the address bus (13A) is transmitted to the register (6
6).

Further, the internal clock signal supplied to the terminal (67) is supplied to an asynchronous control circuit (68) to be described later, and the signal decoded by the decoder (61) and the frequency dividing circuit (65W) (65R) are The signal is in the control circuit (
6B). As a result, the control circuit (68) is controlled in response to data exchange requests from the MPU (12) and write requests and read requests from the memory control circuit (15) so that these requests do not collide with each other. Command signals are formed and output, and each of these command signals is sent to the register (66), counter (63W) and (63R).
is supplied to the output control terminal of And this register (6
6) Arbitrary numerical values and count values from the counter (63W) < 63R) are sent to the random access memory (RAM) (70) for image storage via the address bus (69).
) is supplied to the address terminal.

Also, the signal from the terminal (51) is sent to the memory control circuit (71).
At the same time, a signal from the control circuit (68) described above is supplied to the control circuit (71). As a result, the write control signal (WE) is generated during the period when the output control signal is supplied to the counter (63W) or the register (66) at the time of the above-mentioned write request and data exchange request. The data is then supplied to the RAM (70). Further, a so-called row and column address control signal (RAS/CAS) is formed in accordance with a signal from the control circuit (68) and supplied to the RAM (Ma0).

Furthermore, the data from the data bus (3) is transferred to the parallelization circuit (7).
2), and 16 pieces of data are parallelized.

This parallel data is supplied to the register (73W), and the same command signal as the counter (63W) from the control circuit (68) is supplied to the control terminal of the register (73W). As a result, the parallel data supplied to the register (73W) is output at a predetermined timing, and the data bus (74)
The data is written to the address specified by the counter (63W) of the RAM (70).

Also, the data (parallel data) at the address specified by the counter (63R) of the RAM (70) is transferred to the data bus (74).
At this time, the control circuit (68) supplies the same command signal as the counter (63R) to the register (73R), and data at the specified address passes through the register (73R) to the °ζ multiplexer ( 75). And this multiplexer (7
5), the output control signal (
OE), 16 pieces of parallel data are sequentially supplied one data at a time to the data bus (7).

Furthermore, the data on the data bus (74) is transferred to the register (66).
) is exchanged with data on the data bus (130) via a register (76) controlled by the same command signal.

Therefore, in this circuit, the data base (3 data) is written to the RAM (70) according to the control from the MPU (12) and the memory control circuit (15), and
The data of AM (70) is read out to the data bus (7),
Sarani RAM (70) 0:) Cheetaka MPTJ (
12).

The capacity of the RAM (70) is, for example, 4 MB. This reduces the number of pixels in one frame to, for example, 768
512, it is possible to store data for about 10 frames, and data for 40 frames x 3 primary colors can be stored in total.

Description of G4 Asynchronous Control Circuit Furthermore, the above-mentioned asynchronous control circuit (68) is configured as shown in FIG. In this figure, the terminal (81W
) (811?) (81M) are supplied with write, continuation, and MPU request signals, respectively. The signals from these terminals (81W), (81R), and (81M) are connected to flip-flops (82W), (81M), respectively.
2R) (82M) is supplied to the trigger terminal of this flip-prop (82R) (82M).
A high potential is supplied to the data terminals of and). Q of this flip-flop (82W) (821?) (82M)
Output is delay element (83) (83R) (83M)
Through Nando circuit (84 buttocks) (84R) (84M
), and this NAND output is fed to the flip-flop (
85W ) (85R) (85M) (supplied to the D data terminal. This flip-flop (85W
) (85R) (85M) Q output is a flip-flop (82W) (82R) (82M)
At the same time, the Q output is supplied to the clear terminals of the shift registers (86W) (86R) (86M). Furthermore, the terminal (87K) (8
The internal clock signal from 7R) (87M) is supplied to the shift register (86W) (86R) (86M). And this shift register (86W)
(86R) Q8 output of (86 and) is written, output terminal of each command signal of MPU (88) (88
R) (88M).

Furthermore, the output of the flip-flop (82W) and the d7 output of the shift register (86W) are connected to the NOR circuit (89W).
), and this NOR output is supplied to the NAND circuit (84R).
(84M). Also flip-flop (
82R) output and the giant 7 output of the shift register (86R) are supplied to the NOR circuit (891?), and this NOR output is supplied to the NAND circuit (84M), and the d7 output of the shift register (86R) is a NAND circuit (84W
). Further, the d output of the shift register (86M) is supplied to the NAND circuit (84W) (84R).

Therefore, in this circuit, priority is set in the order of write-read->MPU, and when request signals are supplied more than one clock apart, an 8-clock command signal corresponding to the previous request signal is output. Afterwards, a command signal corresponding to the subsequent request signal is output, and when multiple request signals are supplied within a clock, each 8 is output according to the priority order described above.
A clock command signal is output.

In addition, in the above configuration, the internal clock is, for example, 32 MHz, and on the other hand, the data input and output to the RAM (70) has one frame of 768 x 512 pixels, and the pixel clock is approximately 11.8 MHz (30 frames per second). Since 16 data are processed in parallel, the data clock frequency is approximately 0.7 MHz. Therefore, command signals for eight internal clocks can be output more than five times during one data clock, and no problem will occur even if the asynchronous control described above is performed.

This is how images are stored. According to the above-mentioned device, by writing an arbitrary value to the register (21) of the memory control circuit (15), a frame period corresponding to this value is elapsed. A frame pulse is supplied to the memory (6) for each frame pulse, and a so-called frame-by-frame image is stored. Further, by supplying a freeze signal to the terminal (33), frames corresponding to the value in the register (21) are continuously stored in the memo (January 6), and subsequent writing is stopped.

Furthermore, by writing an arbitrary control value to RAM (39V) (39H), an image frame corresponding to this control value is set, and data only within the range of this image frame is included.

In this case, since the address counters (63R') (63W) of the memory (6) are stopped outside the range of the image frame, data is efficiently stored on the RAM (70) without any blank spaces. In addition, when writing continuously, the image is formed at the same position on the screen by using the same control value as when writing, but at this time, the register (62R) (62
It is necessary to sequentially write the first address of each image frame calculated in advance by the MPU (12) etc. to W').

Note that in the above example, three primary colors (RGB) were stored, but when storing a composite signal, the data bus (3R) (3G) (3B) (7R) for the three primary colors described above is used.
)(7G) By using (, 7B) independently,
It is also possible to accumulate three times as long.

H Effects of the Invention According to this invention, the memory control circuit is provided with a storage means, and memory writing/writing is performed according to the waveform stored therein.
Since readout is controlled, image frames can be easily set by arbitrarily rewriting this waveform.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of an example of the present invention, and FIGS. 2 to 4 are specific configuration diagrams of main parts, respectively. (6aR) ~ (6dB) is memory, (12a
) to (12d) are microcomputers, (i5
) is a memory control circuit, and (39) is a random access memory as a storage means.

Claims (1)

[Claims] It has a large capacity image memory and a microcomputer, a memory control circuit of the image memory is provided with a storage means, an arbitrary waveform is written from the microcomputer into the storage means, and an arbitrary waveform is written from the microcomputer to the storage means. An image storage device that controls writing/reading of the image memory according to a waveform.