JPS63188196A - Slit resistance switching circuit - Google Patents
Slit resistance switching circuitInfo
- Publication number
- JPS63188196A JPS63188196A JP2091587A JP2091587A JPS63188196A JP S63188196 A JPS63188196 A JP S63188196A JP 2091587 A JP2091587 A JP 2091587A JP 2091587 A JP2091587 A JP 2091587A JP S63188196 A JPS63188196 A JP S63188196A
- Authority
- JP
- Japan
- Prior art keywords
- switching circuit
- dividing
- dividing resistor
- divided
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 description 13
- 238000012360 testing method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000011990 functional testing Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は分割抵抗切換回路に関し、特に電子式卓上計算
機の液晶駆動回路等に用いられる分割抵抗切換回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a divided resistance switching circuit, and more particularly to a divided resistance switching circuit used in a liquid crystal drive circuit of an electronic desk calculator.
電子式卓上計算機（以下、電卓という）において製品の
テストをする場合、外部の入力端子よりテストパターン
を入力して、内部のロジックおよび内部ＲＯＭのデータ
チェックなどを行う、データの出力は通常出力バッファ
などの出力端子を用い、例えば電卓は液晶出力端子を多
数有するため、そのデータ出力をチェックする端子とし
ては好都合となっている。When testing a product using an electronic desktop calculator (hereinafter referred to as a calculator), a test pattern is input from an external input terminal to check the internal logic and internal ROM data, and the data is usually output from an output buffer. For example, a calculator has many liquid crystal output terminals, so it is convenient as a terminal for checking the data output.
電卓の液晶出力端子は分割抵抗により分割された電位を
液晶レベルセレクタにより選択して出力する分割抵抗切
換回路に接続されている。The liquid crystal output terminal of the calculator is connected to a dividing resistor switching circuit which selects and outputs the potential divided by the dividing resistors using a liquid crystal level selector.
従来の電卓の分割抵抗切換回路の分割抵抗の抵抗値は貫
通電流制、御のため高く設定されていた。The resistance value of the dividing resistor in the dividing resistor switching circuit of conventional calculators was set high in order to control the through current.
上述した従来の分割抵抗切換回路を用いた電卓の機能テ
ストでは、出力データが液晶端子から出力される時、内
部の分割抵抗の抵抗値が高いため、周波数が高くなるに
つれて、ＬＳＩの内部インピーダンスと測定器の負荷容
量により、出力波形がなまってしまい、正常な機能テス
トができないという欠点があった。In a functional test of a calculator using the conventional dividing resistor switching circuit described above, when the output data is output from the liquid crystal terminal, the resistance value of the internal dividing resistor is high, so as the frequency increases, the internal impedance of the LSI and The problem was that the output waveform was distorted due to the load capacity of the measuring instrument, making it impossible to perform a normal functional test.
本発明の目的は、上記欠点に鑑み、分割抵抗値を変えて
内部インピーダンスを下げることを可能にした分割抵抗
切換回路を提供することにある。SUMMARY OF THE INVENTION In view of the above drawbacks, it is an object of the present invention to provide a dividing resistance switching circuit that makes it possible to lower internal impedance by changing dividing resistance values.
本発明の分割抵抗切換回路は、電源間の電位を複数の第
１の分割抵抗により分割した複数の電位をレベルセレク
タにより選択して出力する分割抵抗切換回路において、
複数の前記第１の分割抵抗それぞれに並列に接続された
スイッチと第２分割抵抗の直列接続を含んで構成される
。The divided resistance switching circuit of the present invention is a divided resistance switching circuit that selects and outputs a plurality of potentials obtained by dividing the potential between power supplies by a plurality of first dividing resistors using a level selector.
It is configured to include a switch connected in parallel to each of the plurality of first dividing resistors and a second dividing resistor connected in series.
次に本発明の分割抵抗切換回路について図面を参照して
説明する。Next, the divided resistance switching circuit of the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の電卓の液晶駆動回路用の分
割抵抗切換回路のブロック図である。１は通常使用時の
分割抵抗、２は液晶レベルセレクタ、３はテスト時の分
割抵抗、４は分割抵抗切換用の制御信号、５は液晶レベ
ル選択用の制御信号、６はトランスファーゲートである
０分割抵抗１の抵抗値をＲ１分割抵抗３の抵抗値をＲ８
とし、Ｒ′Ｐ；ＰＲｏどなるように抵抗値を設定してお
く。FIG. 1 is a block diagram of a dividing resistor switching circuit for a liquid crystal drive circuit of a calculator according to an embodiment of the present invention. 1 is a dividing resistor during normal use, 2 is a liquid crystal level selector, 3 is a dividing resistor during testing, 4 is a control signal for switching the dividing resistor, 5 is a control signal for selecting a liquid crystal level, and 6 is a transfer gate.0 The resistance value of dividing resistor 1 is R1 The resistance value of dividing resistor 3 is R8
Then, the resistance value is set so that R'P; PRo.
通常使用時は制御信号４を低レベルにすることにより、
トランスファーゲート６をＯＦＦにして使用する。電源
ＶＤＤの電位を分割抵抗で分割した電位のいずれかを制
御信号５により液晶レベルセレクタ２が選択して出力信
号線１２を通して出力バッファへ、さらには液晶に伝え
る。During normal use, by setting control signal 4 to a low level,
Use with transfer gate 6 turned OFF. The liquid crystal level selector 2 selects one of the potentials obtained by dividing the potential of the power supply VDD by the dividing resistor according to the control signal 5, and transmits the selected potential to the output buffer and further to the liquid crystal through the output signal line 12.
電卓のテスト時には、制御信号４を高レベルにすること
によりトランスファーゲート６をＯＮにして使用する。When testing the calculator, the control signal 4 is set to a high level to turn on the transfer gate 6.
このようにすることにより分割抵抗１と３が並列に接続
されるがＲ＞Ｒｏであるため、分割抵抗１の抵抗値Ｒは
無視され、分割抵抗３の抵抗値Ｒ，で抵抗分割され、内
部インピーダンスが下がり、液晶端子に出力される出力
波形のなまりを小さくすることができる。By doing this, dividing resistors 1 and 3 are connected in parallel, but since R>Ro, the resistance value R of dividing resistor 1 is ignored, and the resistance is divided by the resistance value R of dividing resistor 3, and the internal The impedance is lowered, and the rounding of the output waveform output to the liquid crystal terminal can be reduced.
第２図は本発明の他の実施例の電卓駆動回路用の分割抵
抗切換回路のブロック図である。第２図の１．２．５．
６は第１図に示すものと同様である。７は分割抵抗（抵
抗値がＲ１）、８は分割抵抗（抵抗値がＲ２）、９〜１
１は制御信号、１３゜１４はノアゲートである０分割抵
抗の抵抗値はＲ＞Ｒ１＞Ｒ２に設定しておく、また分割
抵抗切換用にトランスファーゲート６のほかにトランス
ファーゲート６′も設けられている。FIG. 2 is a block diagram of a dividing resistor switching circuit for a calculator driving circuit according to another embodiment of the present invention. 1.2.5 in Figure 2.
6 is similar to that shown in FIG. 7 is a divided resistor (resistance value is R1), 8 is a divided resistor (resistance value is R2), 9 to 1
1 is a control signal, 13° and 14 are NOR gates.The resistance values of the 0-divided resistors are set to R>R1>R2.In addition to the transfer gate 6, a transfer gate 6' is also provided for switching the divided resistors. There is.
通常使用時には、制御信号９を高レベルにして分割抵抗
７，８を切り放しておく。During normal use, the control signal 9 is set at a high level to disconnect the dividing resistors 7 and 8.
テスト時には、制御信号９を低ベレルにし、さらに制御
信号１０および１１を変えることにより、出力端子にか
かる負荷容量に応じた抵抗値を選択することができる。At the time of testing, by setting the control signal 9 to a low level and further changing the control signals 10 and 11, it is possible to select a resistance value according to the load capacitance applied to the output terminal.
この実施例では、抵抗値をいろいろと変化させることが
可能となるため、出力端子の負荷の大きさにより、適切
な抵抗値でのテストが可能となる利点がある。This embodiment has the advantage that it is possible to vary the resistance value, and therefore allows testing at an appropriate resistance value depending on the magnitude of the load on the output terminal.
以上説明したように本発明の分割抵抗切換回路は、通常
使用時は内部の分割抵抗値を大きくして貫通電流を小さ
くして消費される電流を抑え、テスト時には内部の分割
抵抗値を小さくして出力端子の能力を上げることにより
、出力データの出力波形のなまりを小さくできる効果が
ある。特に、本発明を電卓に適用した場合のＲＯＭのデ
ータチェックなど出力波形の変化の顕著なデータに対し
て特にこの効果は大きい。As explained above, the divided resistance switching circuit of the present invention increases the internal divided resistance value to reduce the through current to suppress current consumption during normal use, and reduces the internal divided resistance value during testing. By increasing the capability of the output terminal, it is possible to reduce the roundness of the output waveform of the output data. This effect is particularly great for data whose output waveform changes significantly, such as when checking data in a ROM when the present invention is applied to a calculator.
第１図は本発明の分割抵抗切換回路の一実施例のブロッ
ク図、第２図は本発明の分割抵抗切換回路の他の実施例
のブロック図である。
１．３，７．８・・・分割抵抗、２・・・液晶レベルセ
レクタ、４．９〜１１・・・切換用制御信号１．５・・
・液晶レベル選択用制御信号、６・・・トランスファー
ゲート。
代理人 弁理士 内 原 音１２゜
＼パ・
１も
拳２図FIG. 1 is a block diagram of one embodiment of the divided resistance switching circuit of the present invention, and FIG. 2 is a block diagram of another embodiment of the divided resistance switching circuit of the present invention. 1.3, 7.8...Division resistor, 2...Liquid crystal level selector, 4.9-11...Switching control signal 1.5...
-Control signal for liquid crystal level selection, 6...transfer gate. Agent Patent Attorney Oto Uchihara 12゜＼Pa・1 also fist 2
Claims (1)
数の電位をレベルセレクタにより選択して出力する分割
抵抗切換回路において、複数の前記第１の分割抵抗それ
ぞれに並列に接続されたスイッチと第２分割抵抗の直列
接続を含むことを特徴とする分割抵抗切換回路。In a dividing resistor switching circuit that selects and outputs a plurality of potentials obtained by dividing a potential between power supplies by a plurality of first dividing resistors using a level selector, a switch connected in parallel to each of the plurality of first dividing resistors; A dividing resistor switching circuit comprising a series connection of a second dividing resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2091587A JPS63188196A (en) | 1987-01-30 | 1987-01-30 | Slit resistance switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2091587A JPS63188196A (en) | 1987-01-30 | 1987-01-30 | Slit resistance switching circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63188196A true JPS63188196A (en) | 1988-08-03 |
Family
ID=12040518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2091587A Pending JPS63188196A (en) | 1987-01-30 | 1987-01-30 | Slit resistance switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63188196A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05100626A (en) * | 1991-10-07 | 1993-04-23 | Nec Corp | Semiconductor integrated circuit |
| JP2005037746A (en) * | 2003-07-16 | 2005-02-10 | Mitsubishi Electric Corp | Image display apparatus |
| JP2006326142A (en) * | 2005-05-30 | 2006-12-07 | Matsushita Electric Ind Co Ltd | Rice cooker |
| JP2008134496A (en) * | 2006-11-29 | 2008-06-12 | Nec Electronics Corp | Gradation potential generation circuit, data driver of display device and display device having the same |
-
1987
- 1987-01-30 JP JP2091587A patent/JPS63188196A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05100626A (en) * | 1991-10-07 | 1993-04-23 | Nec Corp | Semiconductor integrated circuit |
| JP2005037746A (en) * | 2003-07-16 | 2005-02-10 | Mitsubishi Electric Corp | Image display apparatus |
| US7375710B2 (en) | 2003-07-16 | 2008-05-20 | Mitsubishi Denki Kabushiki Kaisha | Image display apparatus having gradation potential generating circuit |
| JP2006326142A (en) * | 2005-05-30 | 2006-12-07 | Matsushita Electric Ind Co Ltd | Rice cooker |
| JP4604841B2 (en) * | 2005-05-30 | 2011-01-05 | パナソニック株式会社 | rice cooker |
| JP2008134496A (en) * | 2006-11-29 | 2008-06-12 | Nec Electronics Corp | Gradation potential generation circuit, data driver of display device and display device having the same |
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