JPS63187692A - Manufacture of circuit device - Google Patents
Manufacture of circuit deviceInfo
- Publication number
- JPS63187692A JPS63187692A JP1945287A JP1945287A JPS63187692A JP S63187692 A JPS63187692 A JP S63187692A JP 1945287 A JP1945287 A JP 1945287A JP 1945287 A JP1945287 A JP 1945287A JP S63187692 A JPS63187692 A JP S63187692A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- cream solder
- electrode portions
- electrode
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 59
- 239000006071 cream Substances 0.000 claims description 36
- 239000004020 conductor Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 description 4
- 238000001035 drying Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 244000145100 Capsicum baccatum var. baccatum Species 0.000 description 1
- 235000015855 Capsicum pubescens Nutrition 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、混成集積回路又はこれに類似の回路装置の製
造方法に関し、更に詳細には、リード接続電極部分の相
互間が半田によって短絡されろことを１υｊ止する方法
に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a hybrid integrated circuit or a circuit device similar thereto, and more particularly, the present invention relates to a method for manufacturing a hybrid integrated circuit or a circuit device similar thereto. Concerning the method of stopping the locoto by 1υj.
？従来の技術］
回路基板上に多数のリードを有するＩＣを接続する場合
に、導体層の電極部分を選択的に露出させろようにオー
バーコー！−ガラス層を設け、重陽部分にクリーム半田
を印刷し、クリーム半田を溶融し、同化することによっ
てリードを半田で接続することは既に行われている。? Prior Art] When connecting an IC having a large number of leads on a circuit board, an overcoat is used to selectively expose the electrode portions of the conductor layer. - It has already been done to connect the leads with solder by providing a glass layer, printing cream solder on the double positive part, melting and assimilating the cream solder.
［発明が解決しようとする問題点］
ところで、ＩＣ等の回路部品の小型化が進み、リードの
ピッチが０．８ｍｍ以下のフラットパック型ＩＣか出現
した。この種のリード間隔の狭いＩＣを回路基板にクリ
ーム半田によって接続すると、クリーム半田を溶融した
ときに半田が隣りの電極部分へ流れ、半田ブリッジが生
じることがある。[Problems to be Solved by the Invention] Incidentally, as circuit components such as ICs have become smaller, flat-pack type ICs with lead pitches of 0.8 mm or less have appeared. If this type of IC with narrow lead spacing is connected to a circuit board using cream solder, when the cream solder is melted, the solder may flow to the adjacent electrode portion, resulting in a solder bridge.
そこで、本発明の目的は、半田ブリッジが発生し難い回
路装置の製造方法を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a circuit device in which solder bridges are less likely to occur.
Ｅ問題点を解決するための手段］
上記問題点を解決し、上記目的を達成するための本発明
は、実施例を示す図面の符号を参照して説明すると、絶
縁層３によって区画されている複数の電極部分２８〜２
ｄの全部にクリーム半田を塗布せずに、夫々の一部にク
リーム半田４を塗布し、複数の電極部分２ａ〜２ｄのク
リーム半田塗′ｊ５領域を複数の電極部分２８〜２ｄの
配列方向においてジグザグに配置し、しかる後、クリー
ム半田４を溶融し、固化させることによって各リード７
を半田８で各電極部分２ａ〜２ｄに接続することを特徴
とする回路装置の製造方法に係わるものである。Means for Solving Problem E] The present invention for solving the above problems and achieving the above objects will be described with reference to the reference numerals in the drawings showing the embodiments. Multiple electrode portions 28-2
Cream solder 4 is applied to a part of each of the electrode parts 2a to 2d without applying cream solder to the entire part d, and the cream solder 5 areas of the plurality of electrode parts 2a to 2d are applied in the arrangement direction of the plurality of electrode parts 28 to 2d. Each lead 7 is arranged in a zigzag pattern, and then the cream solder 4 is melted and solidified.
This relates to a method of manufacturing a circuit device characterized in that the electrode parts 2a to 2d are connected to each other with solder 8.
［作用］
上記発明によれば、クリーム半田４が？Ｓ極部分２ａ〜
２ｄの全領域に塗布されないなめ、これを；容融させた
時に、クリーム半田非塗布部分５８〜５ｄの方向に半田
が流動し、電極部分２８〜２ｄの配列方向への半田の流
動が抑制され、半田ブリッジの発生が少なくなる。また
、クリーム半田４は複数の電極部分２ａ〜２ｄの配列に
対してジグ−”ｒりに塗布されるため、クリーム半田４
の塗布領域の相互の対向部分の長さが短くなるか又は零
になり、半田ブリッジの発生率が大幅に少なくなる。[Operation] According to the above invention, the cream solder 4? S pole part 2a~
2d is not applied to the entire area; when melted, the solder flows in the direction of the cream solder-unapplied areas 58 to 5d, and the flow of solder in the arrangement direction of the electrode areas 28 to 2d is suppressed. , the occurrence of solder bridges is reduced. Moreover, since the cream solder 4 is applied in a jig-like manner to the array of the plurality of electrode parts 2a to 2d, the cream solder 4
The lengths of the mutually opposing portions of the application areas are reduced or even zero, and the incidence of solder bridging is significantly reduced.
１実施例］
次に第１図及び第２図に基づいて本発明の実施例に係わ
る混成集積回路装置の製造方法を説明ずろ。1 Embodiment] Next, a method for manufacturing a hybrid integrated circuit device according to an embodiment of the present invention will be explained based on FIGS. 1 and 2.
まず、第１図（Ａ＞及び第２図（Ａ）に示す如く、アル
ミナセラミック絶縁基板１の上に銀パラジウムＡｇＰｄ
ペーストを印刷し、乾燥し、焼成ずろことによって導体
層２を形成する。なお、導体ｒ？ｉ２は、基板１上に取
り付けるフラットパックＴＩ′！ｌＣのリードを接続す
るための多数の電極部分２ ａ、 ２ ｂ、 ２ Ｃ，
２ｄと配線部分２ｅとを有する。多数の電極部分２８〜
２ｄは互いに平行に配置され呵冊状に延びている。First, as shown in FIG. 1 (A) and FIG. 2 (A), silver palladium AgPd was placed on an alumina ceramic insulating substrate 1.
The conductor layer 2 is formed by printing the paste, drying it, and baking it. In addition, the conductor r? i2 is a flat pack TI' to be installed on board 1! A large number of electrode parts 2 a, 2 b, 2 C, for connecting the leads of 1C,
2d and a wiring portion 2e. A large number of electrode portions 28~
2d are arranged parallel to each other and extend in a rectangular shape.
次に、図示はされていないが、厚膜抵抗体、クロスオー
バーガラス膜の形成、クロスオーバー配線導体の形成等
をなす。Next, although not shown, a thick film resistor, a crossover glass film, a crossover wiring conductor, etc. are formed.
次に、第１図（Ａ＞及び第２図（Ａ）に示す如く、オー
バーコートガラスペーストを印刷し、乾燥し、焼成する
ことによって絶縁層３を選択的に設ける。この絶縁層３
は電極部分２ａ〜２ｄを露出させ、配線導体部分２ｅを
被覆するように形成する。図面では電極部分２ａ〜２ｄ
に接触するように絶縁層３が設けられているが、電極部
分２ａ〜２ｄから少し離れるように設けても差し支えな
い。Next, as shown in FIG. 1 (A) and FIG. 2 (A), an insulating layer 3 is selectively provided by printing, drying, and baking an overcoat glass paste.
is formed so as to expose the electrode portions 2a to 2d and cover the wiring conductor portion 2e. In the drawing, electrode parts 2a to 2d
Although the insulating layer 3 is provided so as to be in contact with the electrode portions 2a to 2d, it may be provided a little apart from the electrode portions 2a to 2d.
次に、第１図（Ｂ）及び第２図（Ｂ）に示す如く、電極
部分２８〜２ｄの上に、５ｎ−Ｐｄ系又はＳｎ −Ａｇ
−Ｐｄ系半田合金粉末とフラックスとから成るクリーム
半田４をマスクを使用して印刷する。クリーム半田４は
、電極部分２８〜２ｄの全領域に印刷せずに、一部のみ
に印刷する。この結果、クリーム半田非塗布領域５ ａ
、 ５ ｂ、 ５ Ｃ，５ｄが各電極部分２ａ〜２ｄに
生じている。第１図（Ｂ）から明らかな如く、クリーム
半田４は、多数のｔｉ部分２ａ〜２ｄに対してジグザグ
に印刷され、クリーム半田非塗布領域５ａ〜５ｄもジグ
ザグに配置されている。今、２つの電極部分２ａ。Next, as shown in FIG. 1(B) and FIG. 2(B), 5n-Pd-based or Sn-Ag
- Cream solder 4 made of Pd-based solder alloy powder and flux is printed using a mask. The cream solder 4 is not printed on the entire area of the electrode portions 28 to 2d, but only on a portion thereof. As a result, cream solder non-applied area 5 a
, 5b, 5C, and 5d are generated in each electrode portion 2a to 2d. As is clear from FIG. 1(B), the cream solder 4 is printed in a zigzag pattern on a large number of ti parts 2a to 2d, and the cream solder non-applied areas 5a to 5d are also arranged in a zigzag pattern. Now two electrode parts 2a.
２１１におけるクリーム半田４の塗布のパターンを比叙
すると、電極部分２ ａ、 ２ ｂが延びる方向の上部
においては一方の電極部分２ａにクリーム半田非塗布領
域５ａが設けられ、中央部においては両方の主峰部分２
ａ、 ２ ｂにクリーム半田４が塗布され、下部にお
いては他方の電極部分２ｂにクリーム半田非塗布領域５
ｂが設けられている。To illustrate the pattern of application of the cream solder 4 in 211, one electrode part 2a is provided with a cream solder non-applied area 5a at the upper part in the direction in which the electrode parts 2a, 2b extend, and in the center part, both of the electrode parts 2a and 2b are provided with a non-application area 5a. Main peak part 2
Cream solder 4 is applied to a and 2b, and a cream solder non-applied area 5 is applied to the other electrode portion 2b at the bottom.
b is provided.
次に、第１図（Ｃ）及び第２図（Ｃ）に示す如くフラジ
１−バック型ＩＣ６のリード７を各電極部分２８〜２ｄ
のクリーム半田４の上に置き、クリーム半田４を例えば
２３０℃で加熱溶融し、固化させることによって半田８
で各リード７を各電極部分２ａ〜２ｄに接続する。第１
図（Ｂ）のパターンに塗布されているクリーム半田４を
溶融させると、溶融半田は半田？Ｍれ性の良いクリーム
半田非塗布領域５８〜５ｄの方向に流れ、クリーム半田
非塗布領域５ａ〜５ｄが半田８で被覆された状態になる
。この様に溶融半田がクリーム半田非塗布領域５ａ〜５
ｄの方向即ち各電極部分２ａ〜２ｄが延びている方向に
流動すれば、この方向に直交する方向く電極部分２８〜
２ｄの配列方向）への溶融半田の流動が制限され、電極
部分２８〜２ｄの相互間の半田ブリッジは、極端に少な
くなる。Next, as shown in FIG. 1(C) and FIG. 2(C), the leads 7 of the flange 1-back type IC 6 are connected to each electrode portion 28 to 2d.
solder 8 by heating and melting the cream solder 4 at, for example, 230°C and solidifying it.
Each lead 7 is connected to each electrode portion 2a to 2d. 1st
When the cream solder 4 applied to the pattern in figure (B) is melted, is the molten solder solder? It flows in the direction of the cream solder non-applied areas 58 to 5d with good M resistance, and the cream solder non-applied areas 5a to 5d are covered with the solder 8. In this way, the molten solder is applied to the cream solder non-applied areas 5a to 5.
If it flows in the direction d, that is, in the direction in which each electrode portion 2a to 2d extends, the electrode portions 28 to 2d flow in a direction perpendicular to this direction.
The flow of molten solder in the direction of arrangement of electrode portions 28 to 2d is restricted, and solder bridges between electrode portions 28 to 2d are extremely reduced.
この効果を調べるために、各電極部分２ａ〜２ｄの寸法
を０．４ ｍｍＸ２．０ ｔｐｍ、＠、極部分２８〜２
ｄの相互間隔を０．４開、クリーム半田４の塗布領域を
０．４關ＸＬ４＋ｎ＋ｎ、クリーム半田非塗布領域５ａ
〜５ｄを０．４ ｍｍ Ｘ ０．６ ｍｍ、ＩＣ６のリ
ード７の数を１２本２列、リード７のピッチを０．８閾
として、リード７を半田接続におけるリード７相互間の
半田ブリッジ即ち短絡の発生を１００個のＩＣ６につい
て調べた。この結果、１００個のＩＣ６の合計２４００
本のリードにおいて生じた半田ブリッジの発生は１箇所
であった。従って、嘔位ビン当りの半田ブリッジの発生
率は約０．０４％である。一方、第１図（Ａ）の電極部
分２８〜２ｄの全部に半田クリームを塗布してＩＣ６の
リード７を接続し、半田ブリッジの発生を同−粂件で調
べたら、約５％であった。In order to investigate this effect, the dimensions of each electrode portion 2a to 2d were set to 0.4 mm x 2.0 tpm, @, and the polar portions 28 to 2
The mutual spacing of d is 0.4, the area where cream solder 4 is applied is 0.4 x XL4+n+n, and the area where cream solder is not applied is 5a.
~5d is 0.4 mm x 0.6 mm, the number of leads 7 of IC6 is 12 in 2 rows, and the pitch of leads 7 is 0.8 threshold, and the leads 7 are connected by solder bridges between the leads 7. The occurrence of short circuits was investigated for 100 IC6s. As a result, the total of 100 IC6 is 2400
There was only one solder bridge that occurred in the lead of the book. Therefore, the incidence of solder bridges per bottle is approximately 0.04%. On the other hand, when we applied solder cream to all of the electrode parts 28 to 2d in Figure 1(A) and connected lead 7 of IC6, we investigated the occurrence of solder bridges in the same case, and found that it was approximately 5%. .
Ｕ変形例コ
本発明は上述の実施例に限定されるものでなく、変形可
能なものである。例えば、電極部分２８〜２ｄを囲む絶
縁層３をクロスオーバーガラスによって形成してもよい
。また、クリーム半田非塗布領域５ａ〜５ｄの長さＸを
変えても差し支えない。U Modification The present invention is not limited to the above-described embodiment, but can be modified. For example, the insulating layer 3 surrounding the electrode portions 28 to 2d may be formed of crossover glass. Further, the length X of the cream solder non-applied areas 5a to 5d may be changed.
イリし、この長さＸｏ、３ｚｍ以上であることが望まし
く、且つ電極部分２８〜２ｄの全長の半分以下であるこ
とが望ましい。また、ＩＣのリード以外のリードの接続
にも適用可能である。This length Xo is desirably 3zm or more, and desirably less than half of the total length of the electrode portions 28 to 2d. It is also applicable to connections of leads other than IC leads.
［発明の効果］
上述から明らかな如く、本発明によれば、電極部分の相
互間の方向の半田の流れを抑制し、半田ブリフジの発生
を阻止することができる。[Effects of the Invention] As is clear from the above, according to the present invention, the flow of solder in the direction between the electrode portions can be suppressed, and the occurrence of solder blobs can be prevented.
第１図（Ａ）（Ｂ）（Ｃ）は、本発明の実施例に係わる
回路装置の一部を製造工程順に示す平面図
第２図（Ａ）（Ｂ）（Ｃ）は、第１図（Ａ）（Ｂ）（Ｃ
）のＡ −Ａ線、Ｂ−Ｂ線、Ｃ−Ｃ線の断面図である。
１・・・基板、２・・・導体層、２８〜２ｄ・・・電極
部分、３・・・絶縁層、４・・・クリーム半田、５ａ〜
５ｄ・・・クリーム半田非塗布領域、６・・・ＩＣ１７
・・・リード、８・・・半田、
代 理 人 高 野 則 次手続補正書
（自発）
昭和６２年９月１１１（
持訂庁長冒 ７ｊ、）１１，３カ 殿 ｉ、ｉ
′；’、１１ １１件内表示
昭和６２ 年 特 許 に〔ｌ 第１９４５２
３２、発明の名称 回路装置の製造方法３ｈ１１止を
ｒる名
・１田との関係 出願人1(A), 2(B), and 2(C) are plan views showing a part of a circuit device according to an embodiment of the present invention in the order of manufacturing steps. (A) (B) (C
) is a sectional view taken along line A-A, line B-B, and line C-C. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Conductor layer, 28-2d... Electrode part, 3... Insulating layer, 4... Cream solder, 5a-
5d... Cream solder non-applied area, 6... IC17
...Reed, 8...Handa, Agent Norihiro Takano Next Procedural Amendment (Voluntary) September 111, 1986 (Revised by the Director of the Revision and Revision Agency 7j) 11, 3 Lords i, i
';', 11 Displayed in 11 1986 Patent [l No. 19452
32. Title of the invention: Method for manufacturing circuit devices 3h11 Name/Relationship with 1 Applicant
Claims (1)
電極部分に連続している配線部分とを有する導体層を絶
縁基板上に設け、少なくとも前記電極部分に隣接する配
線部分の上に絶縁層を設け、前記電極部分にクリーム半
田を塗布し、前記クリーム半田を溶融し、固定すること
によつて複数のリードを前記複数の電極部分にそれぞれ
半田で接続することを含む回路装置の製造方法において
、前記クリーム半田を前記電極部分の全領域に塗布せず
に一部分に塗布し、前記複数の電極部分の各クリーム半
田塗布領域を前記複数の電極部分の配列方向にジグザグ
に配置ことを特徴とする回路装置の製造方法。(1) A conductor layer having a plurality of lead connection electrode portions parallel to each other and a wiring portion continuous to the electrode portions is provided on an insulating substrate, and an insulating layer is provided on at least the wiring portion adjacent to the electrode portions. A method for manufacturing a circuit device comprising: providing a plurality of leads, applying cream solder to the electrode portions, melting and fixing the cream solder, and connecting a plurality of leads to the plurality of electrode portions with solder, respectively; A circuit characterized in that the cream solder is not applied to the entire area of the electrode portion but to a portion thereof, and each cream solder application area of the plurality of electrode portions is arranged in a zigzag manner in the arrangement direction of the plurality of electrode portions. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1945287A JPS63187692A (en) | 1987-01-29 | 1987-01-29 | Manufacture of circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1945287A JPS63187692A (en) | 1987-01-29 | 1987-01-29 | Manufacture of circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63187692A true JPS63187692A (en) | 1988-08-03 |
Family
ID=11999709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1945287A Pending JPS63187692A (en) | 1987-01-29 | 1987-01-29 | Manufacture of circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63187692A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0269992A (en) * | 1988-09-05 | 1990-03-08 | Fujitsu Ltd | Method of soldering lead of surface mounting part |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6212982B2 (en) * | 1978-12-11 | 1987-03-23 | Nisshin Flour Milling Co |
-
1987
- 1987-01-29 JP JP1945287A patent/JPS63187692A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6212982B2 (en) * | 1978-12-11 | 1987-03-23 | Nisshin Flour Milling Co |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0269992A (en) * | 1988-09-05 | 1990-03-08 | Fujitsu Ltd | Method of soldering lead of surface mounting part |
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