JPS63187354A - Memory controller - Google Patents

Abstract

PURPOSE:To easily perform error correction, by using the same error check and correct (ECC) code for the fetch data of an intermediate buffer (WS) and that of a main memory (MS). CONSTITUTION:When a data is transferred from the MS3 to the WS2, an MFD data line 21 is selected by a selector 30, and the data is stored in a WFDR latch 11, and passes an ECC circuit 4, and if a one bit error exists in the fetch data from the MS3, the error correction is performed, and a corrected data is stored in a WSDR latch 13, and it is stored in the WS2 by passing through a WMSD data line 20. Also, when the data is swapped out from the WS2 to the MS3, a WFD data line 22 is selected by the selector 30, and the data passes through the ECC circuit 4, and when the one bit error exists in the fetch data of the WS2, the error correction is performed, and the data is stored in the WSDR latch 13, and it is stored in the MS3 by passing through the WMSD data line 20.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a storage control device, and particularly to an error check and correction method for upper, middle, and lower memories in which the storage layer is not formed. This invention relates to a storage control device that can be shared and has improved reliability.

[Conventional technology]

A conventional device is a storage control device that forms a storage hierarchy by main memory, intermediate buffer, and lower, neutral, and upper memory of buffer storage. and store it in the intermediate buffer at the same time,
A one-way store-through system is adopted. Also, when storing data between the intermediate buffer and the main memory, the reason why the data is stored only in the intermediate buffer and stored in the main memory is that the corresponding block is
It uses the scrubbing method, which is used only when it is written out to main memory. As this type of device, for example, Japanese Patent Application Laid-Open No. 52-55
555 and Nikkei Electronics, General Purpose Large Computers, (May 31, 1982), by Toshio Hiraguri, Seijibu Ueno, and Takamitsu Tsuchimoto, "Large-sized computer with improved performance using three-layer memory system and high-density technology. computer M
-58013824 (P581-399).

[Problem that the invention seeks to solve]

In such a storage control device, the latest data is held in the intermediate buffer, and in order to improve the reliability of the intermediate buffer, a Hamming code error check and correct (ECC) function is provided.

Conventional storage control devices either have separate ECC circuits for the intermediate buffer and main memory, or perform error correction using ECC only when data is transferred from the intermediate buffer to the backup storage. No error correction was performed when writing data from the intermediate buffer to the main memory or from the intermediate buffer to the main memory.

Such a conventional device is shown in FIG. 1 is a buffer storage (hereinafter abbreviated as BS), 2 is an intermediate buffer (hereinafter referred to as WS)
), 3 is a main memory (hereinafter abbreviated as MS), 4 is an error check and collect circuit (hereinafter abbreviated as ECC circuit), 10
is the woDa latch for sending data to the BSI after passing through the ECC circuit 4, and 11 is the WF'J) R latch for storing data fetched from WS2. is sent to the ECC circuit 4, and when sent to the MS3, it is sent as is.

12 stores data fetched from MS3, M
It is an SDR latch. 23 is WF'f)R, latch 1
This is an MSD data line that sends data of 1 Y M 8.5. In the conventional storage control device, when data is sent from WS2 to BS1, it passes through the ECC circuit 4 and contains 1 in the data.
If there was a bit error, it was corrected and sent to BSl, but when sending data from MS3 to WS2, ECC is used.
Without creating a circuit equivalent to circuit 4, use WS as is.
I was writing data to 2. Also, from MS5 to WS2
In order to transfer data 2 to WS2, the free space Jj
l! In order to ensure security, the data in the WS is selected using a certain algorithm, and if there is a history that the data has been stored and changed in the past, it is dumped out to the MS6, but at that time, the ECC circuit 4 Does not pass rA85
Go straight to MS6.

4 I'm deeply involved. In this way, conventional storage control devices
Even if there is an error in MS3 or WS2, continue with W.
Because it is written to S2 or 1Vis5, WS
Since the rate at which a 1-bit error occurs in the MS increases greatly, and the rate at which a 1-bit error occurs at the MS also increases, the 1-bit robustness decreases accordingly. Also, the error that occurred in WS2, or MS
Since it is not possible to determine whether the error occurred in step 3, I do not know which B or A MY should be replaced.

There are also examples where the ECC circuits on each side are waited for by the intermediate buffer and the main memory.

This conventional device is shown in FIG.

Items with the same numbers as in Figure 2 are the same as in Figure 2.4
・ Pickles. 5 is the ECC circuit of MS5, and 16 is the WS2.
It is a WSDR launch for sending data to MS6,
Even when transferring data from WS2 to MS3, from MS3 to WS2
In order to perform error correction during data transfer to the ECC circuit 5, it is necessary to increase the /%-dore of the ECC circuit 5.

An object of the present invention is to easily correct errors using ECC when writing data that has been etched from main memory to an intermediate buffer and when writing data from the intermediate buffer to main memory.

[Failure to solve the problem]

The above object is achieved by sharing the ECC code used in the intermediate buffer and the main memory and by using the same ECC circuit.

[Effect]

In the present invention, the ECC1 path used in the intermediate buffer is directly applied to fetch data from the main memory, and error correction is performed both when writing from the main memory to the intermediate buffer and when writing from the intermediate buffer to the main memory. By doing this, No.1
- A highly reliable storage control device can be easily provided without a large increase in hardware.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

In FIG. 1, BS1, WS2. MS3. ECC circuit 4. W
ODR latch10. WFDEL latch 11 is the same as in FIG. 13 is a WSDR launch for sending data after passing through the ECC circuit 4 to WS2 or MS3; 20 is a WSDR launch for sending data from the WSDR latch 13 to WS2 or MS3;
2. The WMSD data line 21 for sending to MS3 is
MF I) Data line, 22, sends the fetch data from MS3, WIl sends the 7 ENT data from WS2.
The i'D data line 30 is a selector.

When transferring data from WS2 to BS+, it is the same as explained in FIG. If there is a 1-pit error in the data fetched from MS5, the error is corrected, the corrected data is stored in the WSDR latch 16, and the WMSD
Data line 20 is passed through and stored in WS2. Also vVs
When swapping out data from 2 to M83, select WF'D data data 22 with selector 30, and
If there is a 1-bit error in the fetch data of WS2 through the circuit 4, the error is corrected and the WSDR,
Data is stored in the latch 13, passed through the WMSD data line 20, and stored in the MS3.

〔Effect of the invention〕

As explained above, according to the present invention, by using the same ECC code for WS fetch data and MS fetch data, 800 circuits can be shared, and MS
When transferring data from the WS to the MS, and when swapping out data from the WS to the MS, error correction using ECC can be performed with a small amount of hardware, increasing the reliability of the storage control device. In addition, it is possible to easily identify whether a failure occurred in the WS or MS.
7. There is an effect that can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a storage control device showing one embodiment of the present invention. FIG. 2 is a block diagram of a conventional storage control device. FIG. 3 is a block diagram of another conventional storage control device. 1... Buffer storage (BS), 2, +4
+ Buff 7a (WS), 6... Main memory (MS), 4
...Error check and collect (ECC) circuit,
10-WODRraychi, 11-WPDRuyf
, 12-M F D R y +, 13-WSDR y
f, 2°...WMSD data line, 21...MFD data line, 22...WFD data line, 60...Selector.

Claims (1)

[Scope of Claims] 1. In a storage control device in which a storage hierarchy is configured by a main memory, an intermediate buffer, and a buffer storage, (1) either fetch data from the intermediate buffer or fetch data from the main memory is (2) an ECC that performs error correction and indication according to an arbitrary Hamming code without distinguishing whether the selected data is fetched from an intermediate buffer or from main memory; (3) a first bus for transmitting the error-corrected data to the buffer storage and a second bus for transmitting the error-corrected data to the intermediate buffer; (4) transmitting data from the main memory to the intermediate buffer. A storage control device characterized in that the third bus is selected when data is transferred from the intermediate buffer to the main memory, and the second bus is selected when data is transferred from the intermediate buffer to the main memory.