JPS5816362A - Controller for double shared memory - Google Patents

Abstract

PURPOSE:To increase greatly the reliability of a system, by using a changeable storage means in each processor and fetching either one of the systems by the on-/off-mode of the storage means. CONSTITUTION:A storage means which can be set and reset by a program or another means is set in each memory expander 4 or CPU3, and the transmission of either one of both reading data to the CPU is decided by the on-/off-mode of this storage means when these two reading data are normal. In such way, some group of plural CPUs 3 uses the data of a shared memory M1 with priority, and the rest groups of CPU3 use the data of a shared memory M2 with priority respectively. As a result, the breakdown of all CPUs can be avoided although the errors occur frequently at a single system sharing memory for the data to which the detection of error is impossible.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for duplex shared memory between multiple processing devices.

First, an example of the overall configuration of a multiple processing device including a dual shared memory, which is the premise of the present invention, will be described with reference to FIG.

No. 18 ii) includes four processing units 8 (CPUI to CPU
4) is a duplicate shared memo! 71 (Ml, M2) t-shared configuration, the processing device 3 (hereinafter referred to as CPU) has connection mechanism 4 (MEI to MB4) with shared memory 1 (hereinafter referred to as memory expander) t- However, the shared memo +71 is a processing unit installed corresponding to each CPU.
P4: hereinafter referred to as port). In FIG. 1, only one reference numeral is given to the same configuration. For example, for CPU4 from C to H, %C
The code 3 is attached to PU1, and no code is attached to CPU2 to CPO4, and the same applies to other parts.

Therefore, in the following explanation, when CPU5 is used,
Let CPUI to CPU4 be representative.

The memory expander 47 and ports 2 of both shared memories are connected to the shared memory-CPU interface 5, and each CPU connects the memory expander 4 and the shared memory ports 2 to the shared memory-CPU interface 5.
5 inter-PU interfaces! Data is transferred to and from the shared memory via the shared memory.
Shared memory sharing method 4 View interface 6
PII is connected and both shared memories are synchronously created. Each CP
U has a crowd path γ, operates various input/output devices 9, and uses a 020 communication path 8 to perform mutual interrupt communication and mutual monitoring.

In such a system configuration, memory expander 4
As shown in the internal configuration tsgz diagram, receives address A1 write data WDt- from 10Pυ and transfers both shared memory memory M1. Address A1 write 2, write data WD1 . Sends WD2 through In/-7 Eighth 5.5', and outputs data RDI and RD from both shared channels.
2 received and checked, the normal data RDtCP
Send to U. At this time, the data RDI of both systems.

There are 9 cases in which RD2 is normal with no error detected, but the two data are different (if a 1-bit parity check is performed, a 2-bit error is considered normal), as shown in Figure 2. , 10 is an address buffer,
1lrj: write data buffer, 12: bladder ejection data selection circuit, 13° 13': bladder ejection data buffer, 14
．． Reference numeral 14' denotes a continuous output data selection circuit, and 15 represents an output of the output data selection circuit.

Typical specific examples of conventional read data selection circuits are shown in Figures 3 and 4. Figure #I3 shows that if both systems are normal, the data is ORed and the
The 0 and 0 systems that are used to send data to the PU are called the l and z systems, respectively. :KI, % Continuous data from 1 system 14t Error detection circuit tgK checks the data, and if there is an error, Kai i detects 1 system timeout error 25 tf
l system Esiera - detection signal 17, 0 data 1 from l system
4 is inhibited and sent to the CPU, and the same applies to the 2nd system.In the 0 line method, even if data m6 is not detected by the error detection circuit 16, the CPU can detect an error by ORing the same data). Although it is possible to improve the quality of the system, if one system 0 shared memory fails in the addressing system and the timing system fails], if data errors that cannot be detected by an error detection circuit such as ζO occur repeatedly, all CPUs will go down. becomes.

In the 4th m, if both systems are normal, the predetermined data [-CPUK] is sent.If the predetermined shared memory is slow to detect an error and data g * nt is generated one after another, all CPUs This results in the downtime. Recently, C)CPU usage is such that when it goes down, it is often impossible to back it up manually.On the other hand, in order to improve reliability in such systems, CPU full duplex system, input/output O synchronization, Every consideration has been made to ensure that the system does not go down even if one CPU performs an incorrect calculation, such as consistency checking, rationality checking, and mutual diagnosis. It is undesirable for all 0 CPUs to go down just because of a failure.

The purpose of this invention is to provide a duplex shared memory control device II that prevents all CPUs from going down when such an undetectable data error p occurs in a single shared memory.

Features of the present invention As shown in Figure 5, each memory expander (in some cases, each C5Pυ) has a memory means (7 bits for priority selection) that can be reset by a program or some other means. 20),
Both systems! If the output data is normal, which tCPU to send to is determined by turning on/off this storage means. By doing this, some of the 0 CPU groups in multiple CPU 0 preferentially use the data of the shared memory 1 system, and the remaining pOcPU evaluation preferentially uses the data of the shared memory 2 system, so that one system Even if undetectable data WA errors occur one after another in the shared memory, all CPUs can be prevented from going down.

An embodiment of the present invention will be described with reference to gsg to 12th WJt.

Figure 6 shows CPU5 (including Mesori Exbander 4t)
This shows the configuration of CPU internal bus leg restraint device 1 (
BC) intra-CPU path 2faKti controlled by 30,
Memory expander (MJi: ) 4, memory control unit (MCυ) 28, basic computing unit all (BPU) 32,
An input/output control mechanism (IOP) 33 is connected. The memory front gear unit 28 stores programs and data dedicated to its CPU, and controls nine main points. Basic computing machine #
0, input/output controller 11133 to which optional machine #I such as floating point arithmetic unit (PPP) 31 is connected to 1lB2.
The memory expander 4 controls the input/output capacitor and transfers data between the input/output pin and the main memory or the shared memory via the two shared memories and the CPU interface 6. Shared memory Ml, M2 and I! be done. Main memory 27 and shared memory l (Ml,
M and D are distinguished by memory address, 41m!
Memory addresses greater than or equal to the memory address are allocated to shared memory.

FIG. 7 shows the configuration of the shared memory 1 (including ports). The shared memory path 36 controlled by the shared memory bus control device 37 includes the memory control device 3!
s1 port 2 is connected. The memory control device 3s controls a memory 34 that stores shared data among multiple CPUs. 2 (Pi-P4) is connected to CPUI-4 via a shared memory-CPU interface st.

The shared memory path control device 37 is connected to the shared memory path control device of the other system shared memory (not shown) via the shared memory interface 7 and the shared memory interface 6, so that the shared memory of both systems can be connected at the same time. Synchronization control is performed to perform data transfer with the KIfIiI constant 0 CPU.

@fHIJB Memory expander 40 configuration 〇-I have shown an example, so I will give it to you. The address comparison path 44 detects whether or not the four addresses of the paths within CPυ are shared memory addresses (addresses greater than or equal to 41 are allocated to the shared memory), and the shared memory address is When the memory start signal 4I49 is received, the share memory start signal 46 turns on, and the address person, data WDt address/
(7A 1G% write data pack ll IC is set and address 38 (A1.A
2), write data 81 (WDI - WD2)% activation signal 40 (RIQl, REQi) t-! ! Output 0
Both systems shared memory Ml, M! Maybe, a series of data 41 (a
pl, iDg), response signal 42 (ANSI.

The program N82F sets the data in the WR output data buffers 1B and 13' and activates the response control circuit 43. The response control circuit 43 is a shared mail order 9M for both systems.
1. When the responses from M2 are complete, the response @-It! $2 is returned to the basic calculation mechanism 32 and input/output control mechanism 33 via the CPU internal bus 29. At this time, l! The outgoing data selection circuit 12 selects the data in the above-mentioned manner and outputs the data of either of the nine systems as the successive outgoing data 50. Also,
The response control circuit 43 performs a timeout error check aS.
1l system time act error detection signal 25. 2 system timeout error detection signal 26t is output to the data selection circuit 12. When the data selection circuit 12 detects an error in both system data, an error signal (ERB) is output. ) 51 is replied along with a response signal (AN8) 52.

The read data selection circuit 12 is provided with a priority selection block flop, which will be described later, and its rewriting requires that the register address taico ADDR>54 become the O register address for the block 70.
When the register address decoding circuit (DECODE) 45 detects the register write signal (Rli:G
WRITE ) 55 is turned on, register day! (REGDATA) Set when the specific hit of 5B is @l'', and reset when ``o''o.

The detailed configuration of the read data selection circuit 120 is shown in FIG. From the sharing of both types! The data 14.14' output and set in the bladder output data buffer 13゜13' in the memory expander is detected by an error detection circuit 16.18.
The error will be checked. If there is an error in error check, or timeout error detection signal -9
When 25 and 26 are on, read data error is detected, output signals 17 and 19 are on, and the system O data t-CPU
Prohibit sending data to the other system and send data from other systems to the CPU 0 If both systems are normal, select priority 7 Lip 7 Lock Z
Either the read data 1 priority selection signal 21 or the continuous output data 2 priority selection signal 22, which is the output of oo, is sent to the data t-CPU. When both systems have an error, the read data error signal (ERR) 20 for both systems is turned on.

The priority selection flip 70 knob 100 has its set signal 2
4 turns on and is rewritten as 9, and the data signal 23 becomes 1.
1", the successive data 1 selection signal 21 is on, the successive data 2 selection signal 22 is off, and the data signal 2 is turned on.
The opposite is true when 3 is @O”.

The configuration of the response control circuit 43 is shown in FIG.

Among the responses from the shared memory for both systems, when the response signal (AN81) 5 of the 1st system Ml is sent back, the 1st system Ml response memory circuit 56
7 times and 2 system timeout inspection a$115
G is started, and if there is no 01t2 system M20 response signal 5', a timeout is detected and the %2 system timeout detection circuit 6
1 is set and the 2nd system timeout error signal 26 is turned on, but if the 2nd system response signal 5' is returned within the specified time, the 2nd system timeout detection circuit 59 is reset and the response signal 52 is turned on. Turns on. CPU responds with response signal 5
If 2t- is received, the activation signal is turned off, so the shared memory activation signal 46 is also turned off.
ζi storage circuits 56, 57. Timeout circuit 60.61
is reset to its initial state.

Next, the configuration of the port 2 is shown in FIG. 10. When the activation signal (REQ) 40 from the memory expander 4 is turned on, a path occupation request signal (B - Rli:Q
I) Turn on 64. The path control circuit 30 prioritizes the request signals from each port and outputs a path occupancy permission signal (B4ELt) 65 to the nine selected ports. When the port 2 receives this signal, it puts the address and write data on the shared memory path, sets the memory activation 7 lip 69, and outputs the memory activation signal 66 as its output to the shared memory path 36. After the memory write or read operation is completed, the threading data (RD) $7,
A response signal (AN8) 68 is returned via the shared memory path 36t, so it is sent to the memory expander 4, and the response signal 68 resets the memory activation 7 flip-flop 69t.

The various parts of the embodiment have been described above. FIG. 11 shows a time chart for memory access, and FIG. 12 shows a time chart for rewriting the priority selection tree flop lOo. Note that both are interlocked in the program so that they are not performed at the same time.

Next, an example of how to control the priority selection alli-lag flop 100 in this embodiment will be described with reference to FIGS. 13 and 14.

No. 1311 is for a two-CPO system, (A) shows the state when all 0 devices are normal, CPU1 turns on the built-in priority selection alli-lag flop, and outputs the indulged data in the l-system shared memory Ml. The CPU 2 also turns off the built-in priority selection 7 lip-flop and uses the output data from the 2-system shared memory M2. CPUI is for large-scale business, C
It is assumed that PU2 is carrying out the work of system B, and that the system will not go down in order to ensure that either of the services can continue. In the figure, a solid line indicates that read data is used, and a broken line indicates that continuous data is not used. In addition, Ml @ failure and M2 minor failure occur when a detectable error occurs in the memory expander. In this case, as shown in (B) and (C), the data in the shared memory of the correct system is used, so
There is no effect.

In addition, Mt major failure and M2 major failure occur when an undetectable error occurs in the memory expander. In this case, the CPU using the data performs self-rationality check, mutual diagnostic check, etc. Detects an abnormality and shuts down. However, since the CPUs of other systems do not use the data in the memory where the major failure occurred, they can continue their work as shown in (D) and (E), respectively.

FIG. 14 shows a case where there are three CPUs, one of which is a standby system. In this case, minor failures and major failures in the shared memory are almost the same as in the case of 0CP02 units in Figure 13, but the CPU
If the system fails, the following system reconfiguration is possible by utilizing the fact that the priority selection flip-flop program is rewritten. Now, Figure 14 (
In A), when CPU2 goes down due to a failure, C
PUa detects that CPU2 is down through mutual monitoring and starts backup tS, but at this time, it checks which side of the shared memory is prioritized by CPU2 (this information is stored in O8 on the main memory of each CPU). (It is stored in the configuration pipe layer table.) In the case of this figure, the 2-system shared method 401 is selected as a priority, so the CP! By turning off the priority selection flop of 8 itself and using the data of 2-system shared memory @: 9M2, it is possible to reconfigure the system exactly the same as before the failure, as shown in Figure 14 (B). . When the CPU fails, the situation is as shown in FIG. 14(C).

Figure 14 (A) shows the O procedure when the OCPU is 2/7. If you were to be more careful, the CPU2 might have gone down due to a serious failure in the 2nd system shared memory M2, so first reconfigure the system using the data in the 1st system shared memory M1, then run the shared memory M2t-diagnosis. After that, it is also possible to switch to using the contents of the shared memory M2.

FIG. 16 shows another embodiment of the present invention, which differs from FIG. 5 in that a clip 70 for specifying a dual-system data OR method that can be rewritten by a program is added. This dual-system data-OR method specified alli-lag flop 70
By turning on, it is possible to OR the data of both systems and send it to the CPU when both systems are normal, as in the conventional example shown in FIG. Since CPUK checks the data sound, if the data of both systems is different, an error is detected and the process is stopped. Depending on the usage situation, it may be very difficult for the data to be taken into the processing device, and it is suitable for situations where it would be better to stop all the processing devices.

FIG. 17 shows yet another embodiment of the present invention. Switch 7sK on the priority selection flip 70 knob in the memory expander, which determines which shared memory data is used.
[69 if it is a good replacement, 1 when switch 73 is on
Shared notes! jM1t,.

Share 2 types when you are off! JM2t-Select. To install this switch at the operator's hand, Operator 04
It can be switched in one turn. As described above, according to the present invention, data ll! is stored in one system of the duplex shared memory. At the time of output, even if data Ill of the error detector occurs one after another, all CPUs can be prevented from going down. Furthermore, according to the present embodiment, even when backing up a CPU after a failure, the system configuration can be the same as before the failure, and the reliability of the system can be greatly improved.

[1110 Brief explanation iml is an overall configuration diagram of a plurality of processing devices including a general duplex shared method 9 which is a premise of the present invention, and No. 31a is a shared memory in the processing device which is a premise of the present invention @0. The configuration diagram of the peak connection mechanism, FIGS. 3 and 4 are the configuration diagrams of the conventional example of the 2nd rxto dual-system read data selection circuit, and FIG. 61 is the embodiment of the present invention of the dual-system read data selection circuit. Figure, Figure 6 ~ Iris 10
The figures are configuration diagrams of specific embodiments of each part applied to this Jjl light, the first intention is a time chart for explaining the operation of the present invention), and Figures 5 to 1513 are diagrams showing the use of the present invention. 16 and 17 are diagrams showing other embodiments of the present invention corresponding to FIG. 5.

1--Duplicated shared memory, 2--Shared memory processing device connection device l11 (boat), 3--Processing device (CPU
), 4... Processing device side shared memory connection device all (memory expander), 5... Shared memory to processing II device viewing interface, 12... Enthusiasm data selection circuit, 1
00...Priority selection 7 lipfrog.

Agent Patent Attorney Masamisaya Akimoto 5 Figure sz 2 - CPc/t CP(/2 0PU5C
F (/4th Figure 8 Early 77th !3 Country (C) (δ
)(A)

Claims (1)

[Claims] 1. It is composed of multiple OtS processing devices and a duplexed shared memory that is commonly accessed by the multiple OtS processing devices, and each processing device reads data from both systems of the duplicated shared memory and processes each data. 2-In a dual shared memory control device that performs a check and imports normal data into the processing device, a storage device that can be changed by a program or other means is provided in the winter storage device, and the storage device is on·
Depending on the off content, determine which data to import into the processing definition when both system data are normal, and select multiple processing [Ito
A duplex shared memory control device characterized in that some of the processing devices take in data from the shared memory of one system, and the remaining noisML devices take in data from the shared memory of the other system.