JPS63186335A - Structure of computer - Google Patents

Abstract

PURPOSE:To omit an external mechanism which supplies interruptions and to simplify the software for the structure of a computer, by adding an interval timer to a register in a CPU and loading the value in response to a task switching mechanism of hardware. CONSTITUTION:A count register 11 serving as an interval timer is added to a register 8 in a CPU. When a task switching action is carried out, the value which is saved into an area 8a shown by the present value TR of the register in the CPU in the form of a hardware mechanism and held by a table 9 shown in a table 10 is used as the new register value. In this case, the register 11 is also replaced with the new value. The register 11 performs an automatic count-down action as the time elapses and the task is automatically switched to another task shown by the data on an area 13 at a time point when the value of the register 11 is equal to 0. Thus the periodical external interruptions are omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application]' This invention relates to a computer structure equipped with an execution time management function.

[Conventional technology]

FIG. 3 is a block diagram showing the hardware configuration of a conventional conventional electronic computer. In the figure, 1 is a programmable device that can control the signal generation interval by a program.
The timer 2 is a programmable pull interrupt controller that receives the signal generated by the programmable timer 1 as an interrupt signal; 3 is an l-step central processing unit (hereinafter referred to as CPU); and 4 is an interrupt selector. .

Here, programmable fist timer 1. The programmable interrupt controller 2 and the CPU 3 are connected to a common bus, and the programmable timer 1 and the programmable interrupt controller 2 are connected to each other via the interrupt selector 4 and to the programmable interrupt controller 2.
and CPU3 are directly connected. FIG. 4 is a block diagram showing a typical software configuration of the portion of the basic software that performs task management. In the figure, 5 is an interrupt processing section activated by a -interrupt signal, 6 is a task control section that determines the task to be activated next), and 7 is a dispatch section that actually performs task switching.

FIG. 5 is an explanatory diagram showing a conventional computer structure (architecture) for efficiently realizing the above software processing. In the figure, 8 is a C that stores information that is held and discussed by the CPU 3 among the information necessary to perform task switching.
Register 9 in PU3 represents a table in memory that holds register values necessary to restart the task after suspending the task, and 10 represents a table in memory necessary to access table 9. .

Next, the operation will be explained. The interrupt signal from the programmable timer 1 is sent to the programmable interrupt controller 72 via the interrupt selector 4, and is periodically input to the programmable interrupt controller 2: the CPU 3. The interrupt control section 5 is activated by this interrupt signal and issues a task switching request to the task control section 6. The task control unit 6 selects a task to be executed next and causes the dispatcher unit 7 to execute the task.

Here, a hardware task switching mechanism shown in FIG. 5 is used as a computer structure for efficiently executing the software processing for performing the task switching. When table 10 is used as the destination of a jump (JMP) or call (CALL) instruction, the current register value in the CPU 3 is saved to the area 8a indicated by T it as a hardware mechanism, and the value shown in table 10 is The value n held in the daple 9 becomes the new register value.

[Problem that the invention seeks to solve]

Since the conventional computer structure is configured as described above,
Periodic hardware interrupts are inserted from outside the CPU 3 to perform task management, but these mechanisms are not always necessary, and the problem is that they complicate both the hardware configuration and software processing. There was a point.

This invention was made to solve the above-mentioned problems.
The purpose is to obtain a computer structure that eliminates the need for external mechanisms and simplifies the software.

[Means for solving problems]

The computer structure according to the present invention provides an interval timer that performs automatic countdown in a register in the CPU, and reduces the load of task switching on basic software by linking the loading of values to this interval timer with a hardware task switching mechanism. It was designed to do so.

[For production]

In the computer structure of this invention, when a task is switched, a value is automatically loaded into an interval timer in the CPU, and as time passes, the value of this interval timer decreases until the value of the interval timer reaches "0". Then, the hardware task switching mechanism is automatically activated, task switching occurs, and a new value is loaded into the interval timer, and automatic task switching progresses by repeating this process.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 8 represents a register within the CPU 3, reference numeral 9 represents a table that holds register values necessary to restart a task after interruption, and reference numeral 10 represents a table necessary to access table 9. These correspond to those of the prior art which are given the same reference numerals in FIG. Further, 11 is a count register that is added to the register 8 and acts as an interval timer, 12 is an area where the counter value of the task in table 9 is stored, and 13 is data indicating the task to be switched at the time of task switching. This is the area where is stored. Here, the counter value in the area 12 is automatically loaded into the power input register 11 at the time of task switching.

Next, the operation will be explained. When task switching occurs,
As a hardware mechanism, the current value of the register in the CPU 3 (other than the counter value 12) is saved to the area 8a indicated by TR, and the value held in the table 9 indicated by the table 10 is the new value of the register. However, at this time, the counter register 11 also takes on a new value. The counter register 11 automatically counts down as time passes.
When the value of the count register 11 reaches 60''K, task switching automatically occurs to the task indicated by the data in the area 13.

FIG. 2 is an explanatory diagram showing details of the operation at the time of task switching. In the figure, 14, 15, and 16 are tables having the same structure as the table 9, and the tables 14 and 15 are logically chained using the data in the area 13 as a pointer. When a task switch occurs, execution rights are transferred one after another through this chain.

The task management basic software does not need to be involved in such transfer of execution rights between tasks at all. However, if you want to change the execution order of tasks, for example, if you want to execute table 16 between tables 14 and 15,
The data in area 13 of table 14, 15.degree. 16 can be rewritten by a program. The same goes for adding tasks.

Furthermore, if it is desired to adjust the continuous execution time of a task, the counter value 12 of each task may be rewritten by a program.

In the above method, since the continuous execution time of each task is directly specified, it is possible to easily calculate how many units of CPU time a certain task will be executed.

〔Effect of the invention〕

As described above, according to the present invention, a register in the CPU is provided with an interval timer, and when the count value reaches "O", the register value of the CPU is stored in a predetermined area and a new value is generated. , and also load a new initial value to the interval timer, so
This eliminates the need for periodic interrupts from the outside for task management, making it possible to reduce hardware requirements.
It is possible to simplify the basic software mentioned above, and it also has the effect of making it possible to speed up task switching and to easily design basic software that can specify how many tasks should be executed within the CPU time. be.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a computer structure according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing its task switching operation, K
FIG. 3 is a block diagram showing the hardware configuration of a conventional computer, and FIG. 4 is a block diagram showing its software configuration. FIG. 5 is an explanatory diagram showing the structure of a conventional computer. 3 is a CPU, 9 is a register, and 11 is an interno timer (count register). In the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation (two others) Figure 1 1 Sword Wa〉Toreshimege J

Claims (1)

[Claims] In a computer structure that includes a register in the central processing unit that stores information held by the central processing unit among the information necessary for executing task switching, an interval timer that automatically counts down at a constant speed is installed in the register. When the count value of the interval timer reaches "0", the register value of the central processing unit is stored in a predetermined area, and in exchange, a new value is stored in the register from another area. A computer structure characterized by having a function of automatically loading a new initial value into the interval timer.