JPS6318390A - Bit map unit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bitmap device that facilitates and speeds up clipping of drawings in a bitmap image display system.

Conventional technology When drawing in a bitmap image display system, if a drawing-prohibited area exists, it is determined whether the area does not intrude into the drawing-prohibited area, and drawing is performed only in areas that are not prohibited, that is, drawing-permitted areas. You have to do it like this. This is called clipping, and the area determination described above can be performed over a wide area by numerical calculations if both the drawing figure and the drawing permission area are given by mathematical formulas, but if it is an arbitrary figure or an arbitrary area, it is possible to This must be done pixel by pixel.

In the past, drawing software was responsible for all of the clipping, processing it as broadly as possible numerically, and then repeatedly determining the remaining portion pixel by pixel.

Problems to be Solved by the Invention Although region determination for each pixel is simple, it causes a dramatic increase in processing time. On the other hand, determination based on numerical calculations may result in complicated processing procedures, and if the formula representing the drawn figure is relatively complex, it will take the same amount of time as region determination for each pixel. Furthermore, the advantage of the bitmap image display system is that it is possible to display any figure at any position.
This feature means that it is difficult to perform the above-mentioned wide-area processing.

Therefore, in the conventional bitmap image display system, clipping requires a lot of time in both development of drawing software and processing execution.

The present invention has been made in view of these points, and it is an object of the present invention to realize simple and high-speed limping in a bitmap image display system.

Means for Solving the Problems The present invention is a bitmap device comprising main memory means, sub-memory means and control means. The image information itself is written and stored in the main storage means. Write permission area information is stored in the secondary storage means.

The control means realizes clipping by receiving and receiving area information from the secondary storage means and controlling writing to the main storage means.The main storage means retains image information by storing each pixel as a set of bits. . This is a conventional practice. A feature of the present invention is the existence of a sub-storage means that holds write-enabled area information, and the sub-storage means has a logic +!
On, 1111' is stored.

Now, when a write request to a certain area of the main storage means is issued from an external device, the control means reads the corresponding area of the secondary storage means, determines whether that area is write-protected or write-enabled, and only if permission is granted, the control means reads the corresponding area from the main storage means. generating a write signal to the means;

Embodiment FIG. 1 shows a first embodiment of the present invention. In this example, the main storage means 1 is DRAM (DynamicRa
The secondary storage means 2 is SRAM (5tatic Rando).
This is a bitmap device configured with m Access Memory. Normally, the circuit shown in FIG. 1 is multiplexed by the width of the data bus of the host processing system. Generally SRAM
can take a shorter access time than DRAM, and in this example, the access time of the secondary storage means 2 is set to be about half or less than that of the main storage means 1.

When a write request to the main memory means 1 is issued from an external device, the corresponding address is transferred to the address bus 4 and read
/write switching section 6 requests write, and timing generation section 5 sends RAS-:)MP! -') CAS and timing are generated sequentially, and the address multiplexer 7 receives the MPX signal from the timing generation section 5 and multiplexes the address. In parallel with this series of steps, the corresponding address in the sub-storage means 2 is read out. This read data is write permission information and is sent to the control means 3.

The RAS signal output from the timing generator 5 is output at the beginning of the cycle, and the control means 3 transmits it to the main storage means 1 without masking it. However, the CAS signal is issued after the data output of the sub-storage means 2 is determined, and if the output data of the sub-storage means 2 is a logic "○", it is masked by the control means 3 and does not reach the main storage means 1. In this case, the main storage means 1 only executes a refresh cycle and does not write data.

As described above, according to this embodiment, writing to the main memory 1 can be suppressed by the write permission information held by the sub memory 2.

FIG. 2 shows a second embodiment of the invention. This example is a bitmap device in which a main memory means and a sub-memory means are formed on the same chip by using a DRAM having four input/output terminals on one chip. In the figure, 101 corresponds to the sub-storage means, and 102.3.4 corresponds to the main storage means. Normally, the circuit shown in FIG. 2 is multiplexed by the width of the data bus of the host processing system.

In this example, a read-modify-write cycle is executed whenever a write request to the main storage means occurs. That is, the timing generation unit 5 calculates RA S -> M P
X->CA S->OK (High) ->011
(Low) -)W'E and sequentially generate timing. During this time, the D flip-flop 31 constituting a part of the control means 3 converts the output data of the sub-storage means to 0'K (Hi
gh) -> OE (Low), and if the data is logic "0", it will be masked by the WE multiplication signal control means 3.

In this case, the main storage means and the sub-memory means only execute a read cycle, and no writing occurs.

The data latched by the D flip-flop 31 is logic 11.
If it is 11+, writing is performed following reading, but in this case, the data written to the sub-memory means is set to logic IJI+ by the pull-up resistor 8, so the information held by the sub-memory means is not changed.

As described above, according to this embodiment, clipping can be performed by holding the main storage means and the sub-memory means on the same chinobu.

As described in detail, according to the present invention, clipping can be easily performed without requiring complicated procedures, and its practical value is great.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of the first implementation ERJ in the present invention, and the second
The figure is a circuit diagram of a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Main storage means, 2...Sub-storage means, 3...Control means, 4...Address bus, 6...Timing Generation section, 6...r
ead/write switching section, 7...Address multiplexer, 8...Pull-up resistor, 31
...D flip-flop. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
--Primary ratio + breath + #2 2-11 shi ■ 1 small + 2 + stage 3 -- one thing" 1 means 4- address bus 7- address multiplexer Fig. 1/-11 main i self 1 fable, + #! z - - - = 1 + record current stage J - 1 Lily post L history 4 - 1 - address bus S - 1 timing birth n country 7 - - A Y reply mar + brekbu 8 - pull azudu resistance

Claims (1)

[Claims] A main storage means for holding bitmap image information, a sub-storage means for holding write-permitted area information on the bitmap, and reading the write-permitted area information from the sub-storage means to control writing to the main storage means. A bitmap device comprising a control means for partially suppressing an attempt by an external device to write to the main memory means.