JPS63181508A - Digital waveform data generation circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of an address signal generation circuit by dividing one period of waveforms in terms of P and prescribing the address value of the address signal generated based on a clock signal for a memory storing the respective instantaneous amplitudes. CONSTITUTION:A first accumulator AC1 integrates alpha every arrival of the clock signal. An epsilon-ary counter 35 counts the clock signals and supplies a carry signal to the first accumulator AC1. When the carry signal does not arrive from the counter 35, a second accumulator AC2 integrates gamma every arrival of clock signal. And in the case of exceeding beta, the accumulator AC2 supplies the carry signal synchronizing to the clock signal to the first accumulator AC1 and adds gamma+(2<n>-beta) to the integrated value. When the carry signal arrives from the counter 35, it integrates gamma+delta every arrival of clock signal and in the case of exceeding beta, it supplies the carry signal synchronizing to the clock signal to the first accumulator AC1 and adds (gamma+delta)+(2<n>-beta) (provided that (n) is a positive integer) to the integrated value.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example (Fig. 1) I] Invention Effect A: Industrial Application Field The present invention relates to a digital waveform data generation circuit suitable for use in digital color subcarrier data generation circuits and the like.

B. Summary of the Invention The present invention relates to a digital waveform data generation circuit, which includes a memory in which one period of a waveform is divided into P parts and each instantaneous amplitude data is stored, and a memory that is driven by a clock signal to generate an address signal. In a digital waveform data generation circuit comprising an address signal generation circuit that supplies an address signal to a memory, and in which digital waveform data is repeatedly output from the memory, the address value of the address signal generated from the address signal generation circuit. is expressed by the following formula, address value = [α+γ/β+(δ/β)・(1/ε”)
+ <1/ε)] ・m+ζ (However, α to ε are positive integers,
ζ is O or a positive integer constant, m is 1 depending on the clock signal
Numbers that increase by increments, fractions in [ ] are true fractions, and numbers in [ ] are numbers modulo P. ) The address signal generation circuit includes a first accumulator that accumulates α every time a clock signal arrives, and an ε that counts the clock signal and supplies a carry signal to the first accumulator.
When a decimal counter and a carry signal from the counter do not arrive, T is accumulated every time a clock signal arrives, and when β is exceeded, a carry signal is supplied to the first accumulator in synchronization with the clock signal, and , the integrated value is γ+(
2n - β) (where n is a positive integer, 2n is the value closest to β and larger than β), and when a carry signal arrives from the counter, γ+ is added every time a clock signal arrives.
When δ is accumulated and β is exceeded, a carry signal is supplied to the first accumulator in synchronization with the clock signal, and
The configuration of the address signal generation circuit is simplified by including a second accumulator that adds (γ+δ)+(21−β) to the integrated value.

C. Prior Art Below, a conventional method of generating digital waveform data will be described. First, one method is to digitize one cycle of an analog signal with a desired waveform, write it in a memory, and read it repeatedly using a clock signal. An example will be specifically explained below.

For example, a case will be described in which one cycle of a sine wave with a frequency of Fs is digitized using a clock signal with a frequency of Fc, written into a memory, and read out using a clock signal with a frequency of Fc. These frequencies FS,
If there is a relationship of FC=4F5 between FCs, as shown in Fig. 4A, one period of the sine wave is divided into four, and the four instantaneous amplitude data [)l /MD', + <For example, 78 bits. (binary number) is sequentially written to four addresses in memory. In this case, a clock signal having a frequency of Fc, for example, is supplied to the write address counter. Then, a clock signal with a frequency of FC is supplied to the read address counter, and the four instantaneous amplitude data D, ~D4 of the above-mentioned sine wave are supplied.
By sequentially and repeatedly reading out the data, continuous digital sine wave data can be obtained.

If there is a relationship between frequencies Fs and FcO of Fc = 3.5Fs (i.e., 2Fc = 7Fs), as shown in Figure 4B (2 periods of the sine wave are divided into 7, and the 7 The instantaneous amplitude data D, -D7 (e.g., approximately 8-bit binary numbers) of the two points will be sequentially written to seven addresses in the memory.In this case, the memory capacity will be slightly smaller than in the case of FIG. increase

Furthermore, between the frequencies F s , , F cO, Fs:Fc
= 3001: If there is a relationship of 10,000, it means that the memory must store digital sine wave data for 10,000 cycles, and if one sample data is 8 bits, the memory has a capacity of 80 bits. You will need something like this.

Therefore, it can be seen that the simpler the integer ratio of the frequencies FS and FC is, the smaller the memory capacity is required, but the more complex the integer ratio is, the larger the memory capacity is.

Therefore, the frequency Fs of the digital waveform data to be obtained
U.S. Patent Nos. 4 and 3 disclose a digital waveform data generation circuit that does not require the use of a relatively large capacity memory even if the frequency FcO ratio of the clock signal is a complex integer ratio.
It is disclosed in the specification of No. 49,833, Japanese Patent Application Laid-open No. 88905/1983, etc.

Below, regarding this kind of digital waveform data generation circuit,
This will be explained with reference to FIGS. 5 and 6.

FIG. 5 shows the digital waveform data generation circuit as a whole, and FIG. 6 shows the specific configuration of the address signal generation circuit.

In FIG. 5, (3) is a memory in which one period of the sine wave is divided into P parts, and the instantaneous amplitude data of P([lil) at each point is stored in the memory (3).

(1) is a clock signal generation source, and (2) is an address signal generation circuit (phase calculation circuit) that generates an address signal based on this clock signal and supplies the address signal to the memory (3).

Then, the frequency of the digital sine wave data to be read from this memory (3) is Fs, and the frequency of the clock signal is Fs.
Let it be c.

Now, if the phase of the digital sine wave data read out from this memory (3) at any given time is φf, then
This is expressed as the following equation.

φ; φQ+2πFs-t (1) Here, φ0 represents the initial phase.

Next, when m is the count value of a read address counter (not shown) for the memory (3), the time t during which m clock signals are counted by this counter is expressed as follows.

t=m・ (1/Fc) ・ ・ ・ ・ ・ ・
・(2) Substituting this equation (2) into equation (1), we get (1
) is expressed as follows.

ψ=φ. +2π(FS/FC)-m... (3) Therefore, if the ratio of the frequency F S % F m is expressed as the ratio of integers that have no common factor Fs:Fm-N1M, (3)
The formula is expressed as follows.

φ=φo+2π(87M)・m (4) The initial phase φ0 is m as the initial value of the count value m.

can be excluded by including m(,=(l), then equation (4) can be expressed as the following equation.

φ=2π(87M) ・m (5) Then, as mentioned above, one period of the sine wave is divided into P parts, and each of the P pieces of instantaneous amplitude data is stored in the memory (3). Therefore, taking this into consideration, equation (5) can be expressed as the following equation.

φ=(2π/P)・(P:87M)・m・・・・(
6) In this equation (6), the phase φ is (P・M・m/M), where the phase φ is 2π/P, which is the phase obtained by dividing one wavelength into P.
It shows that it increases according to the value of
This (P, .87M) .m indicates the address value of memory (3).

Next, by substituting specific numerical values into equation (6), we will consider a specific configuration of the address signal generation circuit (2). Frequency Fs
, the ratio N:M of Fc is N:M=3001:1000
0 and P is P72048, equation (6) is expressed as the following equation.

φ=(2π/2048)X (2048x3001/1
10000)X −・(7)=(2π/2048)
X (614+378/625)Xm In this equation (7), m is a number that increases by l, such as 0.1.2.3, . Therefore, (614+378/625
)Xm is a number that increases by (614+:378/625) and is a number modulo 2048, that is, 2048
If it exceeds , the number starts from 0.

FIG. 6 shows a specific configuration of the address signal generation circuit (potential sum calculation circuit configuration) of FIG. 5. (10) in Figure 6 is 61
This is an arithmetic circuit that performs 4xm operations, that is, an accumulator. Also, Figure 6 (20) is (378/625) x
This is a carry accumulator, which is an arithmetic circuit that calculates m and when the value exceeds 1, subtracts 1 from the result of the calculation and supplies l as a carry signal to the accumulator (10).

First, the achievator (10) will be explained. It is composed of an 11-bit adder (11) and an 11-bit latch circuit (12).

The adder (11) adds the binary number corresponding to 614, the latch contents of the launch circuit (12) (binary number corresponding to a certain decimal number), and 1 of the carry signal from the carry achiemulator (20). After that, it is supplied to the launch circuit (12). Further, this latch circuit (12) is supplied with the clock signal having the above-mentioned frequency Fc, and latches the addition output of the adder (11) every time this clock signal arrives.

The output of this accumulator (10), ie, the latch circuit (12), is supplied as an address signal to the memory (3) in FIG. 5. In this accumulator (10), each time a clock signal arrives, the launch contents of the launch circuit (12) increase by 614, and when carry signal 1 is supplied from the carry accumulator (20), the launch content increases by 615.
To increase.

Next, the carry accumulator (20) will be explained. This is a 10-bit adder (21), (22), 1
It consists of a 0-bit switching circuit (23) and a 10-bit latch circuit (24).

In the adder (21), the binary number corresponding to 378 and the latched contents of the latch circuit (24) are added, and the added output is supplied to the switching circuit (23) and the other adder (22). In the adder (22), 399 (=1024
-625) and the addition output of the adder (21) are added, the addition output is supplied to the switching circuit (23), and the carry signal is sent to the switching circuit (23).
3) as a switching control signal and to the adder (11) of the accumulator (10). The output of the switching circuit (23) is supplied to the launch circuit (24). This latch circuit (24) is supplied with a clock signal having the above-mentioned frequency Fc. The output of the launch circuit (24,) is supplied to the adder (21).

In this carry accumulator (20), an adder (22
), when the carry signal is not output from the launch circuit (24), the latch contents of the launch circuit (24) and the binary number corresponding to 378 are added, and the added output is switched by the switching circuit (23) and supplied to the launch circuit (24). be done. Adder (
When the carry signal is output from the adder (22)
In other words, when the addition output of 2) exceeds 1024, the addition result of adder (21) is 625 (=1024-3
99)], the carry signal is supplied to the addition carry (11) of the accumulator (10), and the addition output of the adder (22), that is, the adder (21)
and the addition output of 399 (=1024-625) (102
The output of the addition of the binary number corresponding to the complement of 625 to 4 is switched by the switching circuit 1i (23) and supplied to the latch circuit (24).

Thus, when the ratio N:M of integers that do not have a common factor between the frequency Fs of the digital sine wave data and the frequency FC of the clock signal is N:M=3001:10000, the memory (3) has 1 2 periods of sine wave in the time axis direction
048 and store each 8-bit instantaneous amplitude data, so the memory (3) has a capacity of 1
It can be seen that the capacity is small, 6384 bits.

D Problems to be Solved by the Invention The present invention applies the principle of the conventional digital waveform data generation circuit described above to divide one period of the waveform into P parts, and store each instantaneous amplitude data in a memory. The address of the address signal generated based on the supplied clock signal is Address = [α+γ/β+(δ/β)・(1/ε)+
(1/ε)] ・m+ζ (where α to ε are positive integers, ζ is a constant of O or a positive integer, m is a number that increases by 1 according to the clock signal, the fraction in [ ] is a true fraction, [ ] is the number modulo P.) This paper attempts to propose a digital waveform data generation circuit that can simplify the configuration of the address signal generation circuit.

E Means for Solving Problems The present invention provides memories (31) and (32) in which a waveform for one period is divided into P parts and each instantaneous amplitude data is stored.
an address signal generation circuit (33) driven by a clock signal to generate an address signal, and the address signal is supplied to the memories (31), (32); In the digital waveform data generation circuit configured to repeatedly output digital waveform data from the address signal generation circuit (33), the address value of the address signal generated from the address signal generation circuit (33) is expressed by the following formula, address value = [α + γ / β + ( δ/β)・(1/ε) +(1/ε
)]・m+ζ (However, α to ε are positive integers, ζ is O or a constant of positive integers, m
is a number that increases by 1 in response to a clock signal, the fraction in [ ] is a true fraction, and the number in [ ] is a number modulo P. ) The address signal generation circuit (33) includes a first accumulator AC that accumulates α every time a clock signal arrives, and an ε-based counter that counts the clock signal and supplies a carry signal to the first accumulator AC. (35), and when the carry signal from the counter (35) does not arrive, γ is accumulated every time a clock signal arrives, and when β is exceeded, the carry signal is sent to the first accumulator AC in synchronization with the clock signal. , and add γ+(2n-β
) (where n is a positive integer, 2n is the value closest to β and larger than β.), and when a carry signal arrives from the counter (35), γ + δ is When β is exceeded, a carry signal is supplied to the first accumulator AC in synchronization with the clock signal, and the integrated value is (γ + δ) + (2n - β) (where n is a positive integer). A second accumulator AC2 that adds
It is equipped with the following.

F Effect According to the present invention, the address signal generation circuit (33)
The first accumulator AC, accumulates α every time a clock signal arrives. The epsilon counter (35) counts the clock signal and supplies a carry signal to the first accumulator AC.

The second accumulator AC2 of the address signal generation circuit (33) integrates T every time a clock signal arrives when the carry signal from the counter (35) does not arrive, and when it exceeds β, it synchronizes with the clock signal. and supplies a carry signal to the first accumulator AC, and adds γ to the accumulated value.
+(2n-β), and when a carry signal arrives from the counter (35), γ+δ is integrated every time a clock signal arrives, and when β is exceeded, the carry signal is added to the first one in synchronization with the clock signal. is supplied to the accumulator AC, and the integrated value is (γ + δ) + (2n - β) (however,
n is a positive integer).

G. Embodiment Below, with reference to FIG. 1, an embodiment in which the present invention is applied to a circuit that generates PAL digital color subcarrier data as digital waveform data will be described in detail. In FIG. 1, (31) is a sinROM from which digital U-axis color subcarrier data is obtained, and (32) is a cosROM from which digital V-axis color subcarrier data is obtained.

(33) is an address signal generation circuit (phase calculation circuit) that generates address signals to be supplied to these ROMs (31) and (32). Further, (34) is a color subcarrier phase/hue control circuit.

First, the memories (31) and (32) will be explained.

One period of sine wave is divided into 1024, and each of the 1024
pieces of instantaneous amplitude data (e.g. 8 bits) are stored in the memory (
31), and similarly, the cosine wave for one period is 102
It is assumed that the data is divided into four parts, and each of the 1024 pieces of instantaneous amplitude data (for example, 8 bits) is stored in the memory (32).

Next, the address signal generation circuit (33) will be explained. The frequency Fsc of the color subcarrier in the PAL system is expressed by the following equation. However, Fh indicates the horizontal frequency.

Fsc=(1135/4+1/625) - Select the frequency Fc of the Fh clock signal to, for example, 864Fh. Thus, the address value (decimal number) of the address signal supplied to the sin ROM (31) is as shown in (3) above.
, (6), it is expressed as the following equation.

Address value - (1024XFsc/Fc) - m+ =
(1024X (1135/4+ 1/625)XFh/864Fh) X m + K = (336+8/27 + (5/27.)X (1
/625)+1/625) X m + K =336Xm+ (8/274- (5/27)x (1/625)) This is the initial value of the address value when the color subcarrier phase/hue control circuit (occurs once) occurs.
) is changed according to the control state. Here, 336
= α, 27 = β, 8 = γ, 5 = δ, 625 = ε, K = ζ
It is.

Note that the phase of the digital V amber subcarrier data output from the cos ROM (32) is inverted depending on whether the number of lines is odd or even. 3
1) to the address value supplied to 512 per line.
(=1024/2) is added or not added.

In the address signal generation circuit (33), AC.

is an accumulator that performs a calculation of 336Xm.

This accumulator AC, is a 10-bit adder A3.
and a 10-bit latch circuit L3. In the adder A3, the latch contents of the latch circuit L3 (binary number corresponding to the decimal number), the binary number corresponding to 336, and 1 of the carry signal to be described later are added, and the added output is supplied to the latch circuit L3. and latched. Latch circuit L3
is supplied with a clock signal having a frequency of 864Fh, and is cleared (CLR) by a color frame pulse generated once every eight fields.

In this accumulator AC, the latched content of the latch circuit L3 increases by 336 (=α) every time a clock signal arrives, increases by 337 when a carry signal of 1 arrives, and returns to 0 when it reaches 1024. and increases again.

Next, (8/27+ (5/27)x (1/625)
The carry accumulator AC2 which calculates Xm and obtains a carry signal will be explained.

SWa is γ=8 and b=13=r+δ (however, γ=5
), an n=5-bit changeover switch, SWb
are c=r+ (32-27)=13 and d=b+ (
32-27) = 18, and these switches SWa and SWb convert the clock signal with a frequency of 864Fh to 1/625 (=1/ε
) is switched by the output of the frequency divider (625-decimal counter) (35). Here, (32-27) is 3
It is the complement of 27 (-β). Note that this frequency divider (35) is cleared (C) by the color frame pulse.
LR) will be done. Then, normally, γ=8 is output from switch SWa, and c-13 is output from switch SWb.
is output and a pulse (counter carry signal) is output from the frequency divider (35), the switch SW
b=13 is output from a, and d is output from switch SWb.
Switches SWa and SWb are set so that =18 is output.
can be switched. Note that 32 is the value of 211 that is closest to (and larger than 27) 27 (=β).

AH% A2 is an n=5-bit adder and SW.

is a changeover switch of n=5 bits, Ll is a latch circuit of n=5 bits, and L2 is a latch circuit of 1 bit/7 bits. A clock signal having a frequency of 864Fh is supplied to the latch circuits L1 and L2, and a color frame pulse is supplied as a clear signal.

In the adder A1, the latch contents of the latch circuit L1 (binary number corresponding to the decimal number) and the binary number corresponding to a=8 or b-13, which is the output of the switch S W a, are added, and the addition output is The signal is supplied to the latch circuit L1 through the switch SW1. Also, in the adder A2, the latch contents of the latch circuit and the output of the switch swb, C=13 or d.
The binary number corresponding to =18 is added, and the addition output is supplied to the launch circuit L1 through the switch SWI.

Further, the switch SW is switched by a carry signal from the adder A2 (outputted when the addition output exceeds 32), and the carry signal is supplied to the launch circuit L2.

Next, the operation of this carry accumulator AC2 will be explained. First, adder A1 has γ=8, adder A2 has C=
The case where 13 is supplied will be explained. When the carry signal is not obtained from the adder A2, the switch SW is switched to the adder Al side, and the latched contents of the latch circuit start from γ-8 and increase by γ=8. Then, when the addition output of adder A2 exceeds 32, that is, when the addition output of addition circuit A exceeds 27, adder A
Carry signal 1 is output from 2, and this is the latch circuit L.
2 and is latched, and the switch SW1
is switched to the adder A2 side, and in the adder A2, 27 is subtracted from the content of the latch circuit LI, and 7=
8 is added, that is, the contents of latch circuit L1 and (32-
27) The binary number corresponding to +8=13=C is added,
The addition output is supplied to the latch circuit and launched, and then the switch SW is switched to the adder A1 side again. After this, repeat this operation.

Next, every time the frequency divided output is obtained from the frequency divider (35), adder A1 receives b=γ+δ=8+5=13, adder A2 receives d=b+ (32-27)=r+δ+ (32 -27)
A case where =8+5+(32-27)=18 is supplied will be explained. When the carry signal is not obtained from the adder A2, the switch SW1 is switched to the adder A1 side, and the latched contents of the latch circuit L1 start from b=13 and increase by b=13. And adder A2
When the addition output exceeds 32, that is, when the addition output of addition circuit A1 exceeds 27, the carry signal 1 is output from adder A2.
is output, and this is supplied to the launch circuit L2 and latched, and the switch SW.

is switched to the adder A2 side, and the adder A2 subtracts 27 from the contents of the latch circuit and adds b=1 to it.
3 is added, that is, the contents of latch circuit L1 and (32-
27) The binary number corresponding to +13=18=d is added, the addition output is supplied to the launch circuit L1 and latched, and then the switch SW1 is switched to the adder A side again.

After this, repeat this operation.

Further, the calculation of (1/625)xm is performed by a frequency divider (35).

The output of the latch circuit L2 and the output of each 1 bit of the frequency divider (35) are sent to the parallel in/serial out circuit (36).
and is also supplied to the OR gate (37). The output of the OR gate (37) is supplied as a load signal to the parallel in/serial out circuit (36).

And this parallel in/parallel out circuit (36
), that is, the carry accumulator AC2
carry signal and the divided output of the divided carry (35) (
The carry signal of the counter) is supplied to the adder A3 of the accumulator AC.

Next, the color subcarrier phase/hue control circuit (34) will be explained. This consists of a 10-bit adder A6 and a 1
It consists of a 0-bit changeover switch SW3 and 10-bit latch circuits t and s. This launch circuit L
5, a color framing pulse is supplied as a pulse. A 10-bit color subcarrier phase control signal and an 8-bit hue control signal are supplied to adder A6 and added, and the added output and the color subcarrier phase control signal are supplied to changeover switch SW3. The switching output is supplied to launch circuit L5 and latched. This switch SW3 is normally the adder A6.
It is switched to the input terminal side of the color subcarrier phase control signal only during the horizontal blanking period.

Note that the phase control signal and hue control signal of the color subcarrier are as follows:
These are digital signals obtained by supplying the outputs of potentiometers for phase control and hue control of color subcarriers to an A/D converter and digitizing them. The output of the phase/hue control circuit for this color subcarrier is supplied to an adder A4, where it is added to the output of a latch circuit L3, and the added output is supplied to a launch circuit L4 and latched. A clock signal is supplied to this latch circuit L4.

Thus, from this launch circuit L4, the above address value = (1024XFsc/F c) m+ = C
l024X (1135/4+ 1/625)XFh/864Fh)
25) +1/6253 X m + K =336Xm+ [8/27+ (5/27)
supplied to Also, the address signal of this address value is 1
It is supplied to the 0-bit adder A5 and added to the binary number corresponding to 572, and the addition output and the latch output of the logic circuit L4 are supplied to the changeover switch SW2 and are switched depending on whether the line is odd or even. te, cos ROM (
32).

In this way, the U-axis digital color subcarrier data is output from the sin ROM (31), and the cosRoM (31)
2) outputs V-axis digital color subcarrier data whose phase is reversed depending on whether the line is odd or even.

Next, a description will be given of an NTSC system digital color subcarrier data generation circuit that is realized by utilizing most of the circuit configuration of the PAL system digital color subcarrier data generation circuit shown in FIG. In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals, and redundant explanation will be omitted. The NTSC system digital color subcarrier data generation circuit shown in FIG. 2 uses the switches SW a and SW in the PAL system digital color subcarrier data generation circuit shown in FIG.
b. Frequency divider circuit (35), parallel in/serial out circuit (36), OR game) (37), adder As, changeover switch SW2 is omitted, and the number of bits and input data value of each circuit are changed. This is what I did.

First, the memories (31) and (32) will be explained.

One period of sine wave is divided into 1024, and each of the 1024
The instantaneous amplitude data (e.g., 8 bits) of Fllii is stored in the memory (31), and similarly, the cosine wave for one period is divided into 1024 pieces, and each of the 1024 pieces of instantaneous amplitude data (e.g., 8 bits) is stored in the memory (31). (32).

Next, the address signal generation circuit (33) will be explained. The frequency Fsc of the color subcarrier in the NTSC system is expressed as follows. However, Fh indicates the horizontal frequency.

Fsc=(910/4)・Fh The frequency Fc of the clock signal is selected to be, for example, 858Fh. In this way, the address value (decimal number) of the address signal supplied to the sin ROM (31) is the above-mentioned (3
) and (6), it is expressed as the following equation.

Address value = (1024XFsc/Fc) ・m+
(1024X (910/4)X XFh/858Fh)xm+) ( = (271+221/429) This is the initial value of the address value at the time of occurrence of the color sub-ILI transmission phase/hue control circuit (which occurs twice).
34) It is changed according to the control state.

In the address signal generation circuit (33), AC.

is an accumulator that performs a calculation of 271Xm, and has the same configuration as that in FIG. Furthermore, the frequency of the clock signal is 85
It is 8Fh. Furthermore, the latch circuit L3 is cleared by a color frame pulse generated once every four fields. This accumulator AC.

In this case, the latch contents of the launch circuit L3 increase by 271 each time a clock signal arrives, and increase by 272 when a carry signal of 1 arrives.

Next, a description will be given of the carry accumulator AC2 which performs the calculation of (221/429)Xm to obtain a carry signal. AI and A2 are each an n-=9-bit adder and SW
, is an n=9-bit changeover switch, L is a n=9-bit launch circuit, and L2 is a 1-bit latch circuit. A clock signal having a frequency of 858Fh is supplied to the latch circuits L1 and L2, and a color frame pulse is supplied as a clear signal.

In the adder A1, the launch contents (binary number according to the decimal number) of the launch circuit L1 and the binary number corresponding to 221 are added, and the addition output is supplied to the launch circuit L1 through the switch SW1. Also, in adder A2, the latch contents of the launch circuit and 304=221+ (512-
429) is added to the corresponding binary number, and the addition output is supplied to the latch circuit L1 through the switch SWI. Also, the carry signal from adder A2 (addition output is 5
(output when it exceeds 12) switches SW.

is switched, and its carry signal is supplied to launch circuit L2.

Next, the operation of this carry accumulator AC2 will be explained. When the carry signal is not obtained from the adder A2, the switch SWI is switched to the adder A1 side, and the latched contents of the latch circuit L1 start from 221 and start from 2.
Increase by 21.

When the addition output of adder A2 exceeds 512, and when the addition output of addition circuit A1 exceeds 429, addition W-
A carry signal 1 is output from the device A2, and this is supplied to the launch circuit L2 and latched, and the switch SW
, is switched to the adder A2 side, and the adder A2 subtracts 429 from the contents of the latch circuit L1 and adds 221 to it, that is, the contents of the launch circuit L1 and 2.
21+(512-429) and the binary number corresponding to -304 are added, the addition output is supplied to the latch circuit L1 and latched, and then the switch S is switched to the adder A side again. After this, repeat this operation.

Then, from this latch circuit L4, the above-mentioned address value -
(1024XFsc/Fc)-m+ = (1024x
910/4xFh/ 858Fh)xm+ = (271+221/429)Xm 271Xm+ (221/429)
and the cos ROM (32).

In this way, the digital color subcarrier data of the U axis is output from the sin ROM (31), and the digital color subcarrier data of the U axis is output from the cos ROM (31).
2) outputs the digital color subcarrier data of the ■ axis.

Next, a description will be given of a PAL-M digital color sub-I branch transmission data generation circuit which is realized by utilizing most of the circuit configuration of the PAL digital color sub-carrier data generation circuit shown in FIG. In FIG. 3, parts corresponding to those in FIG. 1 are given the same reference numerals, and redundant explanation will be omitted. The NTSC system digital color subcarrier data generation circuit shown in FIG. 3 has switches SWa, swb,
If the frequency divider circuit (35), parallel in/serial out circuit (36), and OR gate (37) are omitted,
The number of bits of each circuit and the input data value are changed.

First, the memories (31) and (32) will be explained.

One period of sine wave is divided into 1024, and each of the 1024
pieces of instantaneous amplitude data (e.g. 8 bits) are stored in the memory (
3■), and similarly, one period of cosine wave is stored in 10
It is assumed that the signal is divided into 24 pieces, and each of 1024 pieces of instantaneous amplitude data (for example, 8 bits) is stored in the memory (32).

Next, the address signal generation circuit (33) will be explained. The frequency Fsc of the color subcarrier in the PAL-M system is expressed as follows. However, Fh indicates the horizontal frequency.

Fsc=(909/4) ・Fh The frequency Fc of the clock signal is selected to be, for example, 858Fh. Thus, the address value (decimal number) of the address signal supplied to the sin ROM (31) can be expressed as the following equation from equations (3) and (6) above.

Address value = (1024XFsc/Fc) - m+ =
(1024X (909/4)X ×Fh/858Fh) This is the initial value of the address value at the time of generation, and the value is the phase/hue control circuit (34) of the color subcarrier.
) is changed according to the control state.

In the address signal generation circuit (33), AC.

is an accumulator that performs the calculation of 271xm, and has the same configuration as that in FIG. Furthermore, the frequency of the clock signal is 85
It is 8Fh. Further, the latch circuit L3 is cleared by being supplied with one color frame pulse for eight fields. In this accumulator AC1, the latched contents of the latch circuit L3 increase by 271 each time a clock signal arrives, and increase by 272 when a carry signal of 1 arrives.

Next, the carry accumulator AC2 which obtains a carry signal by calculating (31/143)Xm will be explained.

AI and A2 are each n=8 bit adders, and SWl is n=8 bit adder.
An 8-bit changeover switch, L1, is a latch circuit with n=8 bits, and L2 is a 1-bit latch circuit. A clock signal having a frequency of 858Fh is supplied to the latch circuits t, , , L2, and a color frame pulse is supplied as a clear signal.

In the adder A1, the contents of the latch (binary number corresponding to the decimal number) of the latch circuit L1 are added to the binary number corresponding to 31, and the added output is supplied to the latch circuit L1 through the switch SW1. Also, in adder A2, the latch contents of latch circuit L1 and 144=31+(256-14
3) and the corresponding binary number are added, and the added output is supplied to the latch circuit L1 through the switch SW1. Further, the switch SW is switched by a carry signal from the adder A2 (outputted when the addition output exceeds 256), and the carry signal is supplied to the latch circuit L2.

Next, the operation of this carry accumulator AC2 will be explained. When the carry signal is not obtained from the adder A2, the switch SW1 is switched to the adder A side, and the latched contents of the latch circuit start from 31 and start from 31.
Increase by increments. Then, the addition output of adder A2 is 256
When the addition output of the adder circuit A1 exceeds 143, a carry signal 1 is output from the adder A2, which is supplied to the latch circuit L2 and latched.
The switch SW1 is switched to the adder A2 side, and the adder A2 subtracts 143 from the content of the latch circuit L1 and adds 31 to it, that is, the content of the latch circuit L1 and 31+(256-143). The binary number corresponding to =144 is added, and the addition output is supplied to the latch circuit and latched, and then the switch SW1 is switched to the adder A1 side again. After this, repeat this operation.

Then, from the latch circuit L4, the above address value = (1024XFsc/Fc) m+
= (1024X909/4XFh/ 858 F h)
and cos ROM (32).

In this way, the digital color subcarrier data of the U axis is output from the sin ROM (31), and the digital color subcarrier data of the U axis is output from the cos ROM (31).
2) outputs V-axis digital color subcarrier data whose phase is reversed to normal or reverse depending on whether the line is odd or even.

H Effects of the Invention In the present invention, the address value of the address signal generated based on the clock signal to the memory in which one cycle of the waveform is divided into P and each instantaneous amplitude is stored is address value=[α+γ/β+( δ/β)・(1/ε)+
(1/ε)] ・m+ζ (However, α~ε are positive integers, ζ
is a constant of 0 or a positive integer, m is a number that increases by 1 in response to the clock signal, the fraction in [ ] is a true fraction, and the number in [ ] is a number modulo P. ), it is possible to obtain a digital waveform data generation circuit with a simple configuration of the address signal generation circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a PAL digital color subcarrier data generation circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a PAL digital color subcarrier data generation circuit of FIG. 1. A block diagram showing an NTSC system digital color subcarrier data generation circuit using a part of the circuit configuration; FIG. 3 is a block diagram showing a part of the circuit configuration of the PAL system digital color subcarrier data generation circuit shown in Figure 1. FIG. 4 is an explanatory diagram of a conventional example, FIG. 5 is a block diagram showing a conventional digital waveform data generation circuit, and FIG. 6 is a block diagram showing a specific configuration of the address signal generation circuit of FIG. 5. FIG. (31), (32) are memory (ROM), (33)
is an address signal generation circuit, AC is a first accumulator, AC2 is a second accumulator, (34) is a color subcarrier phase/hue control circuit, (35) is a counter (frequency divider), and A1 to A6 are Adder, L1 to L5 are latch circuits, SWa. SWb, SW+ to SW3 are changeover switches. A B Home” Miitari 0 words 1. Fig. 4 Determinable data 1 to 3 skin form 0 theta Isei

Claims (1)

[Claims] A waveform for one cycle is divided into P parts, and a memory in which each instantaneous amplitude data is stored, and an address signal is generated by being driven by a clock signal, and the address signal is supplied to the memory. In a digital waveform data generation circuit having an address signal generation circuit and configured to repeatedly output digital waveform data from the memory, the address value of the address signal generated from the address signal generation circuit is expressed by the following equation. , address value = [α+γ/β+(δ/β)・(1/ε)+(1/ε)]・m+ζ (However, α to ε are positive integers, ζ is 0 or a positive integer constant, m
is a number that increases by 1 according to the above clock signal, [ ]
The fractions inside are true fractions, and the numbers inside [ ] are numbers modulo P. ) The address signal generation circuit includes: a first accumulator that integrates α every time the clock signal arrives; an ε-adic counter that counts the clock signal and supplies a carry signal to the first accumulator; When the carry signal does not arrive from the counter, the γ is integrated every time the clock signal arrives, and when the γ is exceeded, the carry signal is added to the first clock signal in synchronization with the clock signal.
In addition to supplying the accumulated value to the accumulator, γ+
(2^n - β) (where n is a positive integer, 2^n is the value closest to β and larger than β), and when the carry signal from the counter arrives, the clock signal The above γ+δ is integrated every time the above β is reached, and when the above β is exceeded, a carry signal is supplied to the first accumulator in synchronization with the above clock signal, and the integrated value is added to (γ+δ
)+(2^n-β).