JP2535900B2 - Clock signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field B Outline of the Invention C Conventional Technology D Problems to be Solved by the Invention E Means for Solving Problems (FIG. 1) F Action G Example G1 Clock Signal Generation Circuit (1st Figure) Digital color subcarrier signal generator circuit of G2 PAL system (Fig. 2) Digital color subcarrier signal generator circuit of G3 NTSC system (Fig. 3) H Effect of the invention A Industrial field of application The present invention is a digital VTR, etc. The present invention relates to a clock signal generation circuit suitable for application to the digital video equipment.

B. SUMMARY OF THE INVENTION The present invention relates to a clock signal generation circuit, which compares phases of a reference burst signal and an analog color subcarrier signal described later, and outputs the comparison output, which is an integer multiple of the color subcarrier frequency, though it is an integer multiple of the horizontal frequency. Controls the oscillation frequency of a variable oscillator that generates a clock signal with a non-frequency, and supplies the clock signal from the variable oscillator as an address signal to the digital color subcarrier signal generation circuit that stores digital waveform data. A stable clock signal is obtained by obtaining a carrier signal and D / A converting this digital color subcarrier signal to obtain the above analog color subcarrier signal.

C Conventional Technology For example, the frequency Fc of the system clock signal used in the component type digital VTR is selected as a frequency which is an integral multiple of the horizontal frequency Fh but not an integral multiple of the color subcarrier frequency Fsc.

The frequency Fc of the system clock signal is, for example, PAL
864Fh for the system and 858Fh for the NTSC system.

Therefore, conventionally, this system clock signal is generated by the PLL based on the reference horizontal synchronizing signal obtained from the outside.

D Problem to be Solved by the Invention As described above, the clock signal having the frequency Fc which is conventionally an integral multiple of the horizontal frequency Fh but is not an integral multiple of the color subcarrier frequency Fsc is based on the reference horizontal synchronizing signal. Since it was made by using the above method, it had the drawback of lacking stability.

In view of such a point, the present invention has a frequency Fc that is an integral multiple of the horizontal frequency Fh but is not an integral multiple of the color subcarrier frequency Fsc.
It is intended to propose a clock signal generation circuit capable of obtaining a stable clock signal having the above.

E Means for Solving Problems The clock signal generation circuit according to the present invention controls the oscillation frequency based on the phase comparator (5) to which the reference burst signal is supplied and the comparison output of the phase comparator (5). Has been
By a variable oscillator (7) that generates a clock signal having a frequency that is an integral multiple of the horizontal frequency but not an integral multiple of the color subcarrier frequency, digital waveform data is stored, and the clock signal is supplied as an address signal. ,
A digital color subcarrier signal generation circuit (8) that outputs a digital color subcarrier signal and a digital color subcarrier signal from the digital color subcarrier signal generation circuit (8) are supplied and converted into an analog color subcarrier signal An analog color subcarrier signal from the D / A converter (9) is supplied to the phase comparator (5) for phase comparison with the reference burst signal. It was done like this.

According to the present invention, the phase comparator (5)
The reference burst signal and the analog color subcarrier signal from the D / A converter (9) are phase-compared, and the oscillation frequency of the variable oscillator (7) is controlled by the comparison output, and the clock signal is output from the variable oscillator (7). Is output. The clock signal from the variable oscillator (7) is supplied as an address signal to the digital color subcarrier signal generation circuit (8) in which the digital waveform data is stored, and the digital color subcarrier signal is obtained from this clock signal, which is D An analog color subcarrier signal to be supplied to the / A converter (9) and to the phase comparator (5) is obtained.

G Embodiment G1 Clock Signal Generation Circuit An embodiment of the clock signal generation circuit according to the present invention will be described in detail below with reference to FIG. External reference sync signal from input terminal (1) (external reference video signal)
(A signal including at least a reference horizontal and vertical sync signal and a reference burst signal, which will be simply referred to as a reference signal hereinafter) is supplied to a sync separation circuit (2) and a burst extraction circuit (3). The sync separation circuit (2) separates the reference horizontal sync signal from the reference signal. This horizontal synchronizing signal is supplied to the burst extraction circuit (3), where a burst gate signal is created, and the reference gate signal is extracted from the reference signal by this burst gate signal.

This reference burst signal is supplied to the phase comparator (5) and compared in phase with the analog color subcarrier signal from the low pass filter (10) described later. The comparison output of the phase comparator (5) is supplied to the voltage controlled variable oscillator (7) through the low pass filter (6), and its oscillation frequency is controlled. A system clock signal CK is output from this variable oscillator (7). The frequency Fc of the system clock signal CK is, for example, 864Fh in the PAL system and 858Fh in the NTSC system, and these clock signals CK are integer multiples of the horizontal frequency Fh, but not integer multiples of the color subcarrier frequency Fsc Have a frequency.

The clock signal CK is supplied as an address signal to the digital color subcarrier signal generation circuit (8) in which digital waveform data is stored. The structure of the digital color subcarrier signal generation circuit (8) will be described later with reference to FIG. 2 (for PAL system) and FIG. 3 (for NTSC system). The digital color subcarrier signal generation circuit (8) outputs the first digital color subcarrier signal SC ₁ and the second digital color subcarrier signal SC ₂ having a 90 ° phase difference from the first digital color subcarrier signal SC ₁ . The color subcarrier frequencies Fsc of the first and second digital color subcarrier signals SC ₁ and SC ₂ are Fsc = (1135/4 + 1/625) in the PAL system and Fsc = in the Fh NTSC system. (910/4) ・ It is Fh.

The first digital color subcarrier signal SC ₁ from the digital color subcarrier signal generation circuit (8) is supplied to the D / A converter (9) and converted into an analog color subcarrier signal, and then the lowpass filter ( It is supplied to the phase comparator (5) through 10) and is phase-compared with the reference burst signal from the burst extraction circuit (3) as described above.

Then, in the phase comparator (5), the low pass filter (6), the variable oscillator (7), the digital color subcarrier signal generation circuit (8), the D / A converter (9) and the low pass filter (10), PLL (4) is configured.

(14) is an encoder for converting a component video signal into a color video signal (composite color video signal). The encoder (14) includes a system clock signal CK from the variable oscillator (7) and a digital color subcarrier. The first and second digital color subcarrier signals SC ₁ and SC ₂ from the signal generating circuit (8) are supplied.

The encoder (14) receives the first and second digital color subcarrier signals SC ₁ and SC ₂ having a phase difference of 90 ° from the input terminals (1
1) and (12) first and second digital color signals (digital red difference and blue difference signals or digital I and Q signals) C ₁ and C ₂ are balanced-modulated and both digital modulated signals are added By doing so, the digital carrier color signal C is obtained.

Then, in the digital adder circuit (15), input terminal (13)
The digital luminance signal Y from and the digital carrier color signal C from the encoder (14) are added, and the digital color video signal (composite color video signal) is output to the output terminal (16).
Get M.

Further, although not shown, the clock signal CK described above is also supplied to the time base collector (TBC).

G2 PAL System Digital Color Subcarrier Signal Generation Circuit Next, an example of the PAL system digital color subcarrier signal generation circuit will be described with reference to FIG.

In FIG. 2, (31) and (32) are memories, and the memories (31) and (32) have P cycles of sine wave and cosine wave for one period.
It is assumed that the data is divided and P pieces of instantaneous amplitude data at each point are stored. (33) generates an address signal based on the clock signal and stores the address signal in a memory (3
An address signal generation circuit (phase calculation circuit) supplied to 1) and (32). Then, for example, the frequency of the digital sine wave data to be read from the memory (31) is Fs, and the frequency of the clock signal is Fc.

Assuming that the phase of the digital sine wave data read from the memory (31) at an arbitrary time t is φ, this is expressed by the following equation.

φ = φ ₀ + 2πFs · t (1) Here, φ ₀ represents the initial phase.

Next, when m is a count value of a read address counter (not shown) for the memory (31), the time t at which m clock signals are counted by this counter is expressed by the following equation.

t = m · (1 / Fc) (2) When this equation (2) is substituted into the equation (1), the equation (1) is expressed as the following equation.

φ = φ ₀ + 2π (Fs / Fc) · m (3) Then, if the ratio of frequencies Fs and Fc is represented by an integer ratio Fs: Fc = N: M that does not have a common factor, equation (3) becomes It is expressed as the following equation.

φ = φ ₀ + 2π (N / M) · m (4) Since the initial phase φ ₀ can be excluded by including m ₀ as the initial value of the count value m, when m ₀ = 0, the equation (4) is obtained. Is expressed by the following equation.

φ = 2π (N / M) · m (5) Then, as described above, one period of the sine wave is divided into P, and each of the P instantaneous amplitude data is stored in the memory (3). Therefore, considering this, the equation (5) is expressed as the following equation.

φ = (2π / P) · (P · N / M) · m (6) In this equation (6), the phase φ is 2π / P which is a phase obtained by dividing one wavelength into P, and (P)・ N ・ m / M) is shown to increase according to the numerical value. That is, this (P
(N / M) · m indicates the address value of the memory (3).

Further explaining, (31) is a sinROM from which digital U-axis color subcarrier data is obtained, and (32) is a cosROM from which digital V-axis color subcarrier data is obtained. Also, (34) is
This is a phase / hue control circuit for the color subcarrier.

First, the memories (31) and (32) will be described. One cycle of the sine wave is divided into 1024, and each 1024 instantaneous amplitude data (for example, 8 bits) is stored in the memory (31). Similarly, one cycle of the cosine wave is divided into 1024,
It is assumed that 1024 pieces of instantaneous amplitude data (for example, 8 bits) are stored in the memory (32).

Next, the address signal generation circuit (33) will be described. The frequency Fsc of the chrominance subcarrier in the PAL system is represented by the following equation. Here, Fh indicates the horizontal frequency.

Fsc = (1135/4 + 1/625) · Fh The frequency Fc of the clock signal is selected to be 864Fh, for example. Thus, the address value (decimal number) of the address signal supplied to the sinROM (31) is expressed by the following equation from the above equations (3) and (6).

Address value = (1024 × Fsc / Fc) m + K = [(1024 × (1135/4 + 1/625) × Fh / 864Fh] × m + K = [336 + 8/27 + (5/27) ×× (1/625) + 1 / 625] × m + K = 336 × m + [8/27 + (5/27) × (1/625)] × m + (1/625) × m + K This K is a color frame pulse (occurs once in 8 fields) The initial value of the address value at the time of occurrence of the color subcarrier phase / hue control circuit (3
It can be changed according to the control state of 4).

Since the digital V-axis color subcarrier data output from the cosROM (32) undergoes phase inversion according to the odd / even number of lines, the address value of the address signal supplied to the cosROM (32) is the sinROM (31 ), 512 (= 1024/2) is added or not added to each address value for each line.

In the address signal generation circuit (33), AC ₁ is 336 ×
It is an accumulator that calculates m. The accumulator AC ₁ is composed of 10-bit adder A ₃ and 10-bit latch circuit L _3. The adder A _3, and latch content of the latch circuit L ₃ (10 decimal binary number corresponding to the number), binary numbers and corresponding to 336, and 1 carry signal described later is added,
The added output is latched is supplied to the latch circuit L _3. The latch circuit L _3, frequency with the clock signal of 864Fh is supplied, is cleared (CLR) by the color frame pulse generated once every 8 fields.

In this accumulator AC ₁ , the latch content of the latch circuit L ₃ increases by 336 each time the clock signal arrives, increases by 337 when the carry signal 1 arrives, returns to 0 when it reaches 1024, and increases again. To do.

Next, carry accumulator AC ₂ that performs a calculation of [8/27 + (5/27) × (1/625)] × m to obtain a carry signal
Will be described. SWa is an n = 5-bit selector switch that switches between 8 and b = 13, and SWb is c = 8 + (32
-27) = 13 and d = b + (32-27) = 18 are switched n
= 5-bit changeover switch, these switches SWa, SW
b is switched by an output of a frequency divider (625-base counter) (35) that divides a clock signal having a frequency of 864Fh into 1/625. Here, (32-27) is the complement of 27 to 32. The frequency divider (35) is cleared (CLR) by the color frame pulse. And usually switch S
8 is output from wa, c = 13 is output from the switch SWb, and b = 1 from the switch SWa only when a pulse (carry signal of the counter) is output from the frequency divider (35).
The switches SWa and SWb are switched so that 3 is output and d = 18 is output from the switch SWb. 32 is 27
^Is a value of 2 ⁿ that is closest to and greater than 27.

A ₁ and A ₂ are n = 5-bit adders, SW ₁ is an n = 5-bit changeover switch, L ₁ is an n = 5-bit latch circuit, and L ₂ is a 1-bit latch circuit. Latch circuit L ₁ , L
The _2, frequency with the clock signal of 864Fh is supplied, color frame pulse is supplied as a clear signal.

In the adder A ₁ , the latch content of the latch circuit L ₁ (binary number corresponding to a decimal number) and the binary number corresponding to a = 8 or b = 13 which is the output of the switch SWa are added, and the addition output is It is supplied to the latch circuits L ₁ through the switch SW _1. or,
The adder A _2, the latch content of the latch circuit L _1, switch
Binary number and corresponding to the output serving c = 13 or d = 18 of SWb are added, the addition output is supplied to the latch circuits L ₁ through the switch SW _1. Also, the switch SW ₁ is switched by the carry signal from the adder A ₂ (addition output is outputted to exceed 32), the carry signal is supplied to the latch circuit L _2.

Next, let's explain the operation of this carry accumulator AC ₂ . First, the case where 8 is supplied to the adder A ₁ and c = 13 is supplied to the adder A ₂ will be described. When the carry signal is not obtained from the adder A ₂ , the switch SW ₁ is switched to the adder A ₁ side, and the latch content of the latch circuit L ₁ starts from 8 and increases by 8. When the added output of the adder A ₂ exceeds 32, that is, when the added output of the adder circuit A ₁ exceeds 27, a carry signal 1 is output from the adder A ₂ and is supplied to the latch circuit L _2. while being latched, the switch SW ₁ is switched to the adder a ₂ side, the adder a _2, it 8 is added along with 27 is subtracted from the contents of the latch circuits L _1, i.e., the latch circuits L ₁ Contents and (32-27) +8
= 13 = c and the binary number corresponding to c are added, and the added output is supplied to the latch circuit L ₁ and latched, and then the switch SW ₁ is switched to the adder A ₁ side again. Thereafter, this operation is repeated.

Then, each time the divided output from the frequency divider (35) is obtained, b = 8 + 5 = 13 to the adder A ₁ is, d = b + to the adder A ₂ (32-
The case where 27) = 8 + 5 + (32−27) = 18 is supplied will be described. When the carry signal is not obtained from the adder A ₂ , the switch SW ₁ is switched to the adder A ₁ side, and the latch content of the latch circuit L ₁ starts from b = 13 and b = 13.
It increases in steps. When the addition output of the adder A ₂ exceeds 32, that is, when the addition output of the addition circuit A ₁ exceeds 27, a carry signal 1 is output from the adder A ₂ and this is a latch circuit.
The switch SW ₁ is switched to the adder A ₂ side while being supplied to L ₂ and latched, and 27 is subtracted from the content of the latch circuit L ₁ by the adder A ₂ and b = 13 is added to it. That is, the contents of the latch circuit L ₁ and (32−27) + 13 = 18 =
The binary number corresponding to d is added, and the addition output is supplied to the latch circuit L ₁ and latched, and then the switch SW ₁
Is switched to the adder A ₁ side again. Thereafter, this operation is repeated.

The calculation of (1/625) × m is performed by the frequency divider (35).

Each 1-bit output of the output and the frequency divider of the latch circuit L ₂ (35) is supplied to a parallel-in / serial-out circuit (36) is supplied to the OR gate (37). The output of the OR gate (37) is supplied to the parallel-in / serial-out circuit (36) as a load signal. Then, the 1-bit output of the parallel-in / serial-out circuit (36), that is, the carry signal of the carry accumulator AC ₂ and the frequency division output of the frequency division circuit (35) (the carry signal of the counter)
Is supplied to the adder A ₃ of the accumulator AC ₁ .

Next, the phase / hue control circuit (34) of the color subcarrier will be described. This is composed of a 10-bit adder A ₃ , a 10-bit changeover switch SW _3, and a 10-bit latch circuit L ₅ . The latch circuit L _5, color framing pulse is supplied as a latch pulse. To the adder A _6, and the phase control signal of 10 bits of color subcarrier, 8
The bit control signal is supplied and added, and the addition output and the phase control signal of the color subcarrier are supplied to the changeover switch SW ₃ to be changed over, and the changeover output is supplied to the latch circuit L _5. Latched. This switch SW
₃ usually is switched to the adder A ₆ side, only the horizontal blanking period, it is switched to the input terminal side of the color subcarrier phase control signal. The phase control signal and the hue control signal of the color subcarrier are digital signals obtained by supplying the outputs of potentiometers for phase control and hue control of the color subcarrier to the A / D converter and digitizing them. . Then, the output K of the phase / hue control circuit of this color subcarrier is supplied to the adder A ₄ and added with the output of the latch circuit L ₃ , and the added output is supplied to the latch circuit L ₄ and latched. . A clock signal is supplied to the latch circuit L ₄ .

Thus, from the latch circuit L ₄ , the above address value = (1024 × Fsc / Fc) · m + K = [1024 × (1135/4 + 1/625) × Fh / 864Fh] × m + K = [336 + 8/27 + (5/27 ) × (1/625) +1/625] × m + K = 336 × m + [8/27 + (5/27) × (1/625)] × m + (1/625) × m + K Supplied to sinROM (31). Further, the address signal of the address value is supplied to the 10-bit adder A _5, is added to the binary number corresponding to 572, supply and latching the output of the adder output and the latch circuit L ₄ is a changeover switch SW ₂ Then, the data is switched according to the oddness or evenness of the line, and supplied to the cosROM (32).

Thus, the sinROM (31) outputs the digital color subcarrier data of the U-axis, and the cosROM (32) outputs the digital color subcarrier data of the V-axis whose phase is reversed in the forward or reverse according to the odd or even line. Is output.

G3 NTSC digital color subcarrier signal generation circuit Next, the NTSC digital color subcarrier signal generation realized by using most of the circuit configuration of the PAL digital color subcarrier signal generation circuit shown in FIG. The circuit will be described with reference to FIG. Incidentally, in FIG.
Portions corresponding to those in the figure are denoted by the same reference numerals, and redundant description will be omitted. The NTSC system digital color subcarrier signal generation circuit shown in FIG. 3 is equivalent to the switches SWa, SWb, the frequency dividing circuit (35), and the parallel in / serial output in the PAL system digital color subcarrier signal generation circuit shown in FIG. Circuit (36), OR
The gate (37), the adder A ₅ , and the changeover switch SW ₂ are omitted, and the number of bits of each circuit and the input data value are changed.

First, the memories (31) and (32) will be described. One cycle of the sine wave is divided into 1024, and each 1024 instantaneous amplitude data (for example, 8 bits) is stored in the memory (31). Similarly, one cycle of the cosine wave is divided into 1024,
It is assumed that 1024 pieces of instantaneous amplitude data (for example, 8 bits) are stored in the memory (32).

Next, the address signal generation circuit (33) will be described. The frequency Fsc of the color subcarrier in the NTSC system is expressed by the following equation. Here, Fh indicates the horizontal frequency.

Fsc = (910/4) · Fh The frequency Fc of the clock signal is selected to be, for example, 858Fh. Thus, the address value (decimal number) of the address signal supplied to the sinROM (31) is expressed by the following equation from the above equations (3) and (6).

Address value = (1024 × Fsc / Fc) ・ m + K = [1024 × (910/4) × Fh / 858Fh] × m + K = [271 + 221/429) × m + K = 271 × m + (221/429) × m + K This K is , The initial value of the address value when a color frame pulse (generated once every four fields) is generated, and the value is the phase / hue control circuit (3) of the color subcarrier.
It can be changed according to the control state of 4).

In the address signal generation circuit (33), AC ₁ is 271 ×
This is an accumulator for calculating m, and has the same configuration as in FIG. The frequency of the clock signal is 858Fh.
Further, the latch circuit L ₃ is cleared (CLR) by the color frame pulse generated once in four fields. In this accumulator AC ₁ , the latch content of the latch circuit L ₃ is increased by 271 every time the clock signal arrives, and the carry signal 1
When comes, it increases by 272.

Next, a description will carry the accumulator AC ₂ to obtain a carry signal by performing an arithmetic operation of (221/429) × m. A ₁ , A ₂
Are n = 9-bit adders, SW ₁ is an n = 9-bit changeover switch, L ₁ is an n = 9-bit latch circuit, and L ₂ is a 1-bit latch circuit. For the latch circuits L ₁ and L ₂ ,
A clock signal having a frequency of 858Fh is supplied, and a color frame pulse is supplied as a clear signal.

The adder A _1, a latch content of the latch circuits L ₁ (binary number corresponding to the decimal), binary numbers and corresponding to 221 is added, the latch circuits L ₁ and the addition output through the switch SW ₁
Is supplied to. Further, in the adder A ₂ , the latch content of the latch circuit L ₁ and the binary number corresponding to 304 = 221 + (512−429) are added, and the addition output is supplied to the latch circuit L ₁ through the switch SW _1. It Also, the switch SW ₁ is switched by the carry signal from the adder A ₂ (addition output is outputted to exceed 512), the carry signal is supplied to the latch circuit L _2.

Next, let's explain the operation of this carry accumulator AC ₂ . When the adder A ₂ no carry signal is obtained,
Switch SW ₁ is switched to adder A ₁ and latch circuit L
The latch content of ₁ starts at 221 and increases by 221. When the addition output of the adder A ₂ exceeds 512, that is, the addition output of the adding circuit A ₁ exceeds 429, the carry signal 1 is output from the adder A _2, which is supplied to the latch circuit L ₂ The switch SW ₁ is latched and the adder A ₂
Is switched to the side, and the adder A ₂ subtracts 429 from the content of the latch circuit L ₁ and adds 221 to it, that is, the content of the latch circuit L ₁ and 221+ (512−429) = 304. The binary output is added and the added output is supplied to the latch circuit L ₁ and latched, and then the switch SW ₁ is switched to the adder A ₁ side again. Thereafter, this operation is repeated.

Then, from the latch circuit L ₄ , the above-mentioned address value = (1024 × Fsc / Fc) · m + K = [1024 × (910/4) × Fh / 858Fh] × m + K = [271+ (221/429) × m + K = An address signal of 271 × m + (221/429) × m + K is obtained, and sinROM (31) and cosR are obtained respectively.
OM (32).

Thus, the sinROM (31) outputs U-axis digital color subcarrier data, and the cosROM (32) outputs V-axis digital color subcarrier data.

H Effect of the Invention According to the clock signal generating circuit of the present invention described above, the PLL
In the configuration, the clock signal is obtained from the variable oscillation whose oscillation frequency is controlled based on the phase comparison of the reference burst signal and the color subcarrier signal generated in synchronization with the reference burst signal. However, it is possible to obtain a stable clock signal having a frequency that is not an integer multiple of the color subcarrier frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock signal generation circuit according to the present invention, and FIGS. 2 and 3 are block lines showing examples of digital color subcarrier signal generation circuits of PAL system and NTSC system, respectively. It is a figure. (2) is a sync separation circuit, (3) is a burst extraction circuit,
(4) PLL, (5) phase comparator, (6) low-pass filter, (7) variable oscillator, (8) digital color subcarrier signal generation circuit, (9) D / A converter, (10) is a low-pass filter, (14) is an encoder, and (15) is an adder circuit.

Claims (1)

(57) [Claims] 1. A phase comparator to which a reference burst signal is supplied, and an oscillation frequency is controlled based on a comparison output of the phase comparator so that the oscillation frequency is an integral multiple of a horizontal frequency but an integral multiple of a color subcarrier frequency. A variable oscillator for generating a clock signal having a non-frequency, a digital color subcarrier signal generation circuit for outputting a digital color subcarrier signal by storing digital waveform data and supplying the clock signal as an address signal. A D / A converter supplied with the digital color subcarrier signal from the digital color subcarrier signal generation circuit and converted into an analog color subcarrier signal, the analog color subcarrier from the D / A converter A clock signal generation circuit characterized in that a carrier signal is supplied to the phase comparator for phase comparison with the reference burst signal.